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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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Tutorial: Methodologies and tools for embedded multisensory systems based on ARM cortex M processors

Tutorial: Methodologies and tools for embedded multisensory ...

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Proceedings of the international conference on Compilers, architectures and Synthesis for embedded systems (CASES)

作者： Zeljko Zilic Dept. ECE 3480 University Montreal QC Canada

Modern embedded systems require design methodologies that are productive, yet manage to harvest continuing innovations in embedded processor and sensing technologies. This course outlines techniques for mastering the design using the new tools and software abstractions based on ARM Cortex M processor family. Methodologies are outlined that enhance productivity in large-scale designs, while also employing the advanced hardware accelerators present in modern embedded processors. We then elaborate the ways to design and use platforms for networked systems that build on multi-sensor integration functions.

关键词： embedded systems Program processors Unified modeling language computer architecture Hardware Reliability

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Computational sprinting on a hardware/software testbed 13

Computational sprinting on a hardware/software testbed

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18th international conference on Architectural Support for Programming Languages and Operating systems, ASPLOS 2013

作者： Raghavan, Arun Emurian, Laurel Shao, Lei Papaefthymiou, Marios Pipe, Kevin P. Wenisch, Thomas F. Martin, Milo M.K. Dept. of Computer and Information Science University of Pennsylvania United States Dept. of Electrical Engineering and Computer Science University of Michigan United States Dept. of Mechanical Engineering University of Michigan United States

ISBN: (纸本)9781450318709

CMOS scaling trends have led to an inflection point where thermal constraints (especially in mobile devices that employ only passive cooling) preclude sustained operation of all transistors on a chip- a phenomenon called "dark silicon." Recent research proposed computational sprinting-exceeding sustainable thermal limits for short intervals-to improve responsiveness in light of the bursty computation demands of many media-rich interactive mobile applications. Computational sprinting improves responsiveness by activating reserve cores (parallel sprinting) and/or boosting frequency/ voltage (frequency sprinting) to power levels that far exceed the system's sustainable cooling capabilities, relying on thermal capacitance to buffer heat. Prior work analyzed the feasibility of sprinting through modeling and simulation. In this work, we investigate sprinting using a hardware/software testbed. First, we study unabridged sprints, wherein the computation completes before temperature becomes critical, demonstrating a 6.3× responsiveness gain, and a 6% energy efficiency improvement by racing to idle. We then analyze truncated sprints, wherein our software runtime system must intervene to prevent overheating by throttling parallelism and frequency before the computation is complete. To avoid oversubscription penalties (context switching inefficiencies after a truncated parallel sprint), we develop a sprint-aware task-based parallel runtime. We find that maximal-intensity sprinting is not always best, introduce the concept of sprint pacing, and evaluate an adaptive policy for selecting sprint intensity. We report initial results using a phase change heat sink to extend maximum sprint duration. Finally, we demonstrate that a sprint-and-rest operating regime can actually outperform thermally-limited sustained execution. Categories and Subject Descriptors C.1.4 [Parallel architectures]: mobile processors. Copyright © 2013 ACM.

关键词： Parallel architectures

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Deployment and Scheduling Synthesis for Mixed-Critical Shared-Memory Applications

Deployment and Scheduling Synthesis for Mixed-Critical Share...

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international conference and Workshop on Engineering of computer-Based systems

作者： Sebastian Voss Bernhard Schätz Fortiss GmbH Munich Germany

This paper presents an efficient approach for generating suitable system architectures for embedded systems efficiently. Thereby, we focus on a joint generation of schedules and deployment for mixed-criticality multicore architectures using shared memory. The presented approach computes task and message schedules that are optimized with respect to a global discrete time base. As part of the solution, our approach generates an optimized assignment of tasks to computation resources (cores) concerning local memory constraints of cores and criticality constraints of *** approach is integrated into the Auto FOCUS3 tool-chain, using a formally defined model of computation with explicit data-flow and discrete-time semantics to develop multi-criticality embedded systems. Our approach relies on a symbolic encoding scheme, based on a system model that is derived from the system architecture. This paper provides a formalization describing the scheduling problem as a satisfiability problem using boolean formulas and linear arithmetic constraints. A state-of-the-art satisfiability modulo theory (SMT) solver is used to compute the joint schedule and deployment for such architectures. This paper demonstrates that state-of-the art satisfiability modulo theory solvers can be used to efficiently compute (safety-oriented) deployments including real-time task and communication schedules for mixed-criticality applications.

关键词： Schedules Resource management Computational modeling Multicore processing Processor scheduling Scheduling

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Critical Infrastructure Protection V: 5th IFIP WG 11.10 international conference on Critical Infrastructure Protection, ICCIP 2011, Hanover, NH, USA

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2013年

作者： Jonathan W Butts Sujeet Shenoi

ISBN: (纸本)9783642270413

The information infrastructure---comprising computers, embedded devices, networks and software systems---is vital to day-to-day operations in every sector: information and telecommunications, banking and finance, energy, chemicals and hazardous materials, agriculture, food, water, public health, emergency services, transportation, postal and shipping, government and defense. Global business and industry, governments, indeed society itself, cannot function effectively if major components of the critical information infrastructure are degraded, disabled or destroyed. Critical Infrastructure Protection V describes original research results and innovative applications in the interdisciplinary field of critical infrastructure protection. Also, it highlights the importance of weaving science, technology and policy in crafting sophisticated, yet practical, solutions that will help secure information, computer and network assets in the various critical infrastructure sectors. Areas of coverage include: Themes and Issues, Control systems Security, Infrastructure Security, and Infrastructure modeling and simulation. This book is the 5th volume in the annual series produced by the international Federation for Information Processing (IFIP) Working Group 11.10 on Critical Infrastructure Protection, an international community of scientists, engineers, practitioners and policy makers dedicated to advancing research, development and implementation efforts focused on infrastructure protection. The book contains a selection of 14 edited papers from the 5th Annual IFIP WG 11.10 international conference on Critical Infrastructure Protection, held at Dartmouth College, Hanover, New Hampshire, USA in the spring of 2011. Critical Infrastructure Protection V is an important resource for researchers, faculty members and graduate students, as well as for policy makers, practitioners and other individuals with interests in homeland security. Jonathan Butts is an Assistant Professor of Compute

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SPM-Sieve: A Framework for Assisting Data Partitioning in Scratch Pad Memory Based systems

SPM-Sieve: A Framework for Assisting Data Partitioning in Sc...

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international conference on Compilers, architectures and Synthesis for embedded systems

作者： Prasenjit Chakraborty Preeti Ranjan Panda Intel Technology India Pvt. Ltd. Department of Computer Science & Engineering Indian Institute of Technology Delhi

ISBN: (纸本)9781479913992

Modern system architectures sometimes include scratch pad memories (SPM) in their memory hierarchy to take advantage of their simpler design, in an attempt to meet the system area, performance, and power budget. These systems employing SPM can be broadly categorized as: (a) cacheless systems with only SPM, (b) hybrid systems with both cache and SPM, and (c) reconfigurable systems with the provision to reconfigure local memory as either cache, SPM, or a combination of the two. However SPM based systems have needed larger efforts spent on their programming, mainly due to allocating data and orchestrating data transfers explicitly by software. Tight product development cycles require faster development and porting of diverse applications to multiple SPM based architectures. In this paper we present SPM-Sieve, a profile-based tool and framework targeted for SPM based architectures that generates partitioning decisions of the first level memory in the system hierarchy, and suggests object mapping amongst the memory partitions without resorting to detailed simulation of all configurations. This is done by natively executing an application and using minimal target architecture specification, which not only provides early information influencing data organization in the application, but also provides a foundation for other more sophisticated algorithms to produce optimized allocations. We demonstrate the utility and generality of SPM-Sieve by evaluating it on a large number of SPEC2000 benchmarks targeted for a 128KB first level memory. We evaluate its effectiveness by performing simulation studies comparing the partition suggested by the tool against varying partition sizes, and observe that its suggestions are very competitive for SPM based architectures with and without caches.

关键词： Algorithm Design Performance Memory Allocation Software Cache Scratch Pad Memory

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Virtual prototyping of multiprocessor architectures using the open virtual platform

Virtual prototyping of multiprocessor architectures using th...

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international conference on computer Applications Technology (ICCAT)

作者： Wijdene Rekik Mouna Ben Said Nader Ben Amor Mohamed Abid ENIS CES Laboratory University of Sfax Sfax Tunisia

ISBN: (纸本)9781467352840

The complexity of System on Chip (SoC) design is increasing continuously with the use of MultiProcessor System on Chip (MPSoC) architectures. Mastering the complexity of these systems with a typical co-design workflow is really recommended. As such, computer aided design tools are needed to alleviate the task of designers. There is a lack of co-design tools that support multiprocessor architectures with Operating System (OS) support. Virtual platforms enable us to discover the interactive design space exploration at early stage in the design. They make designing embedded systems less tedious and elevate the low technical details to manage systems complexity and reduce time to market. In this paper, we present an exploration of the Open Virtual Platform (OVP) capabilities for multiprocessor architectures simulation. We particularly focus on the inter-processor communication facilities. We illustrate this study by a set of homogeneous and heterogeneous multiprocessor architectures with different memory hierarchies and peripherals followed by a run of several applications. We also integrate the use of OS to permit workload distribution among processors using several case studies to validate our system.

关键词： Program processors Linux Hardware Multicore processing Complexity theory

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Aspect-Oriented modeling of Railway Cyber Physical systems Based on the Extension of AADL

Aspect-Oriented Modeling of Railway Cyber Physical Systems B...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Lichen Zhang Shanghai Key Laboratory of Trustworthy Computing East China Normal University Shanghai China

ISBN: (纸本)9781479909735

The railway system has developed from a purely physical system based on the laws of mechanics and chemistry, to a more sophisticated Cyber Physical System which embeds electronic components and control systems to improve performance and safety. Therefore, the system in the railway is a typical CPS, which is called the Railway Cyber-Physical System. The railway cyber physical system combines traditional state-based discrete control model and continuous models based on physical environments expressed by the classic differential equations which are the most suitable model for modeling physical system. Architecture Analysis and Design Language (AADL) is a standard architecture description language to design and evaluate software architectures for embedded systems already in use by a number of organizations around the world. In this paper we present our current effort to extend AADL to include new features for separation of concerns of railway cyber physical systems, we extend AADL in spatial aspect, dynamic continous aspect, physical world modeling aspect, formal specification aspect. Finally, we illustrate the proposed method via an example of railway cyber physical system.

关键词： Rail transportation Mathematical model Object oriented modeling Computational modeling Control systems Safety computer architecture

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Task sampling: computer architecture simulation in the many-core era

Task sampling: Computer architecture simulation in the many-...

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international conference on Parallel Architecture and Compilation Techniques (PACT)

作者： Thomas Grass Barcelona Supercomputing Center Universitat Politécnica de Catalunya Barcelona Spain

ISBN: (纸本)9781479910205

Chip Multi-Processors (CMPs) are evolving towards ever increasing core counts. Task-based programming models are a promising candidate for exploiting the parallelism offered by these machines. simulation, the prevailing design methodology in computer architecture, is prohibitively time consuming, when it comes to CMPs featuring 1000s of cores. Sampled simulation is a standard technique for reducing simulation time for single-threaded architectures. Recently, these techniques have been extended to allow for simulation of multi-threaded systems. However, they have not been assessed for dynamically scheduled multi-threaded programs. In this work we use the OmpSs programming model [4]. OmpSs, an extension of OpenMP, allows to declare code blocks as tasks and to specify data consumed and produced by each task. The runtime environment executes tasks, potentially out of program order, on available cores, similar to the out-oforder execution in a superscalar processor.

关键词： Computational modeling Analytical models computer architecture Programming Accuracy Benchmark testing Electronic mail

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Efficient Building Automation simulation Using System on Chip simulation Techniques

Efficient Building Automation Simulation Using System on Chi...

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26th international conference on Architecture of Computing systems 2013

作者： Joseph Wenninger Jan Haase Institute of Computer Technology Vienna University of Technology

The design of building automation systems is a complex task. As it has many similarities to the design of embedded systems, this article proposes the use of simulation techniques taken from circuit design for the development of building automation systems. As an example for the simulation framework being developed a simulation of the energy consumptions of flats and their inhabitants is shown, implemented in the hardware description language SystemC AMS.

关键词： Buildings Time domain analysis Time varying systems Home appliances Computational modeling Home automation Heating

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simulation Testing of a Real-Time Heuristic Scheduler with Automotive Benchmarks

Simulation Testing of a Real-Time Heuristic Scheduler with A...

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international conference on computer modeling and simulation, UKSIM

作者： James Docherty Alex Bystrov Alex Yakovlev School of EEE Newcastle University Newcastle upon Tyne UK

ISBN: (纸本)9781467364211

embedded systems are becoming ever more pervasive in our society, with most routine daily tasks now involving their use in some form. These devices can range from simple low-cost chips to expensive and complex systems and are a major cost driver in the equipment design phase. Therefore reducing this cost by substitution of advanced processors for more simple devices, while retaining reliability, would be beneficial in terms of cost reduction and system flexibility. This paper investigates the simulation of a heuristic based scheduling algorithm for real-time systems capable of managing complex jobs based on an ARM Cortex M3 architecture simulated in MATLAB.

关键词： Sparks Real-time systems Vehicles Engines Benchmark testing Program processors Schedules

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