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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

共 2831 条记录，以下是101-110 订阅

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Image quantisation on a massively parallel embedded processor

引用

international conference on embedded computer systems - architectures, modeling and simulation

作者： Jacobs, Jan van Engelen, Leroy Kuper, Jan Smit, Gerard J. M. Oce Technol BV POB 101 NL-5900 MA Venlo Netherlands Univ Twente NL-7500 AE Enschede Netherlands

ISBN: (纸本)9783540736226

Recent advances in embedded processing architectures allow for new powerful algorithms, which exploit the intrinsic parallelism present in image processing applications. This paper describes the results of the mapping process of stochastic image quantisation on a massively parallel processor. The problem can be modeled in a parallel way. Despite the fact that the implementation is 10 bound, good speedups are achieved (16 x compared to a standard image processing package running on a Pentium processor).

关键词： Vector quantization

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Balanced Application-Specific Processor System for Efficient SIFT-Feature Detection 17

Balanced Application-Specific Processor System for Efficient...

引用

17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Hartig, Julian Paya-Vaya, Guillermo Mentzer, Nico Blume, Holger Leibniz Univ Hannover Inst Microelect Syst Appelstr 4 D-30167 Hannover Germany

ISBN: (纸本)9781538634370

Due to its computational complexity, the Scale-Invariant Feature Transform (SIFT) algorithm poses a challenge for use in embedded applications. To meet real-time at low power, hardware acceleration is necessary. This paper presents an FPGA-based balanced processor system for real-time SIFT feature detection, containing a dedicated hardware coprocessor coupled to a custom VLIW soft-core processor using a FIFO memory. The coprocessor calculates the scale-space and performs the extrema detection for the extraction of feature candidates, whereas the VLIW soft-core processor performs sub-pixel localization and stability checks to get stable SIFT-features. The system achieves a peak frame rate of up to 338 fps on 1,024x376 px images at less than 3 W on a Xilinx Virtex-6 FPGA. The filters within the Gaussian pyramid operate in a time-multiplexed scheme on clock frequencies up to 400 MHz. Furthermore, this paper presents a comprehensive design space exploration, evaluating architectural performance, hardware resources and power consumption trade-offs as well as exposing performance-balanced and pareto-optimal design variants.

关键词： Feature extraction Hardware Field programmable gate arrays Coprocessors VLIW Throughput Real-time systems Field programmable gate arrays Coprocessors Very long instruction word computer hardware real-time systems Feature extraction Throughput PROCESSOR feature detections soft-core

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The Design Space of the Number Theoretic Transform: a Survey 17

The Design Space of the Number Theoretic Transform: a Survey

引用

17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Valencia, Felipe Khalid, Ayesha O'Sullivan, Elizabeth Regazzoni, Francesco USI ALaRI Lugano Switzerland QUB CSIT Belfast North Ireland

ISBN: (纸本)9781538634370

The Number Theoretic Transform (NTT) is a necessary part of most Lattice-based cryptographic schemes. In particular, it offers an efficient means to achieve polynomial multiplication within the more efficient ring-based schemes. The NTT is also a crucial component which needs to be implemented in a critical way, since it is often the bottle-neck and the most resource consuming block of the whole design. As a result, the NTT is an appealing target for exploring different architectures and design trade-offs. In this paper, we compare various optimization strategies applied to maximize the performance or to reduce the resource utilization. Our analysis covers general purpose processors as well as dedicated hardware implemented on reconfigurable platforms and on ASIC. Previously explored design strategies range from the traditional computation where the multiplicative factors (called twiddle factors) are calculated on-the-fly versus memory trade-off exploration (using memory to store pre-computed twiddle factors), to the use of different butterfly designs for implementing the Fast Fourier Transform and its inverse in software, or the sharing of resources for hardware implementations of the forward and inverse NTT. The problem of side channel resistance is also addressed, discussing designs which are robust against power analysis attacks.

关键词： Cryptography Hardware Discrete Fourier transforms Lattices Software Resistance discrete Fourier transform computer hardware cryptography crystal lattices computer software Resource utilization computer programs Transform power analysis Inverse

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Dynamic Task Mapping onto Multi-Core architectures through Stream Rewriting

Dynamic Task Mapping onto Multi-Core Architectures through S...

引用

13th international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Middendorf, Lars Zebelein, Christian Haubelt, Christian Univ Rostock Inst Appl Microelect & Comp Engn Rostock Germany

ISBN: (纸本)9781479901036

Task graphs provide an efficient model of computation for specification, analysis, and implementation of concurrent applications. In this paper, we present a novel approach for mapping the class of series-parallel task graphs onto multi-core architectures based on pattern matching. Both the topology of the graph and the state of the tasks are encoded as a stream of tokens, which is iteratively rewritten at multiple positions in parallel. Hence, our technique is most useful for compute-intensive applications that must adapt to frequently varying and unpredictable workload at runtime. Several complex examples have been evaluated on a multi-core architecture and the experimental results show the effectiveness of our approach.

关键词： graph theory multiprocessing systems pattern matching processor scheduling rewriting systems

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Architectural Low-Power Design Using Transaction-Based System modeling and simulation 14

Architectural Low-Power Design Using Transaction-Based Syste...

引用

international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Mischkalla, Fabian Mueller, Wolfgang Univ Paderborn C LAB D-33102 Paderborn Germany

ISBN: (纸本)9781479937707

Energy efficiency drives the development of more and more complex low-power designs. Based on dynamic power management techniques, multiple voltage islands as well as a huge amount of power states are specified that have to be tested carefully. In this context, low-power design should start at an early stage using state-of-the-art system-level modeling and simulation techniques. However, there is neither a programming language nor any modeling standard that reflects variable power together with its functional side effects in a well-suited abstract manner. To overcome this limitation, we present a modeling approach on top of SystemC TLM to capture low-power design characteristics at electronic system-level. We demonstrate the usability by means of an existing open-source low-power design. The experimental results show that appropriate TLM instrumentation cause only minimal simulation overhead, but offer sufficient details to identify common low-power design errors.

关键词： SystemC/TLM IEEE 1801-2013 (UPF) Power Intent simulation & Validation

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Multi-Domain SystemC Model of 128-Channel Time-Multiplexed Neural Interface Front-End 15

Multi-Domain SystemC Model of 128-Channel Time-Multiplexed N...

引用

international conference on embedded computer systems architectures modeling and simulation

作者： Wirianto, Kiki Zjajo, Amir Galuzzi, Carlo van Leuken, Rene Delft Univ Technol Circuits & Syst Grp Delft Netherlands Maastricht Univ BMI Res Grp Maastricht Netherlands

ISBN: (纸本)9781467373111

A SystemC Multi-Domain Virtual Prototype (MDVP) framework provides multi-domain system integration of multi-electrode neural interface and a fast validation time, offering more efficient design process. In this paper, we propose efficient neuron cell, neuron tissue, and multi-channel neural interface front-end models implemented in a SystemC MDVP framework, which supports chemical, biological, and electrical domain modeling and simulation. The proposed model offers advantages for designers not only in reducing the design time, but also regarding the system integration. We make use of 8x16-channel front-end recording circuits to implement a 128-channel time-multiplexed neural interface front-end model. These models are verified with realistic simulation settings and appropriate input signals.

关键词： SystemC MDVP modeling multi-channel front-end neural interface

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SimGate: Full-system, cycle-close simulation of the Stargate sensor network intermediate node

SimGate: Full-system, cycle-close simulation of the Stargate...

引用

6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Wen, Ye Gurun, Selim Chohan, Navraj Wolski, Rich Krintz, Chandra Univ Calif Santa Barbara Dept Comp Sci Santa Barbara CA 93106 USA

ISBN: (纸本)1424401550

We present SimGate - a full-system simulator for the Stargate intermediate-level, resource-constrained, sensor network device. We empirically evaluate the accuracy and performance of the system in isolation as well as coupled with simulated Mica2 motes. Our system is functionally correct and achieves accurate cycle estimation (i.e. cycle-close). Moreover, the overhead of simulated execution is modest with respect to previously published work.

关键词： Sensor nodes

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An Emulation-Based Real-Time Power Profiling Unit for embedded Software

An Emulation-Based Real-Time Power Profiling Unit for Embedd...

引用

international conference on embedded computer systems -architectures, modeling and simulation

作者： Genser, Andreas Bachmann, Christian Haid, Josef Steger, Christian Weiss, Reinhold Graz Univ Technol Inst Tech Informat A-8010 Graz Austria Infineon Technologies Austria AG Design Ctr Graz Villach Austria

ISBN: (纸本)9781424445011

The power consumption of battery-powered and energy-scavenging devices has become a major design metric for embedded systems. Increasingly complex software applications as well as rising demands in operating times while having restricted power budgets make power-aware system design indispensable. In this paper we present an emulation-based power profiling approach allowing for real-time power analysis of embedded systems. Power saving potential as well as power-critical events can be identified in much less time compared to power simulations. Hence, the designer can take countermeasures already in early design stages, which enhances development efficiency and decreases time-to-market. Accuracies achieved for a deep sub-micron smart-card controller are greater than 90% compared to gate-level simulations.

关键词： embedded systems

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SPynq: Acceleration of Machine Learning Applications over Spark on Pynq 17

SPynq: Acceleration of Machine Learning Applications over Sp...

引用

17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Kachris, Christoforos Koromilas, Elias Stamelos, Ioannis Soudris, Dimitrios NTUA Inst Commun & Comp Syst ICCS Athens Greece Natl Tech Univ Athens Dept Elect & Comp Engn Athens Greece

ISBN: (纸本)9781538634370

Spark is one of the most widely used frameworks for data analytics that offers fast development of applications like machine learning and graph computations in distributed systems. In this paper, we present SPynq: A framework for the efficient utilization of hardware accelerators over the Spark framework on heterogeneous MPSoC FPGAs, such as Zynq. Spark has been mapped to the Pynq platform and the proposed framework allows the seamlessly utilization of the programmable logic for the hardware acceleration of computational intensive Spark kernels. We have also developed the required libraries in Spark that hides the accelerator's details to minimize the design effort to utilize the accelerators. A cluster of 4 nodes (workers) based on the all-programmable MPSoCs has been implemented and the proposed platform is evaluated in a typical machine learning application based on logistic regression. The logistic regression kernel has been developed as an accelerator and incorporated to the Spark. The developed system is compared to a high-performance Xeon cluster that is typically used in cloud computing. The performance evaluation shows that the heterogeneous accelerator-based MpSoC can achieve up to 2.3x system speedup compared with a Xeon system (with 90% accuracy) and 20x better energy-efficiency. For embedded application, the proposed system can achieve up to 40x speedup compared to the software only implementation on low-power embedded processors and 30x lower energy consumption.

关键词： Sparks Hardware Program processors Libraries Machine learning Field programmable gate arrays Cloud computing Field programmable gate arrays Program processors sparks Cloud Computing computer hardware Artificial Intelligence Machine Learning Libraries Accelerators design effort Performance Evaluation hardware accelerator

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Virtual Environment for Developing Real-Time Image Processing for Vehicle Control 17

Virtual Environment for Developing Real-Time Image Processin...

引用

17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Kitrungrotsakul, Yuranan Tanaka, Kiyofumi Hashimoto, Masanobu Onishi, Shuichi Japan Adv Inst Sci & Technol Sch Informat Sci Nomi Japan WITZ Corp Kyoto Japan

ISBN: (纸本)9781538634370

Virtual prototyping is an alternative way to simulate the real product without the physical object. The product is created in simulator before making a physical prototype. In this research, a vehicle controller is the target system for prototyping. The vehicle navigation system is the target program to execute in a vehicle controller system. One of critical factors in a vehicle controller is response time. Thus, this paper aims to create the virtual prototype with real response time for a vehicle controller. The hardware accelerators are used to improve system performance. The hardware accelerators are implemented into two bases, which are GPU and programmable logic (PL). In addition, the overclocking method is applied to increase the operating speed in GPU hardware accelerator. The result from improvement is evaluated in terms of execution time per frame, which is the metric for measurement of the ability of real-time response. To achieve real-time response, the execution time per frame must be below 33.33 ms. The GPU based version achieves run-time response by running at 14.43 ms per frame. The PL based version runs at 16.332 ms per frame, which achieves run-time response.

关键词： virtual prototype hardware accelerator GPU programmable logic embedded system

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