In areas such as psychology and neuroscience a common approach to study human behavior has been the development of theoretical models of cognition. In fields such as artificial intelligence, these cognitive models are...
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In areas such as psychology and neuroscience a common approach to study human behavior has been the development of theoretical models of cognition. In fields such as artificial intelligence, these cognitive models are usually translated into computational implementations and incorporated into the architectures of intelligent autonomous agents (AAs). The main assumption is that this design approach contributes to the development of intelligent systems capable of displaying very believable and human-like behaviors. Decision Making is one of the most investigated and computationally implemented cognitive functions. The literature reports several computational models designed to allow AAs to make decisions that help achieve their personal goals and needs. However, most models disregard crucial aspects of human decision making such as other agents' needs, ethical values, and social norms. In this paper, we propose a biologically inspired computational model of Moral Decision Making (MDM). This model is designed to enable AAs to make decisions based on ethical and moral judgment. The simulation results demonstrate that the model helps to improve the believability of virtual agents when facing moral dilemmas.
In recent years the area of High Performance Computing (HPC) has received an outstanding support both from the users as well as the computer system designers. This support is mainly due to the increase of the complexi...
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ISBN:
(纸本)9781479903719
In recent years the area of High Performance Computing (HPC) has received an outstanding support both from the users as well as the computer system designers. This support is mainly due to the increase of the complexity and density of the data processing of some of the advanced research areas. These areas include but not limited to, the climate modeling, weather forecasting, and performance measurement and improving precision of the nuclear weapon systems as well as space programs. This rise in complexity would impose additional pressure on the clients to demand for further improvements on system features such as speed, reliability, performance, fault tolerance, compatibility, size and cost. This is one of the determining factors that encourages our researchers to model new architectures in the areas of HPC in order to satisfy the clients' scientific and engineering requirements. With this motivation in mind the author has introduced a new architecture which is coined as Master -Slave Multi-Super Hypercube DXTree architecture ((MS) 2 HDX - T). For this architecture the total system cost through mathematical modeling and simulation is compared with similar parameters in the existing HPC systems. The result highlights the advantages or otherwise of the proposed architecture from scientific research and/or commercial point of view.
Public sensing is an application in which sensory systemsembedded in smart devices, vehicles, residential and public spaces form a collective cloud of data sources from which multi-owned access points realize end-use...
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Public sensing is an application in which sensory systemsembedded in smart devices, vehicles, residential and public spaces form a collective cloud of data sources from which multi-owned access points realize end-users' service requests. This conception can be further extended under the umbrella of integrated RFID-Sensor Networks (RSNs) to include RFID systems. Such a configuration is heterogeneous by nature and faces many challenges in terms of data delivery and resource management. In this paper, we represent a Reciprocal Public Sensing (RPS) scheme for integrated RSN architectures. Our scheme incorporates heuristic solutions for static sensors and mobile data collectors, in addition to a reciprocal agreement for data exchange over the tiers of the proposed architecture adhering to the social welfare of the network as a whole. We provide simulation results showing how RPS outperforms other data delivery schemes in terms of minimizing delay, packet loss, and energy consumption, in addition to prolonging the overall network lifetime.
We will present our approach to remote experimentation. The system provides access to a well-maintained, high-fidelity hardware-in-the-loop simulation of a flight-validated hexacopter with an autopilot. The whole syst...
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We will present our approach to remote experimentation. The system provides access to a well-maintained, high-fidelity hardware-in-the-loop simulation of a flight-validated hexacopter with an autopilot. The whole system has already received the Special Flight Operations Certificate (SFOC) and was used during several missions such as sensor deployment on icebergs, terrain mapping, and structural integrity checks. The system is easily accessible to remote users, and in active use for research and teaching. Users will be able to connect through a remote connection and gain access to the system. Several scenarios are available which mimic different flight conditions and flight paths. The platform supports research from the operating system up to arbitrary application software and thus enables case studies on software and system design, modeling, programming, validation, and verification, as well as robotic operations, mission planning, and simultaneous localization and mapping.
Recently, graphics processing units (GPUs) have opened up new opportunities for speeding up general-purpose parallel applications due to their massive computational power and up to hundreds of thousands of threads ena...
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ISBN:
(纸本)9781450319003
Recently, graphics processing units (GPUs) have opened up new opportunities for speeding up general-purpose parallel applications due to their massive computational power and up to hundreds of thousands of threads enabled by programming models such as CUDA. However, due to the serial nature of existing micro-architecture simulators, these massively parallel architectures and workloads need to be simulated sequentially. As a result, simulating GPGPU architectures with typical benchmarks and input data sets is extremely time-consuming. This paper addresses the GPGPU architecture simulation challenge by generating miniature, yet representative GPGPU kernels. We first summarize the static characteristics of an existing GPGPU kernel in a profile, and analyze its dynamic behavior using the novel concept of the divergence flow statistics graph (DFSG). We subsequently use a GPGPU kernel synthesizing framework to generate a miniature proxy of the original kernel, which can reduce simulation time significantly. The key idea is to reduce the number of simulated instructions by decreasing per-thread iteration counts of loops. Our experimental results show that our approach can accelerate GPGPU architecture simulation by a factor of 88X on average and up to 589X with an average IPC relative error of 5.6%.
A novel verification methodology, combining the two new techniques of Live Verification and Processor State Transfer, is introduced to Architecture Description Language (ADL) based processor design. The proposed Just-...
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ISBN:
(纸本)9781467322973;9781467322966
A novel verification methodology, combining the two new techniques of Live Verification and Processor State Transfer, is introduced to Architecture Description Language (ADL) based processor design. The proposed Just-in-Time Verification significantly accelerates the simulation-based equivalence check of the register-transfer and instruction-set level models, generated from the ADL-based specification. This is accomplished by omitting redundant simulation steps occurring in the conventional architecture debug cycle. The potential speedup is demonstrated with a case study, achieving an acceleration of the debug cycle by 660x.
MapReduce is a very popular programming model to support parallel and distributed large-scale data processing. There have been a lot of efforts to implement this model on commodity GPU-based systems. However, most of ...
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MapReduce is a very popular programming model to support parallel and distributed large-scale data processing. There have been a lot of efforts to implement this model on commodity GPU-based systems. However, most of these implementations can only work on a single GPU. And they can not be used to process large-scale datasets. In this paper, we present a new approach to design the MapReduce framework on GPU clusters for handling large-scale data processing. We have used Compute Unified Device architectures (CUDA) and MPI parallel programming models to implement this framework. To derive an efficient mapping onto GPU clusters, we introduce a two-level parallelization approach: the inter node level and intra node level parallelization. Furthermore in order to improve the overall MapReduce efficiency, a multi-threading scheme is used to overlap the communication and computation on a multi-GPU node. Compared to previous GPU-based MapReduce implementations, our implementation, called GCMR, achieves speedups up to 2.6 on a single node and up to 9.1 on 4 nodes of a Tesla S1060 quad-GPU cluster system for processing small datasets. It also shows very good scalability for processing large-scale datasets on the cluster system.
Implementation of digital controllers in embedded environment suffers from the inherent problems associated with analog-digital signals interfacing in hard real-time, therefore, the control algorithms are invariantly ...
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ISBN:
(纸本)9781467329064
Implementation of digital controllers in embedded environment suffers from the inherent problems associated with analog-digital signals interfacing in hard real-time, therefore, the control algorithms are invariantly subjected to approximations. This paper presents a novel technique for implementation of an efficient FPGA based digital Proportional-Integral-Derivative (PID) controller for the motion control of a permanent magnet DC motor. The implementation technique circumnavigates the problem of interfacing analog and digital systems in real-time. The controller is used in a speed control loop. The hardware implementation has been done on a Xilinx Spartan 3 FPGA chip. A novel technique has been adopted for the generation of the control input as a PWM signal for controlling the motor driver circuit and decoding the optical encoder data for using it for the speed feedback in the PID control loop. The VHDL algorithm for the proposed implementation has also been presented in this paper. A comparison of the experimental results with the Matlab ® based simulation shows the effectiveness of the proposed method.
This paper focuses on the design of an on-chip communication system for control architectures used in RF (Radio Frequency) transceivers. Continuous developments and enhancements of RF transceivers, especially of smart...
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ISBN:
(纸本)9781467322973;9781467322966
This paper focuses on the design of an on-chip communication system for control architectures used in RF (Radio Frequency) transceivers. Continuous developments and enhancements of RF transceivers, especially of smart transceivers supporting multi-mode standards, led to new and complex SoC (System-on-Chip) designs. These designs are defined by a distributed controlling concept using several processing modules which are connected over an advanced communication system. Based on the requirements and restrictions of this communication system an application-specific NoC (Network-on-Chip) is presented and analyzed in this work.
One of the major design challenges of Network-on-Chip interconnect is the storage buffers. They occupy a significant portion of the system's area and so they are considered as main "power-hungry" compone...
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ISBN:
(纸本)9781479905478
One of the major design challenges of Network-on-Chip interconnect is the storage buffers. They occupy a significant portion of the system's area and so they are considered as main "power-hungry" components. Deciding the appropriate buffers size and implementation in these systems is the key technique for increasing system performance and also for reducing overall area and power consumption. However, this goal is very hard to achieve with traditional design approaches, where design decisions of the main architectural parameters are generally made with slow and inaccurate software simulation or theoretical modeling. In order to quickly capture and decide the optimal buffers size and the whole system behavior, we propose in this work an efficient design method for Network-on-Chip architecture based on a novel run-time monitoring mechanism (RMM). The system monitors the traffic flow at different system's resources and sends the monitored run-time traffic information to a specialized controller. In addition, our proposed design method allows to easily compute optimal architecture hardware parameters (i.e Buffer size) and allocate the appropriate values on demand to satisfy the requirements of any given application. The RMM mechanism was designed in hardware and integrated into our NoC system (PNoC). From the evaluation results, we conclude that the system performance in terms of execution time was about 27% better when compared with traditional design methods over several benchmark programs.
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