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Optimization Techniques for Dimensionally Truncated Sparse Grids on Heterogeneous systems

Optimization Techniques for Dimensionally Truncated Sparse G...

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Euromicro conference on Parallel, Distributed and Network-Based Processing

作者： Andrei Deftu Alin Murarasu Technische Universität München Germany

Given the existing heterogeneous processor landscape dominated by CPUs and GPUs, topics such as programming productivity and performance portability have become increasingly important. In this context, an important question refers to how can we develop optimization strategies that cover both CPUs and GPUs. We answer this for fastsg, a library that provides functionality for handling efficiently high-dimensional functions. As it can be employed for compressing and decompressing large-scale simulation data, it finds itself at the core of a computational steering application which serves us as test case. We describe our experience with implementing fastsg's time critical routines for Intel CPUs and Nvidia Fermi GPUs. We show the differences and especially the similarities between our optimization strategies for the two architectures. With regard to our test case for which achieving high speedups is a "must'" for real-time visualization, we report a speedup of up to 6.2x times compared to the state-of-the-art implementation of the sparse grid technique for GPUs.

关键词： Optimization Instruction sets Graphics processing units computer architecture Vectors Programming Computational modeling

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Out-Of-Order Execution of Synchronous Data-Flow Networks

Out-Of-Order Execution of Synchronous Data-Flow Networks

引用

international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Baudisch, Daniel Brandt, Jens Schneider, Klaus Univ Kaiserslautern Dept Comp Sci Embedded Syst Grp D-67663 Kaiserslautern Germany

ISBN: (纸本)9781467322973;9781467322966

Data flow process networks (DPNs) have been introduced as a convenient model of computation for distributed and asynchronous systems since each process node can work independently of the other nodes, i.e. without the need of a global coordination. Synchronous and cyclo-static data flow process networks even allow to derive at compile-time efficient static schedules that allow one to run these systems with an efficient use of available resources, e. g. in embedded systems. Single process nodes of DPNs are stream-based computing devices that transform input streams to uniquely defined corresponding output streams such that single values of the output streams are computed as soon as sufficient input values are available. In this sense, they are related to the execution of an instruction stream by a conventional microprocessor. In this paper, we show how out-of-order execution that has been introduced for the efficient use of multiple functional units in microprocessors can also be used for the implementation of DPNs on multiprocessors. This way, the implementation of DPNs on multiprocessors allows one to optimize the throughput of single process nodes, and as shown by our experiments, also of the entire DPN.

关键词： NAD Legal Executions instruction flow Multiprocessor macroprocessor output stream data flow streams rivers Ganglia

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Adaptive Processor Architecture - Invited Paper

Adaptive Processor Architecture - Invited Paper

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international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Huebner, Michael Goehringer, Diana Tradowsky, Carsten Henkel, Joerg Becker, Juergen Ruhr Univ Bochum Chair Embedded Syst Informat Technol ESIT Bochum Germany Karlsruhe Inst Technol KIT Inst Data Proc & Elect IP E Karlsruhe Germany Karlsruhe Inst Technol KIT Inst Informat Proc Technol ITV Karlsruhe Germany Karlsruhe Inst Technol KIT 4Chair Embedded Syst CES Karlsruhe Germany

ISBN: (纸本)9781467322973;9781467322966

This paper introduces a novel methodology to adapt the microarchitecture of a processor at run-time. The goal is to tailor the internal architecture to the requirements of an application and the data to be processed. The latter parameter is normally not known at design time. This leads to the development of more general purpose processors which are capable to handle the data to be processed in any case. With the novel approach which keeps the microarchitecture of a processor flexible, the processor can start as a general purpose device and end up with a specific parameterization, comparable with application specific processor architectures. Furthermore, the increased degree of freedom which is enabled through the approach for a novel quality of processors is described.

关键词： Dynamic and partial processor reconfiguration FPGA internal configuration access port (lCAP) processor adaptation microarchitecture

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Automated, retargetable back-annotation for host compiled performance and power modeling 13

Automated, retargetable back-annotation for host compiled pe...

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international conference on Hardware/Software Codesign and System Synthesis (CODES)

作者： Suhas Chakravarty Zhuoran Zhao Andreas Gerstlauer Electrical and Computer Engineering The University of Texas at Austin

ISBN: (纸本)9781479914173

With traditional cycle-accurate or instruction-set simulations of processors often being too slow, host-compiled or source-level software execution approaches have recently become popular. Such high-level simulations can achieve order of magnitude speedups, but approaches that can achieve highly accurate characterization of both power and performance metrics are lacking. In this paper, we propose a novel host-compiled simulation approach that provides close to cycle-accurate estimation of energy and timing metrics in a retargetable manner, using flexible, architecture description language (ADL) based reference models. Our automated flow considers typical front- and back-end optimizations by working at the compiler-generated intermediate representation (IR). Path-dependent execution effects are accurately captured through pairwise characterization and backannotation of basic code blocks with all possible predecessors. Results from applying our approach to PowerPC targets running various benchmark suites show that close to native average speeds of 2000 MIPS at more than 98% timing and energy accuracy can be achieved.

关键词： Timing Program processors Computational modeling Accuracy Optimization Estimation Pipelines

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An Efficient Asymmetric Distributed Lock for embedded Multiprocessor systems

An Efficient Asymmetric Distributed Lock for Embedded Multip...

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international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Rutgers, Jochem H. Bekooij, Marco J. G. Smit, Gerard J. M. Univ Twente Dept EEMCS NL-7500 AE Enschede Netherlands

ISBN: (纸本)9781467322973

Efficient synchronization is a key concern in an embedded many-core system-on-chip (SoC). The use of atomic read-modify-write instructions combined with cache coherency as synchronization primitive is not always an option for shared-memory SoCs due to the lack of suitable IP. Furthermore, there are doubts about the scalability of hardware cache coherency protocols. Existing distributed locks for NUMA multiprocessor systems do not rely on cache coherency and are more scalable, but exchange many messages per lock. This paper introduces an asymmetric distributed lock algorithm for shared-memory embedded multiprocessor systems without hardware cache coherency. Messages are exchanged via a low-cost inter-processor communication ring in combination with a small local memory per processor. Typically, a mutex is used over and over again by the same process, which is exploited by our algorithm. As a result, the number of messages exchanged per lock is significantly reduced. Experiments with our 32-core system show that when having locks in SDRAM, 35% of the memory traffic is lock related. In comparison, our solution eliminates all of this traffic and reduces the execution time by up to 89%.

关键词： Locks Cache Coherence Multiprocessor Messages execution time Scalability Traffic Writing Instruction

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A Co-simulation Approach for System-Level Analysis of embedded Control systems

A Co-simulation Approach for System-Level Analysis of Embedd...

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international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Glass, Michael Teich, Juergen Zhang, Liyuan Univ Erlangen Nurnberg Erlangen Germany

ISBN: (纸本)9781467322973;9781467322966

Control applications have become an integral part of modern networked embedded systems. However, there often exists a gap between control engineering and system design. The control engineer has detailed knowledge about the algorithms but is abstracting from the system architecture and implementation. On the other hand, the system designer aims at achieving high-quality implementations based on quality constraints specified by the control engineer. This may result in either an over-designed system in case the specifications are pessimistic or an unsafe system behavior when specifications are too optimistic. Thus, future design automation approaches have to consider the quality of control applications both as design objectives and design constraints to achieve safe yet highly optimized system implementations. The work at hand introduces an automatic tool flow at the Electronic System Level (ESL) that enables the optimization of a system implementation with quality of control being introduced as a principal design objective, like the maximum braking distance, while respecting constraints like maximum slip to ensure maneuverability of a car. The gap between mathematically well-defined models for system synthesis and common analysis techniques for control quality is bridged by co-simulation: A SystemC-based virtual prototype of a distributed controller implementation is combined with high-level models of the plants specified in Matlab/Simulink. Through a model transformation, the traditional development process of control applications is combined with state-of-the-art ESL techniques, ensuring model consistency while enabling a high degree of automation.

关键词： Quality Control control systems control engineering design target system implementation English as Second Language maneuverability Pessimism design constraints Specifications Engineers Hand Standing Orders PROCESS DEVELOPMENT

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Design and implementation of hardware-in-the-loop-simulation for uav using pid control method

Design and implementation of hardware-in-the-loop-simulation...

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international conference on Instrumentation, Communications, Information Technology, and Biomedical Engineering (ICICI-BME)

作者： Sufendi Bambang Riyanto Trilaksono Syahron Hasbi Nasution Eko Budi Purwanto School of Electrical Engineering and Informatics Institut Teknologi Bandung Bandung Indonesia Department of Applied Aerospace Technology LAPAN Serpong Indonesia

One of fixed-wing aircraft type is the fixed-wing unmanned aircraft or fixed-wing Unmanned Aerial Vehicle (UAV). The UAV flies without a pilot in the aircraft. All aircraft movements are controlled by an embedded computer or a remote control. The whole complex UAV control system can be decomposed into several separated sections to simplify the control design process. The three-dimensional position control was simplified to one-dimensional height control and two-dimensional navigation control. The UAV motion composed of three force components and three moment components that make up the six Degrees of Freedom (6 DoF). In the modeling process, all motions of the aircraft are considered linear and have multiple inputs and outputs (MIMO). The controller used was a PID controller which is tuned using Ziegler-Nichols method. Implementation of the Hardware-in-the-Loop-simulation (HILS) can be done after the design of control systems for UAV is completed. The design of HILS structure was done with the help of MATLAB software. The controller that has been designed previously was implemented into the Ardupilot mega hardware. The design and implementation of PID control system with Ziegler-Nichols tuning method for the longitudinal and lateral directional dimensions, which include angular rate control, attitude control, altitude control and navigation control was able to stabilize an unstable system or to improve the system response.

关键词： Control systems Aircraft Attitude control Aircraft navigation Mathematical model

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Energy Efficient Stream-based Configurable Architecture for embedded Platforms

Energy Efficient Stream-based Configurable Architecture for ...

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international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Pratas, Frederico Tomas, Pedro Trancoso, Pedro Sousa, Leonel Univ Tecn Lisboa INESC ID IST Lisbon Portugal Univ Cyprus Dept Comp Sci Nicosia Cyprus

ISBN: (纸本)9781467322973;9781467322966

Reconfigurable hardware can be used as an energy and performance efficient co-processing solution to accelerate certain types of applications. To facilitate the design of hardware accelerators we have proposed a methodology that adopts the stream-based computing model and the usage of Graphics Processing Units as prototyping platforms. In this paper we go a step further and propose a new modular architecture for low-power reconfigurable systems to easily map the stream-based algorithms. In particular, the architecture consists of a semi-programable accelerator set that can be adapted to the application needs in terms of functional units and number of streaming engines. The proposed embedded architecture mates the exibility of recon. gurable hardware with the advantages of stream computing for the strict needs of embedded recon. gurable devices. We show a possible organization for this architecture. Moreover, we provide a general case study to analyze the scalability of the proposed architecture in an Altera FPGA. Our experimental results show that a significant speed-up can be achieved compared to general purpose processors using low-power FPGA devices. Our preliminary estimates show that it is also possible to achieve energy savings of up to 118x.

关键词： reconfigurable hardware Building construction ARCHITECTURE configurability embedded platform hardware accelerator embedding Platform energy saving Energy efficiency Scalability Field programmable gate arrays LOW POWER

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Proceedings - 2006 international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2006

Proceedings - 2006 International Conference on Embedded Comp...

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2006 international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2006

ISBN: (纸本)1424401550

The proceedings contain 26 papers. The topics discussed include: parallel memory implementation for arbitrary stride accesses;a table-based application-specific prefetch engine for object-oriented embedded systems;on the characterization of data cache vulnerability in high-performance embedded microprocessors;reduction of energy consumption in processes by early detection and bypassing of trivial operations;modified hotspot cache architecture: a low energy fast cache for embedded processors;area-aware optimizations for resource constrained branch predictors exploited in embedded processors;chip size estimation for SOC design space exploration;profiling driven scenario detection and prediction for multimedia applications;on the calibration of abstract performance models for system-level design space exploration;and multi-objective topology optimization for networked systems.

关键词： Energy utilization

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Model-Driven Robot-Software Design using integrated Models and Co-simulation

Model-Driven Robot-Software Design using integrated Models a...

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international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Broenink, Jan F. Ni, Yunyun Robotics and Mechatronics group CTIT institute faculty of Electrical Engineering Mathematics and Computer Science University of Twente The Netherlands

ISBN: (纸本)9781467322973

The work presented here is on a methodology for design of hard real-time embedded control software for robots, i.e. mechatronic products. The behavior of the total robot system (machine, control, software and I/O) is relevant, because the dynamics of the machine influences the robot software. Therefore, we use two appropriate Models of Computation, which represent continuous-time equations for the machine / robot part, and discrete event / discrete time equations for the control software part. To compute (simulate) such combined models, co-simulation of these models is used. The design work can be done as a stepwise refinement process, whereby each step is verified via co-simulation. This in general yields a shorter design time, and a better quality product. The tools pass model-specific information between each other via parametrized tokens in the generated, high-level code to get a better separation of design steps. This allows for better quality of the models and more reuse, thus enhancing the efficiency of model-driven design for the (industrial) end user. The method is illustrated with a case study using the tools, some of which are at the prototype level. Especially the structuring of the models and regularly doing simulations (of which some can be 'repeated' as real experiments), is beneficial, shortening the development time and producing better models. Future work is to test the method on more complex cases, and to extend the method by detailing out the electronics and mechanics sub design flows.

关键词： Robot hard real-time machine IO Robot software computer software Software design computer programs MACHINE TOOL CONTROL Robot System Microelectromechanical devices Equation discrete-time

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