Since in the large and complex robotic systems such as multiple robot systems, the real robot controllers are spatially distributed according to their physical structure, it is desirable to realize the hierarchical an...
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The proceedings contain 99 papers. The topics discussed include: architectural impact of secure socket layer on Internet servers: a retrospect;architectural simulations of a fast, source-synchronous ring-based network...
ISBN:
(纸本)9781467330503
The proceedings contain 99 papers. The topics discussed include: architectural impact of secure socket layer on Internet servers: a retrospect;architectural simulations of a fast, source-synchronous ring-based network-on-chip design;a case for small row buffers in non-volatile main memories;energy modeling of embedded multimedia streaming applications with GStreamer on heterogeneous MPSoC;efficient code compression for coarse grained reconfigurable architectures;distributed thermal-aware task scheduling for 3D network-on-chip;system level modeling of real-time embedded software;design and evaluation of a four-port data cache for high instruction level parallelism reconfigurable processors;track assignment considering crosstalk-induced performance degradation;efficient verification of out-of-order behaviors with relaxed scoreboards;and ring oscillator physical unclonable function with multi level supply voltages.
computer architects and researchers in the real-time domain start to investigate processors and architectures optimized for real-time systems. Optimized for real-time systems means time predictable, i.e., architecture...
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computer architects and researchers in the real-time domain start to investigate processors and architectures optimized for real-time systems. Optimized for real-time systems means time predictable, i.e., architectures where it is possible to statically derive a tight bound of the worst-case execution time. To compare different approaches we would like to quantify time predictability. That means we need to measure time predictability. In this paper we discuss the different approaches for these measurements and conclude that time predictability is practically not quantifiable. We can only compare the worst-case execution time bounds of different architectures.
Owing to its potential to satisfy all outstanding requests for the same data item with a single response, on-demand data broadcast becomes a widely accepted approach to dynamic and scalable wireless information dissem...
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The ability to continually increase the number of available transistors on a die has lead to the emergence of many- and multi-core computing architectures promising the potential for order of magnitude performance imp...
The ability to continually increase the number of available transistors on a die has lead to the emergence of many- and multi-core computing architectures promising the potential for order of magnitude performance improvements over single core solution through sheer concurrency. The abundance of transistors also enable the development of heterogeneous and (dynamically) reconfigurable architectures targeting selected markets such as real-time and/or embedded high-performance computing through a mix of traditional and customized cores.
The proceedings contain 20 papers. The topics discussed include: classification-based improvement of application robustness and quality of service in probabilistic computersystems;a case study on error resilient arch...
ISBN:
(纸本)9783642282928
The proceedings contain 20 papers. The topics discussed include: classification-based improvement of application robustness and quality of service in probabilistic computersystems;a case study on error resilient architectures for wireless communication;a very fast and quasi-accurate power-state-based system-level power modeling methodology;static task mapping for tiled chip multiprocessors with multiple voltage islands;an architecture for power management in automotive systems;invasive MPI on Intel's single-chip cloud computer;a low-overhead heuristic for mixed workload resource partitioning in cluster-based architectures;design principles for synthesizable processor cores;HPC performance domains on multi-core processors with virtualization;a generic and non-intrusive profiling methodology for SystemC multi-core platform simulation models;and dynamic task-scheduling and resource management for GPU accelerators in medical imaging.
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