This paper presents UWSim: a new software tool for visualization and simulation of underwater robotic missions. The software visualizes an underwater virtual scenario that can be configured using standard modeling sof...
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This paper focuses on the design of an on-chip communication system for control architectures used in RF (Radio Frequency) transceivers. Continuous developments and enhancements of RF transceivers, especially of smart...
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This paper focuses on the design of an on-chip communication system for control architectures used in RF (Radio Frequency) transceivers. Continuous developments and enhancements of RF transceivers, especially of smart transceivers supporting multi-mode standards, led to new and complex SoC (System-on-Chip) designs. These designs are defined by a distributed controlling concept using several processing modules which are connected over an advanced communication system. Based on the requirements and restrictions of this communication system an application-specific NoC (Network-on-Chip) is presented and analyzed in this work.
System-level design space exploration (DSE), which is performed early in the design process, is of eminent importance to the design of complex multi-processor embedded system architectures. During system-level DSE, sy...
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System-level design space exploration (DSE), which is performed early in the design process, is of eminent importance to the design of complex multi-processor embedded system architectures. During system-level DSE, system parameters like, e.g., the number and type of processors, the type and size of memories, or the mapping of application tasks to architectural resources, are considered. simulation-based DSE, in which different design instances are evaluated using system-level simulations, typically are computationally costly. Even using high-level simulations and efficient exploration algorithms, the simulation time to evaluate design points forms a real bottleneck in such DSE. Therefore, the vast design space that needs to be searched requires effective design space pruning techniques. This paper presents and studies different strategies for interleaving fast but less accurate analytical performance estimations with slower but more accurate simulations during DSE. By interleaving these analytical estimations with simulations, our hybrid approach significantly reduces the number of simulations that are needed during the process of DSE. Experimental results have demonstrated that such hybrid DSE is a promising technique that can yield solutions of similar quality as compared to simulation-based DSE but only at a fraction of the execution time.
The synchronous programming model is perfect for modeling, simulation, verification and implementation of reactive systems. While this paradigm can be directly implemented as hardware circuits, multithreaded software ...
The proceedings contain 26 papers. The topics discussed include: exposing security risks for commercial mobile devices;from qualitative to quantitative enforcement of security policy;design and implementation of a clo...
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(纸本)9783642337031
The proceedings contain 26 papers. The topics discussed include: exposing security risks for commercial mobile devices;from qualitative to quantitative enforcement of security policy;design and implementation of a cloud-based assured information sharing system;optimization of key distribution protocols based on extractors for noisy channels within active adversaries;a vulnerability in the UMTS and LTE authentication and key agreement protocols;alternative mechanisms for information security;enforcing information flow policies by a three-valued analysis;towards the orchestration of secured services under non-disclosure policies;an approach for network information flow analysis for systems of embedded components;individual countermeasure selection based on the return on response investment index;security and reliability requirements for advanced security event management;and using behavioral modeling and customized normalcy profiles as protection against targeted cyber-attacks.
Cyber-Physical systems (CPSs) integrate the virtual cyber world with the real physical world. In order to verify the new theories and methods, a novel CPSs simulation model for unmanned vehicle with Wireless Sensor Ne...
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In the recent years, improvements in robotic hardware have not been matched by advancements in robotic software and the gap between those two areas has been widening. To cope with the increasing complexity of novel ro...
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Summary form only given. All widely used software abstractions lack temporal semantics. The notion of correct execution of a program written in every widely-used programming language and in nearly every processor inst...
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Summary form only given. All widely used software abstractions lack temporal semantics. The notion of correct execution of a program written in every widely-used programming language and in nearly every processor instruction-set today does not depend on the timing of the execution. computer architects exploit the fact that timing is irrelevant to correctness with aggressive performance-enhancing techniques such as speculative execution, branch prediction, dynamic dispatch, cache memories, virtual memory, etc. While these techniques improve average case performance, they do so at the expense of controllability, repeatability, and predictability of timing. But temporal behavior matters in almost all systems, but most particularly in networked embeddedsystems. Even in systems with no particular real-time requirements, timing of programs is relevant to the value delivered by programs, and in the case of concurrent and distributed programs, also affects the functionality. In systems with real-time requirements, including most embeddedsystems, temporal behavior affects not just the value delivered by a system but also its correctness. This talk will argue that time can and must become part of the semantics of programs and computerarchitectures. To illustrate that this is both practical and useful, we will describe recent efforts at Berkeley in the design and analysis of timing-centric software systems. In particular, we will focus on two projects, PRET, which seeks to provide computing platforms with repeatable timing, and PTIDES, which provides a programming model for distributed real-time systems.
simulation of models that specify behaviour of software in robots, embeddedsystems, and safety critical systems is crucial to ensure correctness. This is particularly important in conjunction with model-driven develo...
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Due to energy efficiency requirements of modern embeddedsystems, chip vendors are inclined towards multicore architectures with different types of processing engines and non-uniform interconnect fabrics. At the same ...
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Due to energy efficiency requirements of modern embeddedsystems, chip vendors are inclined towards multicore architectures with different types of processing engines and non-uniform interconnect fabrics. At the same time multiple applications are intended to run concurrently on the devices with such heterogeneous architectures. This rapid growth in the complexity of the hardware and its use cases imposes new challenges on the software development tools. To overcome this complexity, model of computation based approaches are becoming increasingly promising. Synchronous Data Flow (SDF) is a popular specification formalism for streaming applications with inherently concurrent nature. However, the parallelism expressed in the original representation is often not sufficient to maximally exploit the potential of multicore platforms. In this paper we present a holistic methodology for improving the throughput of streaming applications while mapping them onto heterogeneous architectures. The approach uses transformations that adapt the parallelism in SDF according to available platform resources. We use a genetic algorithm to explore SDF instances with the objective of maximizing throughput on a target platform. Our model supports architecture heterogeneity and multi-application scenarios. The experiments indicate that our approach outperforms other techniques for exploiting parallelism on a single application in most of the test cases and enables concurrent applications optimization.
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