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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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HNOCS: Modular open-source simulator for Heterogeneous NoCs

HNOCS: Modular open-source simulator for Heterogeneous NoCs

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Yaniv Ben-Itzhak Eitan Zahavi Israel Cidon Avinoam Kolodny Electrical Engineering Department Technion - Israel Institute of Technology Haifa Israel

We present HNOCS (Heterogeneous Network-on-Chip Simulator), an open-source NoC simulator based on OMNeT++. To the best of our knowledge, HNOCS is the first simulator to support modeling of heterogeneous NoCs with variable link capacities and number of VCs per unidirectional port. The HNOCS simulation platform provides an open-source, modular, scalable, extendible and fully parameterizable framework for modeling NoCs. It includes three types of NoC routers: synchronous, synchronous virtual output queue (VoQ) and asynchronous. HNOCS provides a rich set of statistical measurements at the flit and packet levels: end-to-end latencies, throughput, VC acquisition latencies, transfer latencies, etc. We describe the architecture, structure, available models and the features that make HNOCS suitable for advanced NoC exploration. We also evaluate several case studies which cannot be evaluated with any other exiting NoC simulator.

关键词： Topology Throughput Routing computer architecture Traffic control Open source software

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Towards thermal profiling in CMOS/memristor hybrid RRAM architectures

Towards thermal profiling in CMOS/memristor hybrid RRAM arch...

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25th international conference on VLSI Design, VLSID 2012 and the 11th international conference on embedded systems

作者： Merkel, Cory E. Kudithipudi, Dhireesha Department of Computer Engineering Rochester Institute of Technology Rochester United States

ISBN: (纸本)9780769546384

In this paper, we propose a hybrid temperature sensing resistive random access memory (TSRRAM) architecture composed of traditional CMOS components and emerging memristive switching devices. The architecture enables each RRAM switching element to be used both as a memory bit and a temperature sensor. The TSRRAM is integrated into an Alpha 21364 processor as an L2 cache. Its accuracy and performance were simulated using a customized simulation framework. SPEC2000 benchmarks were used to generate thermal profiles in the Alpha processor core. Active and passive sensing mechanisms are also introduced as means for DTM algorithms to determine the thermal profile of the RRAM switching layer. The proposed architecture yielded a 2.14 K mean absolute temperature error during passive sensing, which is well within the useful range of dynamic thermal management (DTM) algorithms. Furthermore, the proposed design is shown to have only an 8 cycle performance overhead. © 2012 IEEE.

关键词： Memory architecture

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An FPGA-based prototyping method for verification, characterization and optimization of LDPC error correction systems

An FPGA-based prototyping method for verification, character...

引用

international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： P. Sakellariou I. Tsatsaragkos N. Kanistras A. Mahdi V. Paliouras Electrical and Computer Engineering Department University of Patras Patras Greece

This paper introduces a methodology for forward error correction (FEC) architectures prototyping, oriented to system verification and characterization. A complete design flow is described, which satisfies the requirement for error-free hardware design and acceleration of FEC simulations. FPGA devices give the designer the ability to observe rare events, due to tremendous speed-up of FEC operations. A Matlab-based system assists the investigation of the impact of very rare decoding failure events on the FEC system performance and the finding of solutions which aim to parameters optimization and BER performance improvement of LDPC codes in the error floor region. Furthermore, the development of an embedded system, which offers remote access to the system under test and verification process automation, is explored. The presented here prototyping approach exploits the high-processing speed of FPGA-based emulators and the observability and usability of software-based models.

关键词： Parity check codes Decoding Field programmable gate arrays MATLAB Hardware Forward error correction embedded systems

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The homogeneity of architecture in a heterogeneous world

The homogeneity of architecture in a heterogeneous world

引用

international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： John Goodacre ARM Cambridge United Kingdom

Summary form only given. It has long been accepted within embedded computing that using a heterogeneous core focused to a specific task can deliver improved performance and subsequent improved power efficiency. The challenge has always been how can the software programmer integrate this hardware diversity as workloads become generalized or often unknown at design time? Using library abstraction permits specific tasks to benefit from heterogeneity, but how can general purpose code benefit? This talk will describe the hardware and software techniques currently being developed in next generation ARM based SoC to address the challenge of maintaining the homogeneity of the software architecture while extending to the benefits of heterogeneity in hardware.

关键词： Hardware computer architecture Abstracts embedded computing Libraries Next generation networking

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Adaptive processor architecture - invited paper

Adaptive processor architecture - invited paper

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Michael Huebner Diana Goehringer Carsten Tradowsky Joerg Henkel Jürgen Becker Embedded Systems in Information Technology (ESIT) Ruhr-University of Bochum - RUB Germany Institute for Data Processing and Electronics (IPE) Karlsruhe Institute of Technology (KIT) Institute for Information Processing Technology (ITIV) Karlsruhe Institute of Technology (KIT) Karlsruhe Institute of Technology (KIT)

This paper introduces a novel methodology to adapt the microarchitecture of a processor at run-time. The goal is to tailor the internal architecture to the requirements of an application and the data to be processed. The latter parameter is normally not known at design time. This leads to the development of more general purpose processors which are capable to handle the data to be processed in any case. With the novel approach which keeps the microarchitecture of a processor flexible, the processor can start as a general purpose device and end up with a specific parameterization, comparable with application specific processor architectures. Furthermore, the increased degree of freedom which is enabled through the approach for a novel quality of processors is described.

关键词： Abstracts Process control Current measurement Monitoring Lead Clocks Argon

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Just-in-Time Verification in ADL-based processor design

Just-in-Time Verification in ADL-based processor design

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： D. Auras A. Minwegen U. Deidersen S. Schurmans G. Ascheid R. Leupers Rheinisch-Westfalische Technische Hochschule Aachen Aachen Nordrhein-Westfalen DE Inst. for Commun. Technol. & Embedded Syst. RWTH Aachen Univ. Aachen Germany

A novel verification methodology, combining the two new techniques of Live Verification and Processor State Transfer, is introduced to Architecture Description Language (ADL) based processor design. The proposed Just-in-Time Verification significantly accelerates the simulation-based equivalence check of the register-transfer and instruction-set level models, generated from the ADL-based specification. This is accomplished by omitting redundant simulation steps occurring in the conventional architecture debug cycle. The potential speedup is demonstrated with a case study, achieving an acceleration of the debug cycle by 660x.

关键词： Registers computer architecture Pipelines Hardware design languages Debugging Mathematical model History

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Trustworthy web service selection using probabilistic models

Trustworthy web service selection using probabilistic models

引用

2012 IEEE 19th international conference on Web Services, ICWS 2012

作者： Mehdi, Mohamad Bouguila, Nizar Bentahar, Jamal Engineering and Computer Science Concordia University Montreal QC Canada Concordia Institute for Information Systems Engineering Montreal QC Canada

ISBN: (纸本)9780769547527

Software architectures of large-scale systems are perceptibly shifting towards employing open and distributed computing. Service Oriented Computing (SOC) is a typical example of such environment in which the quality of interactions amongst software agents is a critical concern. Agent-based web services in open and distributed architectures need to interact with each other to achieve their goals and fulfill complex user requests. Two common tasks are influenced by the quality of interactions among web services: the selection and composition. Thus, to ensure the maximum gain in both tasks, it is essential for each agent-based web service to maintain a model of its environment. This model then provides a means for a web service to predict the quality of future interactions with its peers. In this paper, we formulate this model as a machine learning problem which we analyze by modeling the trustworthiness of web services using probabilistic models. We propose two approaches for trust learning of single and composed services;Bayesian Networks and Mixture of Multinomial Dirichlet Distributions (MMDD). The effectiveness of our approaches is empirically assessed using a simulation study. Our results show that representing the quality of a web service by Multinomial Dirichlet Distribution (MDD) provides high flexibility and accuracy in modeling trust. They also show that using our approaches to estimate trust enhances web services selection and composition. © 2012 IEEE.

关键词： Bayesian networks

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An FPGA-accelerated testbed for hardware component development in MIMO wireless communication systems

An FPGA-accelerated testbed for hardware component developme...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Filippo Borlenghi Dominik Auras Ernst Martin Witte Torsten Kempf Gerd Ascheid Rainer Leupers Heinrich Meyr Institute for Communication Technologies and Embedded Systems RWTH Aachen University Aachen Germany

FPGA-based prototyping is nowadays common practice in the functional verification of hardware components since it allows to cover a large number of test cases in a shorter time compared to HDL simulation. In addition, an FPGA-based emulator significantly accelerates the simulation with respect to bit-true software models. This speed-up is crucial when the statistical properties of a system have to be analyzed by Monte Carlo techniques. In this paper we consider a multiple-input multiple-output (MIMO) wireless communication system and show how integrating an FPGA accelerator in the software simulation framework is key to enable the development of complex hardware components in the receiver, from algorithm all the way to chip testing. In particular, we focus on a MIMO detector implementation based on the depth-first sphere decoding algorithm. The speed-up of up to 3 orders of magnitude achieved by hardware-accelerated simulation compared to a pure software testbed enables an extensive fixed-point exploration. Furthermore, it allows a unique characterization of the system communication performance and the MIMO detector run-time characteristics, which vary for different configuration parameters and operating scenarios and hence require a thorough investigation.

关键词： Hardware Field programmable gate arrays MIMO Servers Computational modeling Software Data models

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Nets-within-nets to model innovative space system architectures

Nets-within-nets to model innovative space system architectu...

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33rd international conference on Application and Theory of Petri Nets and Concurrency, PETRI NETS 2012

作者： Cristini, Frédéric Tessier, Catherine ONERA French Aerospace Lab. Toulouse France

ISBN: (纸本)9783642311307

This paper focuses on a nets-within-nets approach to model, simulate and evaluate innovative space system architectures. Indeed, as military Earth observation space systems are more and more subjected to a wide spectrum of emerging space threats and attacks, it is necessary to devise new architectures and to assess their performance and their threat-tolerance. We will consider networked constellations of autonomous microsatellites - or Autonomous Networked Constellations (ANCs) - in which several heterogeneous interacting entities (satellites and ground stations), ruled by the space dynamics laws, rely on resources (functions or sub-systems) to achieve the overall Earth observation mission. Petri nets are well adapted for modeling ANCs as they feature event-triggered state changes and concurrent communication accesses. The ANC model is based on Renew 2.2 which we use to deal with top-down, bottom-up and horizontal synchronizations so as to represent state propagations from an entity to its nested resources and vice-versa, and from an entity to another one. A model and simulation of a simple ANC subjected to threats are given and discussed. © 2012 Springer-Verlag.

关键词： Petri nets

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System modeling and multicore simulation using transactions

System modeling and multicore simulation using transactions

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Amine Anane El Mostapha Aboulhamid Yvon Savaria Université de Montréal Montréal Canada École Polytechnique de Montréal Montréal Canada

With the increasing complexity of digital systems that are becoming more and more parallel, a better abstraction to describe such systems has become a necessity. This paper shows how, by using the powerful mechanism of transactions as a concurrency model, and by taking advantage of .NET introspection and attribute programming capabilities, we were able to develop a system-level modeling and parallel simulation environment. We kept the same concepts to describe the architecture of high-level models, such as modules and communication channels. However, unlike SystemC, the behaviour is no longer described as processes and events but as transactions. We implemented scheduling algorithms in order to enable simulating a transactional models in parallel by taking advantage of a multicore machine. These algorithms take into account the dependency between transactions and the number of cores of the simulation machine. We studied two synchronisation strategies: one using locking and the other using partitioning. An experiment made on a WiFi 802.11a transmitter achieved a speedup of about 1.9 using two threads. With 8 threads, although the workload of individual transactions was not significant, we could reach a 5.1 speedup. When the workload is significant the speedup can reach 6.3.

关键词： Synchronization Semantics Multicore processing Scheduling algorithms Complexity theory System-on-a-chip Programming

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