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Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems

Combining on-hardware prototyping and high-level simulation ...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Paolo Meloni Sebastiano Pomata Luigi Raffo Roberta Piscitelli Andy D. Pimentel Department of Electrical and Electronic Engineering University of Cagliari Computer Systems Architecture Group University of Amsterdam

Modern heterogeneous multi-processor embedded systems very often expose to the designer a large number of degrees of freedom, related to the application partitioning/mapping and to the component- and system-level architecture composition. The number is even larger when the designer targets systems based on configurable Application Specific Instruction-set Processors, due to the fine customizability of their internal architecture. This poses the need for effective and user-friendly design tools, capable to deal with the extremely wide system-level design space exposed by multi-processor architecture and, at the same time, with an extended variety of processing element architectural configurations, to be evaluated in detail and in reasonable times. As a possible solution, within the MADNESS project [1], an integrated toolset has been proposed, combining the benefits of novel fast FPGA-based prototyping techniques with those provided by high-level simulation. In the toolset, the resulting evaluation platform serves as an underlying layer for a Design Space search algorithm. The paper presents the individual tools included in the toolset and their interaction strategy. The approach is then evaluated with a design space exploration case study, taking as a target application a video compression kernel. The integrated toolset has been used to produce a Pareto front of evaluated system-level configurations.

关键词： computer architecture Program processors Computational modeling Search engines Space exploration Field programmable gate arrays Registers

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Efficient computing in cyber-physical systems

Efficient computing in cyber-physical systems

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Peter Marwedel Michael Engel TU Dortmund Dortmund Germany

Computing in cyber-physical systems has to be efficient in terms of a number of objectives. In particular, computing has to be execution-time and energy efficient. In this paper, we will consider optimization techniques aiming at efficiency in terms of these two objectives. In the first part, we will consider techniques for the integration of compilers and worst-case execution time (WCET) estimation. We will demonstrate, how such integration opens the door to WCET-reduction algorithms. For example, an algorithm for WCET-aware compilation reduces the WCET for an automotive application by more than 50% by exploiting scratch pad memories (SPMs). In the second part, we will demonstrate techniques for improving the energy efficiency of cyber-physical systems, in particular the use of SPMs. In the third part, we demonstrate how the optimization for multiple objectives taken into account. This paper provides an overview of work performed at the Chair for embedded systems of TU Dortmund and the Informatik Centrum Dortmund, Germany 1 .

关键词： Optimization Energy consumption Resource management embedded systems Memory management Timing

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A tightly-coupled multi-core cluster with shared-memory HW accelerators

A tightly-coupled multi-core cluster with shared-memory HW a...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Masoud Dehyadegari Andrea Marongiu Mohammad Reza Kakoee Luca Benini Siamak Mohammadi Naser Yazdani University of Tehran Tehran Tehran IR DEIS Viale Risorgimento Bologna Italy School of ECE University of Tehran Tehran Iran

Tightly coupling hardware accelerators with processors is a well-known approach for boosting the efficiency of MPSoC platforms. The key design challenges in this area are: (i) streamlining accelerator definition and instantiation and (ii) developing architectural templates and run-time techniques for minimizing the cost of communication and synchronization between processors and accelerators. In this paper we present an architecture featuring tightly-coupled processors and hardware processing units (HWPU), with zero-copy communication. We also provide a simple programming API, which simplifies the process of offloading jobs to HWPUs.

关键词： Program processors Synchronization Acceleration Registers computer architecture Hardware Hardware design languages

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PERFORMANCE INVESTIGATION OF PERMANENT MAGNET SYNCHRONOUS MOTOR DRIVE USING VECTOR CONTROLLED TECHNIQUE

PERFORMANCE INVESTIGATION OF PERMANENT MAGNET SYNCHRONOUS MO...

引用

2nd international conference on Power, Control and embedded systems (ICPCES)

作者： Singh, Jaswant Singh, Bindeshwar Singh, S. P. Chaurasia, Ravi Sachan, Sulabh Kamla Nehru Inst Technol Dept Elect Engn Sultanpur 228118 India IIT Roorkee Roorkee Uttar Pradesh India NTT Meerut Meerut Uttar Pradesh India

ISBN: (纸本)9781467310499;9781467310475

The rotor position is necessary to achieve the vector control drive system of Permanent Magnet Synchronous Motor (PMSM). In this thesis, the resolver sensor detecting the rotor position of PMSM is focused. PMSM has been widely used in high performance drive applications for its advantages such as compactness, high efficiency, reliability, and suitability to environment. Due to its high power density and smaller size, PMSM has evolved as the preferred solution for speed and position control drives on machine tools and robots. A PMSM is a motor that uses permanent magnets to produce the air gap magnetic field rather than using electromagnets. These motors have significant advantages, attracting the interest of researchers and industry for use in many applications. PMSMs are widely used in low and mid power applications such as computer peripheral equipments, robotics, adjustable speed drives and electric vehicles. In order to overcome the inherent coupling effect and the sluggish response of scalar control the vector control is employed. By using the vector control, the performance of the AC machine can be made similar to that of a DC machine. In this thesis to achieve high performance the vector control of the Permanent magnet synchronous motors drive are used for different reference constant speed and mechanical load torque is employed. The simulation of PMSM drives with vector control technique is developed using environment. The effectiveness of the proposed control method is verified by simulation based on MATLAB/SIMULINK environment.

关键词： vector controlled technique (VECT) permanent magnet synchronous motor (PMSM) sine pulse with modulation (SPWM) modeling equations current estimation speed estimation

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Sensor systems and Software - Third international ICST conference, S-Cube 2012, Revised Selected Papers

Sensor Systems and Software - Third International ICST Confe...

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3rd international ICST conference on Sensor systems and Software, S-Cube 2012

ISBN: (纸本)9783642327773

The proceedings contain 11 papers. The topics discussed include: vehicular sensing: emergence of a massive urban scanner;framework for a self-managed wireless sensor cloud for critical event management;middleware mechanisms for agent mobility in wireless sensor and actuator networks;vital responder ? wearable sensing challenges in uncontrolled critical environments;time series prediction for energy-efficient wireless sensors: applications to environmental monitoring and video games;connected cars: how distributed data mining is changing the next generation of vehicle telematics products;modeling and simulation of underwater low-power wake-up systems;collaborative sensing platform for eco routing and environmental monitoring;integrate WSN to the web of things by using XMPP;challenges and opportunities for embedded computing in retail environments;and the need for standardized tests to evaluate the reliability of data transport in wireless medical systems.

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Hardware-in-the-loop simulations of circuit architectures for the computation of exact and approximate explicit MPC control functions

Hardware-in-the-loop simulations of circuit architectures fo...

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IEEE international conference on Electronics, Circuits and systems (ICECS)

作者： Alberto Oliveri Marco Storace Dipartimento di Ingegneria Navale Elettrica Elettronica e delle Telecomunicazioni (DITEN) University of Genoa Genoa Italy

Several circuit architectures have been proposed for the fast implementation of embedded control systems, but only simulated results of the stand-alone circuits are usually reported. In this work we perform a hardware-in-the-loop simulation of a closed-loop system in which the controller is physically implemented in an FPGA. We improve two different circuit architectures available in the literature, to make them suitable for the computation of exact and approximate Model Predictive Control and we test them with the FPGA-in-the-loop simulations. Control and circuit performances are discussed.

关键词： computer architecture Integrated circuit modeling Computational modeling Approximation methods Field programmable gate arrays Mathematical model Clocks

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BADCO: Behavioral Application-Dependent Superscalar Core model

BADCO: Behavioral Application-Dependent Superscalar Core mod...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Ricardo A. Velásquez Pierre Michaud André Seznec IRISA/INRIA Rennes France

Microarchitecture research and development rely heavily on simulators. The ideal simulator should be simple and easy to develop, it should be precise, accurate and very fast. But the ideal simulator does not exist, and microarchitects use different sorts of simulators at different stages of the development of a processor, depending on which is most important, accuracy or simulation speed. Approximate microarchitecture models, which trade accuracy for simulation speed, are very useful for research and design space exploration, provided the loss of accuracy remains acceptable. Behavioral superscalar core modeling is a possible way to trade accuracy for simulation speed in situations where the focus of the study is not the core itself. In this approach, a superscalar core is viewed as a black box emitting requests to the uncore at certain times. A behavioral core model can be connected to a cycle-accurate uncore model. Behavioral core models are built from cycle-accurate simulations. Once the time to build the model is amortized, important simulation speedups can be obtained. We describe and study a new method for defining behavioral models for modern superscalar cores. The proposed Behavioral Application-Dependent Superscalar Core model, BADCO, predicts the execution time of a thread running on a superscalar core with an error less than 10% in most cases. We show that BADCO is qualitatively accurate, being able to predict how performance changes when we change the uncore. The simulation speedups we obtained are typically between one and two orders of magnitude.

关键词： Multicore processing Accuracy Microarchitecture Adaptation models Buildings Load modeling Mathematical model

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Using OpenMP superscalar for parallelization of embedded and consumer applications

Using OpenMP superscalar for parallelization of embedded and...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Michael Andersch Chi Ching Chi Ben Juurlink Embedded Systems Architecture Department TU Berlin Berlin Germany

In the past years, research and industry have introduced several parallel programming models to simplify the development of parallel applications. A popular class among these models are task-based programming models which proclaim ease-of-use, portability, and high performance. A novel model in this class, OpenMP Superscalar, combines advanced features such as automated runtime dependency resolution, while maintaining simple pragma-based programming for C/C++. OpenMP Superscalar has proven to be effective in leveraging parallelism in HPC workloads. embedded and consumer applications, however, are currently still mainly parallelized using traditional thread-based programming models. In this work, we investigate how effective OpenMP Superscalar is for embedded and consumer applications in terms of usability and performance. To determine the usability of OmpSs, we show in detail how to implement complex parallelization strategies such as ones used in parallel H.264 decoding. To evaluate the performance we created a collection of ten embedded and consumer benchmarks parallelized in both OmpSs and Pthreads.

关键词： Parallel processing Benchmark testing Decoding Kernel Entropy Parallel programming

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2012 IEEE 31st international Performance Computing and Communications conference, IPCCC 2012

2012 IEEE 31st International Performance Computing and Commu...

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2012 IEEE 31st international Performance Computing and Communications conference, IPCCC 2012

ISBN: (纸本)9781467348812

The proceedings contain 61 papers. The topics discussed include: improving performance and anonymity in the Tor network;temporal characterization of SPEC CPU2006 workloads: analysis and synthesis;performance-sensitivity and performance-similarity based workload reduction;thermal modeling and analysis of storage systems;improving the schedulability and energy efficiency for weakly hard real-time embedded systems;an adaptive power management framework for autonomic resource configuration in cloud computing infrastructures;CloudCast: cloud computing for short-term mobile weather forecasts;AFD: adaptive failure detection system for cloud computing infrastructures;an arbitrary mobility model of mini-sinks using controlled data collection for reducing congestion appearance in wireless sensor networks;fast sink placement for gossip-based wireless sensor networks;and improved deduplication through parallel binning.

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Challenges in automotive cyber-physical systems design

Challenges in automotive cyber-physical systems design

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Dip Goswami Reinhard Schneider Alejandro Masrur Martin Lukasiewycz Samarjit Chakraborty Harald Voit Anuradha Annaswamy Institute for Real-Time Computer Systems TU Munich Germany TUM-CREATE Center for Electromobility Singapore Institute for Automatic Control TU Munich Germany Massachusetts Institute of Technology USA

systems with tightly interacting computational (cyber) units and physical systems are generally referred to as cyber-physical systems. They involve an interplay between embedded systems, control theory, real-time systems and software engineering. A very good example of cyber-physical systems design arises in the context of automotive architectures and software. Modern high-end cars have 50-100 processors or electronic control units (ECUs) that communicate over a network of buses such as CAN and FlexRay. In such complex settings, traditional control-theoretic approaches - where control engineers are only concerned with high-level plant and controller models - start breaking down. This is because implementation-level realities such as message delay, jitter, and task execution times are not adequately considered when designing the controller. Hence, it is becoming necessary to adopt a more holistic, cyber-physical systems design approach where the semantic gap between high-level control models and their actual implementations on multiprocessor automotive platforms is quantified and consciously closed. In this paper we give several examples on how this may be done and the current research challenges in this area that are being faced by the academia and the industry.

关键词： Automotive engineering Schedules Algorithm design and analysis Space exploration Delay Mathematical model Control systems

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