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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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Seeing errors: Model driven simulation trace visualization 12

Seeing errors: Model driven simulation trace visualization

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15th international conference on Model Driven Engineering Languages and systems, MODELS 2012

作者： Aboussoror, El Arbi Ober, Ileana Ober, Iulian IRIT Université de Toulouse 118 Route de Narbonne Toulouse F -31062 France

ISBN: (纸本)9783642336652

Powerful theoretical frameworks exist for model validation and verification, yet their use in concrete projects is limited. This is partially due to the fact that the results of model verification and simulation are difficult to exploit. This paper reports on a model driven approach that supports the user during the error diagnosis phases, by allowing customizable simulation trace visualization. Our thesis is that we can use models to significantly improve the information visualization during the diagnosis phase. This thesis is supported by Metaviz - a model-driven framework for simulation trace visualization. Metaviz uses the IFx-OMEGA model validation platform and a state-of-the-art information visualization reference model together with a well-defined development process guiding the user into building custom visualizations,essentially by defining model transformations. This approach has the potential to improve the practical usage of modeling techniques and to increase the usability and attractiveness of model validation tools. © 2012 Springer-Verlag.

关键词： embedded systems

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Fast-accurate non-polynomial metamodeling for nano-CMOS PLL design optimization

Fast-accurate non-polynomial metamodeling for nano-CMOS PLL ...

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25th international conference on VLSI Design, VLSID 2012 and the 11th international conference on embedded systems

作者： Garitselov, Oleg Mohanty, Saraju P. Kougianos, Elias Nano-Systems Design Laboratory University of North Texas Denton TX United States Department of Computer Science and Engineering University of North Texas Denton TX United States Department of Engineering Technology University of North Texas Denton TX United States

ISBN: (纸本)9780769546384

At the nanoscale domain, the simulation, design, and optimization time of the circuits have increased significantly due to high-integration density, increasing technology constraints, and complex device models. This necessitates fast design space exploration techniques to meet the shorter time to market driven by consumer electronics. This paper presents non-polynomial metamodels (surrogate models) using neural networks to reduce the design optimization time of complex nano-CMOS circuit with no sacrifice on accuracy. The physical design aware neural networks are trained and used as metamodels to predict frequency, locking time, and power of a PLL circuit. Different architectures for neural networks are compared with traditional polynomial functions that have been generated for the same circuit characteristics. Thorough experimental results show that only 100 sample points are sufficient for neural networks to predict the output of circuits with 21 design parameters within 3% accuracy, which improves the accuracy by 56% over polynomial metamodels. The generated metamodels are used to perform optimization of the PLL using a bee colony algorithm. It is observed that the non-polynomial (using neural networks) metamodels achieve more accurate results than polynomial metamodels in shorter optimization time. © 2012 IEEE.

关键词： Polynomials

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Adaptive dynamic memory allocators by estimating application workloads

Adaptive dynamic memory allocators by estimating application...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Ioannis Koutras Alexandros Bartzas Dimitrios Soudris School of Electrical and Computer Engineering National Technical University of Athens Athens Greece

Modern applications are becoming more complex and dynamic and try to efficiently utilize the amount of available resources on the computing platforms. Efficient memory utilization is a key challenge for application developers, especially since memory is a scarce resource and often becomes systems bottleneck. Thus, the developers can resort to dynamic memory management, i.e., dynamic memory allocation and de-allocation, to efficiently utilize the memory resources. A high-performance adaptive memory allocator is presented in this paper. A memory allocator helps applications to manage more efficiently the memory space that operating systems bestow to them. In our approach, we tune the memory allocator at runtime by predicting the amount of memory to be requested. Experimental results obtained using applications from the PARSEC benchmark suite and dmmlib, a memory allocator framework written in C. Results show that adaptive memory allocators can improve the fragmentation problems leading to a more efficient memory usage.

关键词： Memory management Resource management Dynamic scheduling Runtime Hardware Operating systems Program processors

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Multi-modeling and co-simulation-based mobile ubiquitous protocols and services development and assessment

Multi-modeling and co-simulation-based mobile ubiquitous pro...

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7th international ICST conference on Mobile and Ubiquitous systems, MobiQuitous 2010

作者： Leclerc, Tom Siebert, Julien Chevrier, Vincent Ciarletta, Laurent Festor, Olivier MADYNES and MAIA - INRIA Lorraine Nancy Université France

ISBN: (纸本)9783642291531

Mobile and Ubiquitous Computing is about interconnected computing resources embedded in our daily lives and providing contextual services to users. The real influence between user behavior and ubiquitous communication protocols performance and operation needs to be taken into account at the protocol design stage. Therefore, we provide a generic multi-modeling approach that allows us to couple a user behavior model with a network model. To allow both assessment and benchmarking of ubiquitous solutions, we define formal reference scenarios based on the selection of a set of environmental conditions (contexts). We illustrate the use of the framework through its application to the study of mutual influences of mobility models and ad hoc network protocols. © 2012 Springer-Verlag Berlin Heidelberg.

关键词： Network protocols

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Out-Of-order execution of synchronous data-flow networks

Out-Of-order execution of synchronous data-flow networks

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Daniel Baudisch Jens Brandt Klaus Schneider Department of Computer Science University of Kaiserslautern

Data flow process networks (DPNs) have been introduced as a convenient model of computation for distributed and asynchronous systems since each process node can work independently of the other nodes, i. e. without the need of a global coordination. Synchronous and cyclo-static data flow process networks even allow to derive at compile-time efficient static schedules that allow one to run these systems with an efficient use of available resources, e. g. in embedded systems. Single process nodes of DPNs are stream-based computing devices that transform input streams to uniquely defined corresponding output streams such that single values of the output streams are computed as soon as sufficient input values are available. In this sense, they are related to the execution of an instruction stream by a conventional microprocessor. In this paper, we show how out-of-order execution that has been introduced for the efficient use of multiple functional units in microprocessors can also be used for the implementation of DPNs on multiprocessors. This way, the implementation of DPNs on multiprocessors allows one to optimize the throughput of single process nodes, and as shown by our experiments, also of the entire DPN.

关键词： Out of order computer architecture Radiation detectors Schedules Context Registers

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international conference on System simulation and Scientific Computing 2012, ICSC 2012

International Conference on System Simulation and Scientific...

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international conference on System simulation and Scientific Computing 2012, ICSC 2012

ISBN: (纸本)9783642343803

The proceedings contain 52 papers. The special focus in this conference is on modeling theory and technology, M and S technology on synthesized environments and virtual reality environments, pervasive computing and simulation technology, embedded computing and simulation technology, and verification/ validation/accreditation technology. The topics include: theoretical study and 3D CFD simulation of temperature distribution through HTST for orange juice;fuzzy control strategy for train lateral semi-active suspension based on particle swarm optimization;design and implementation of a mathematical simulation platform;an investigation on the flow field of a vortex cup;numerical simulation and linear active disturbance rejection control of unstable heat conduction systems;output power analysis and simulations of resonant tunneling diode based oscillators;an approach for vehicle state estimation using extended kalman filter;equilibrium simulation of power market with wind power based on CVaR approach;high-accuracy magnetic rotary encoder;an adaptive slope compensation circuit and its application;research on weight functions of electromagnetic flowmeter in open channels;engineering modeling and simulation for new estimation of aircraft's dynamic angles;trajectory tracking controller of small-scale helicopter based on backstepping;study on general effectiveness evaluation platform for combat aircraft;fuzzy sliding mode variable structure controller for hypersonic cruise vehicle;grid current control strategy based on internal model control and repetitive control;study on Holon environment model in battle deduction simulation system;improved virtual leader based formation control for nonholonomic multi-UUV;an image processing method for grains counting;design and realization of vision-based landing simulation verification system for UH based on Vega prime / MFC;design and experiment of adaptive active vibration control system for aircraft framework;model reconstruction using

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Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores 12

Collecting signatures to model latency tolerance in high-lev...

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4th Workshop on Rapid simulation and Performance Evaluation: Methods and Tools, RAPIDO'12, Collocated with the 7th Intl. conference on High-Performance and embedded architectures and Compilers, HiPEAC 2012

作者： Uddin, M. Irfan Jesshope, Chris R. Van Tol, Michiel W. Poss, Raphael Computer Systems Architecture Group Institute for Informatics University of Amsterdam Sciencepark 904 1098 XH Amsterdam Netherlands

ISBN: (纸本)9781450311144

The current many-core architectures are generally evaluated using cycle-accurate simulations. However these detailed simulations of the architecture make the evaluation of large programs very slow. Since the focus in many-core architecture is shifting from the performance of individual cores to the overall behavior of the chip, high-level simulations are becoming necessary, which evaluate the same architecture at less detailed level and allow the designer to make quick and reasonably accurate design decisions. We have developed a high-level simulator for the design space exploration of the Microgrid, which is a many-core architecture comprised of many fine-grained multi-threaded cores. This simulator allows us to investigate mapping and scheduling strategies of families (i.e. groups of threads) in developing an operating environment for the Microgrid. The previous method to count and evaluate the workload in basic blocks was not accurate enough. The key problem was that with many concurrent threads the latency of certain instructions is hidden because of the multi-threaded nature of the core. This paper presents a technique to determine the execution time of different types of instructions with thread concurrency. We believe to achieve high accuracy in evaluating programs in the high-level simulator. Copyright 2012 ACM.

关键词： Simulators

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Efficient system design using the Statistical Analysis of Architectural Bottlenecks methodology

Efficient system design using the Statistical Analysis of Ar...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Manish Arora Feng Wang Bob Rychlik M. Tullsen Department of Computer Science and Engineering University of California San Diego La Jolla CA U.S.A. Qualcomm Incorporated San Diego CA U.S.A.

CPU processor design involves a large set of increasingly complex design decisions Doing full, accurate simulation of all possible designs is typically not feasible. Prior techniques for sensitivity analysis seek to identify the most critical design parameters, but also struggle to handle the increasing design space well. They can be overly sensitive to the starting fixed point of the design, can still require a large number of simulations, and do not necessarily account for the cost of each design parameter. The Statistical Analysis of Architectural Bottlenecks (SAAB) methodology simultaneously analyzes multiple parameters and requires a small number of experiments. SAAB leverages the Plackett and Burman analysis method, but builds upon the technique in two specific ways. It allows a parameter to take multiple values and replaces the unit-less impact factor with a cost-proportional impact value. This paper applies the SAAB methodology to the design of a mobile processor sub-system. It considers area and power cost models for the design.

关键词： Benchmark testing Mobile communication Browsers Upper bound Sensitivity analysis Design methodology Multicore processing

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Virtual prototyping for efficient multi-core ECU development of driver assistance systems

Virtual prototyping for efficient multi-core ECU development...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Rainer Kiesel Martin Streubühr Christian Haubelt Anestis Terzis Jürgen Teich Group Research (GR/PAP) Daimler AG Ulm Germany University of Erlangen-Nuremberg Erlangen Germany University of Rostock Rostock Germany

In recent years, road vehicles have experienced an enormous increase in driver assistance systems such as traffic sign recognition, lane departure warning, and pedestrian detection. Cost-efficient development of electronic control units (ECUs) for these systems is a complex challenge. The demand for shortened time to market makes the development even more challenging and thus demands efficient design flows. This paper proposes a model-based design flow that permits simulation-based performance evaluation of multi-core ECUs for driver assistance systems in a pre-development stage. The approach is based on a system-level virtual prototype of a multi-core ECU and allows the evaluation of timing effects by mapping application tasks to different platforms. The results show that performance estimation of different parallel implementation candidates is possible with high accuracy even in a pre-development stage. By adapting the best-fitting parallelization strategy to the final ECU, a reduction in the time to market period is possible. Currently, the design flow is being evaluated by Daimler AG and is being applied to a pedestrian detection system. Results from this application illustrate the benefits of the proposed approach.

关键词： Prototypes Calibration Vehicles Production computer architecture Estimation Hardware

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Efficient hardware implementation of data-flow parallel embedded systems

Efficient hardware implementation of data-flow parallel embe...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Patrice Quinton Anne-Marie Chana Steven Derrien ENS Cachan Bretagne Université européenne de Bretagne Bruz France École Nationale Polytechnique de Yaoundé Université de Yaoundé Cameroon Université de Rennes 1 Université européenne de Bretagne Rennes France

Many modern computing systems deal with streams of data, which have to be processed in parallel in order to be handled in real-time. This is in particular the case for some kind of cyber physical systems, which process data provided by physical devices. We consider here an approach to generate efficient hardware for-a particular class of-such systems, which relies upon the polyhedral model. Flexible parallel components, described by the Alpha functional language, are modelled and assembled using a scheduling method which combines the synchronous data-flow principle of balance equations, and the polyhedral scheduling technique. The modelling of flexible components relies on a simple, affine-periodic, delayable and stretchable time model, which allows a full system to be assembled and synthesized by combining the component hardware descriptions with automatically generated wrappers. We illustrate this method on a simplified WCDMA system and we discuss the relationship of this approach with stream languages, latency-insensitive design, and multidimensional data-flow systems.

关键词： Synchronization Hardware Clocks Registers Schedules Mathematical model Multiaccess communication

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