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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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Efficient Hardware Implementation of Data-Flow Parallel embedded systems

Efficient Hardware Implementation of Data-Flow Parallel Embe...

引用

international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Quinton, Patrice Chana, Anne-Marie Derrien, Steven Univ Europeenne Bretagne ENS Cachan Bretagne F-35170 Bruz France

ISBN: (纸本)9781467322973;9781467322966

Many modern computing systems deal with streams of data, which have to be processed in parallel in order to be handled in real-time. This is in particular the case for some kind of cyber physical systems, which process data provided by physical devices. We consider here an approach to generate efficient hardware for-a particular class of-such systems, which relies upon the polyhedral model. Flexible parallel components, described by the ALPHA functional language, are modelled and assembled using a scheduling method which combines the synchronous data-flow principle of balance equations, and the polyhedral scheduling technique. The modelling of flexible components relies on a simple, affine-periodic, delayable and stretchable time model, which allows a full system to be assembled and synthesized by combining the component hardware descriptions with automatically generated wrappers. We illustrate this method on a simplified WCDMA system and we discuss the relationship of this approach with stream languages, latency-insensitive design, and multidimensional data-flow systems.

关键词： computer hardware Flexible components Parallel Lines Hydrologic models streams embedded systems Equation Cyber-physical systems assemblies rivers Functional programming WRAPPERS

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From Scilab to Multicore embedded systems: Algorithms and Methodologies

From Scilab to Multicore Embedded Systems: Algorithms and Me...

引用

international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Goulas, George Alefragis, Panayiotis Voros, Nikolaos S. Valouxis, Christos Derrien, Steven Menard, Daniel Sentieys, Olivier Gogos, Christos Huebner, Michael Kavvadias, Nikolaos Dimitroulakos, Grigoris Masselos, Kostas Stripf, Timo Oey, Oliver Becker, Juergen Goehringer, Diana Rauwerda, Gerard Sunesen, Kim Kritharidis, Dimitrios Mitas, Nikolaos Technological Educational Institute of Mesolonghi Greece

ISBN: (纸本)9781467322973;9781467322966

While advances in processor architecture continues to increase hardware parallelism, parallel software creation is hard. There is an increasing need for tools and methodologies to narrow the entry gap for non-experts in parallel software development as well as to streamline the work for experts. This paper presents the methodology and algorithms for the creation of parallel software written in Scilab source code for multicore embedded processors in the context of the "Architecture oriented paraLlelization for high performance embedded Multicore systems using scilAb" (ALMA) EU FP7 project. The ALMA parallelization approach in a nutshell attempts to manage the complexity of the task by alternating focus between very localized and holistic view program optimization strategies.

关键词： Software design

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RACOS: Transparent Access and Virtualization of Reconfigurable Hardware Accelerators 17

RACOS: Transparent Access and Virtualization of Reconfigurab...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Vatsolakis, Charalampos Pnevmatikatos, Dionisios Tech Univ Crete Sch Elect & Comp Engn Khania Greece Fdn Res & Technol Hellas Inst Comp Sci Iraklion Greece

ISBN: (纸本)9781538634370

Crafting accelerators using reconfigurable hardware is a promising way to achieve improved performance and power/energy efficiency. However, deploying reconfigurable accelerators is still cumbersome as it involves overall system integration issues and and runtime reconfigurable resource management. We describe the design and implementation of RACOS, a Reconfigurable ACcelerator OS, that provides a simple and intuitive software interface to load/unload reconfigurable hardware accelerators and perform data I/Os transparently to the user. Multiple partially reconfigurable regions are supported, and each region can host either single- or dual-threaded accelerators, effectively virtualizing the reconfigurable resources. RACOS allows multiple applications to use one or more accelerators each, and schedules accelerators for execution according to four policies: simple and inorder that respect the order of request, and out of order and forced that aim to reduce the number of reconfigurations. We evaluate our proposed system varying the number of instances of an accelerated application and show that, despite its generality, RACOS can achieve both high reconfiguration and data communication throughput, close to the maximum reported in bibliography, with a very small resource cost comparable or better than the current state of the art.

关键词： Hardware Software Field programmable gate arrays Throughput Acceleration Libraries Linux Field programmable gate arrays Accelerators hardware accelerator Linux reconfigurable hardware Throughput computer hardware acceleration Libraries computer software Virtualization configurability systems Integration software interface

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A Hybrid Approach for Mapping and Scheduling on Heterogeneous Multicore systems 16

A Hybrid Approach for Mapping and Scheduling on Heterogeneou...

引用

international conference on embedded computer systems - architectures, modeling and simulation (SAMOS)

作者： Emeretlis, A. Theodoridis, G. Alefragis, P. Voros, N. Univ Patras Dept Elect & Comp Engn Patras Greece TEI Western Greece Dept Comp & Informat Engn Antirio Greece

ISBN: (纸本)9781509030767

A hybrid approach for mapping applications represented as Directed Acyclic Graphs (DAGs) is introduced in this work. It combines the Benders decomposition principle, which integrates Integer Linear and Constraint Programming (ILP and CP) methods, with a pure ILP model to find optimal solutions. The cuts that are generated during the iterative Benders solution process are later exploited by the ILP solver to prune the remaining search space. The proposed model succeeds to provide the optimal solution in cases where either method alone fails to do so, while it also reduces the total solution time.

关键词： Multicore architectures Heterogeneous DAGs mapping Benders decomposition ILP - CP optimization

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Balanced Application-Specific Processor System for Efficient SIFT-Feature Detection 17

Balanced Application-Specific Processor System for Efficient...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Hartig, Julian Paya-Vaya, Guillermo Mentzer, Nico Blume, Holger Leibniz Univ Hannover Inst Microelect Syst Appelstr 4 D-30167 Hannover Germany

ISBN: (纸本)9781538634370

Due to its computational complexity, the Scale-Invariant Feature Transform (SIFT) algorithm poses a challenge for use in embedded applications. To meet real-time at low power, hardware acceleration is necessary. This paper presents an FPGA-based balanced processor system for real-time SIFT feature detection, containing a dedicated hardware coprocessor coupled to a custom VLIW soft-core processor using a FIFO memory. The coprocessor calculates the scale-space and performs the extrema detection for the extraction of feature candidates, whereas the VLIW soft-core processor performs sub-pixel localization and stability checks to get stable SIFT-features. The system achieves a peak frame rate of up to 338 fps on 1,024x376 px images at less than 3 W on a Xilinx Virtex-6 FPGA. The filters within the Gaussian pyramid operate in a time-multiplexed scheme on clock frequencies up to 400 MHz. Furthermore, this paper presents a comprehensive design space exploration, evaluating architectural performance, hardware resources and power consumption trade-offs as well as exposing performance-balanced and pareto-optimal design variants.

关键词： Feature extraction Hardware Field programmable gate arrays Coprocessors VLIW Throughput Real-time systems Field programmable gate arrays Coprocessors Very long instruction word computer hardware real-time systems Feature extraction Throughput PROCESSOR feature detections soft-core

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Mapping and performance evaluation for heterogeneous MP-SoCs via packing

引用

international conference on embedded computer systems - architectures, modeling and simulation

作者： Ristau, Bastian Fettweis, Gerhard Tech Univ Dresden Vodafone Chair Mobile Commun Syst D-01062 Dresden Germany

ISBN: (纸本)9783540736226

The computational demand of signal processing algorithms is rising continuously. Heterogeneous embedded multiprocessor systems-on-chips are one solution to tackle this demand. But to be able to take advantage of the benefits of these systems, new strategies are required how to map applications to such a system and how to evaluate the system's performance at a very early design stage. We will present a static, analytical, bottom-up methodology for temporal and spatial mapping of applications to MP-SoCs based on packing. Furthermore we will demonstrate how the result can be used for performance evaluation and system improvement without the need for simulations.

关键词： embedded systems

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The Design Space of the Number Theoretic Transform: a Survey 17

The Design Space of the Number Theoretic Transform: a Survey

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Valencia, Felipe Khalid, Ayesha O'Sullivan, Elizabeth Regazzoni, Francesco USI ALaRI Lugano Switzerland QUB CSIT Belfast North Ireland

ISBN: (纸本)9781538634370

The Number Theoretic Transform (NTT) is a necessary part of most Lattice-based cryptographic schemes. In particular, it offers an efficient means to achieve polynomial multiplication within the more efficient ring-based schemes. The NTT is also a crucial component which needs to be implemented in a critical way, since it is often the bottle-neck and the most resource consuming block of the whole design. As a result, the NTT is an appealing target for exploring different architectures and design trade-offs. In this paper, we compare various optimization strategies applied to maximize the performance or to reduce the resource utilization. Our analysis covers general purpose processors as well as dedicated hardware implemented on reconfigurable platforms and on ASIC. Previously explored design strategies range from the traditional computation where the multiplicative factors (called twiddle factors) are calculated on-the-fly versus memory trade-off exploration (using memory to store pre-computed twiddle factors), to the use of different butterfly designs for implementing the Fast Fourier Transform and its inverse in software, or the sharing of resources for hardware implementations of the forward and inverse NTT. The problem of side channel resistance is also addressed, discussing designs which are robust against power analysis attacks.

关键词： Cryptography Hardware Discrete Fourier transforms Lattices Software Resistance discrete Fourier transform computer hardware cryptography crystal lattices computer software Resource utilization computer programs Transform power analysis Inverse

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General Purpose Computing on Low-Power embedded GPUs: Has It Come of Age?

General Purpose Computing on Low-Power Embedded GPUs: Has It...

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13th international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Maghazeh, Arian Bordoloi, Unmesh D. Eles, Petru Peng, Zebo Linkoping Univ Dept Comp & Informat Sci S-58183 Linkoping Sweden

ISBN: (纸本)9781479901036

In this paper we evaluate the promise held by low-power GPUs for non-graphic workloads that arise in embedded systems. Towards this, we map and implement 5 benchmarks, that find utility in very different application domains, to an embedded GPU. Our results show that apart from accelerated performance, embedded GPUs are promising also because of their energy efficiency which is an important design goal for battery-driven mobile devices. We show that adopting the same optimization strategies as those used for programming high-end GPUs might lead to worse performance on embedded GPUs. This is due to restricted features of embedded GPUs, such as, limited or no user-defined memory, small instruction-set, limited number of registers, among others. We propose techniques to overcome such challenges, e.g., by distributing the workload between GPUs and multi-core CPUs, similar to the spirit of heterogeneous computation.

关键词： graphics processing units multiprocessing systems optimisation power supplies to apparatus

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An FPGA-based Prototyping Method for Verification, Characterization and Optimization of LDPC Error Correction systems

An FPGA-based Prototyping Method for Verification, Character...

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international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Sakellariou, P. Tsatsaragkos, I. Kanistras, N. Mahdi, A. Paliouras, V. Univ Patras Elect & Comp Engn Dept Patras 26500 Greece

ISBN: (纸本)9781467322973;9781467322966

This paper introduces a methodology for forward error correction (FEC) architectures prototyping, oriented to system verification and characterization. A complete design flow is described, which satisfies the requirement for error-free hardware design and acceleration of FEC simulations. FPGA devices give the designer the ability to observe rare events, due to tremendous speed-up of FEC operations. A Matlab-based system assists the investigation of the impact of very rare decoding failure events on the FEC system performance and the finding of solutions which aim to parameters optimization and BER performance improvement of LDPC codes in the error floor region. Furthermore, the development of an embedded system, which offers remote access to the system under test and verification process automation, is explored. The presented here prototyping approach exploits the high-processing speed of FPGA-based emulators and the observability and usability of software-based models.

关键词： LDPC FPGA emulation embedded systems verification code characterization error correcting performance

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A Unifying Logic Encryption Security Metric 18

A Unifying Logic Encryption Security Metric

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18th international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Sisejkovic, Dominik Leupers, Rainer Ascheid, Gerd Metzner, Simon Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst Aachen Germany Hensoldt Cyber GmbH Ottobrunn Germany

ISBN: (纸本)9781450364942

The globalization of the IC supply chain has brought forth the era of fabless companies. Due to security issues during design and fabrication processes, various security concerns have risen, ranging from IP piracy and reverse engineering to hardware Trojans. Logic encryption has emerged as a mitigation against these threats. However, no generic metrics for quantifying the security of logic encryption algorithms has been reported so far, making it impossible to formally compare diferent approaches. In this paper, we propose a unifying metric, capturing the key security aspects of logic encryption algorithms. The metric is evaluated on state-of-the- art algorithms and benchmarks.

关键词： Hardware security security metrics obfuscation logic encryption

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