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international conference on embedded computer systems - architectures, modeling and simulation

作者： Wu, Kehuai Madsen, Jan Tech Univ Denmark Dept Informat & Math Modelling Lyngby Denmark

ISBN: (纸本)9781424410583

Dynamically reconfigurable systems demand complicated run-time management. Due to resource constraints and reconfiguration latencies, efficient reconfiguration strategies that can reduce the overhead cost of dynamic reconfiguration need to be studied. In this paper, we i) propose a reconfigurable task model which extends the classical real-time task model to support the additional states and latencies needed to capture dynamically reconfigurable behavior, ii) propose a coprocessor-coupled reconfigurable architecture which has hardware run-time support for task execution, task reallocation and resource management, and iii) present a SystemC based framework to model and simulate coprocessor-coupled reconfigurable systems. We illustrate how COSMOS may be used to capture the dynamic behavior of such systems and emphasize the need for capturing the system aspects of such systems in order to deal with future design challenges of dynamically reconfigurable systems.

关键词： Coprocessor

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Architecture Exploration of a Programmable Neural Network Processor for embedded systems 16

Architecture Exploration of a Programmable Neural Network Pr...

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international conference on embedded computer systems - architectures, modeling and simulation (SAMOS)

作者： Sung, Wonyong Park, Jinhwan Seoul Natl Univ Dept Elect & Comp Engn 1 Gwanak Ro Seoul 08826 South Korea

ISBN: (纸本)9781509030767

Deep neural network algorithms show very high performance, however increased amounts of arithmetic and memory accesses hinder their adoption to embedded systems. This paper explores a programmable neural network processing architecture that can efficiently execute feed-forward, recurrent, and convolutional deep neural networks. The neural network algorithms are transformed to matrix-vector multiplication operations, which are then executed using a very wide SIMD (Single Instruction Multiple Data) functional unit. Especially, the functional and the data-level parallelism are compared for this architecture exploration, and an auxiliary hardware support for data rearrangement is added. The simulation results show that the architecture with a 128-wide SIMD functional unit can execute deep neural network algorithms for voice command, gesture, and handwritten digit recognition in real-time.

关键词： deep neural network SIMD RNN CNN

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System-Level modeling and simulation of MPSoC Run-Time Management Using Execution Traces Analysis 19th

System-Level Modeling and Simulation of MPSoC Run-Time Manag...

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19th international conference on embedded computer systems: architectures, modeling, and simulation (SAMOS)

作者： Yang, S. Le Nours, S. Real, M. Mendez Pillement, S. Univ Nantes CNRS IETR UMR 6164 F-44000 Nantes France

ISBN: (纸本)9783030275624;9783030275617

Dynamic management of modern Multi-Processors System on Chip (MPSoC) become mandatory for optimization purpose. Evaluation of these managers is essential early in the design process to guarantee a reduced design cycle. However, most of the existing system-level simulation-based frameworks consider static application mapping and do not consider the run-time management effects. In this work, we present a modeling and simulation approach that allows integration of run-time management strategies in MPSoC system simulation. We have integrated the proposed approach in an industrial modeling and simulation framework. A case-study with seven applications running on a heterogeneous multicore platform is considered and different management strategies are evaluated according to latency and power consumption criteria.

关键词： System-level simulation Execution trace Run-time management strategies Heterogeneous multicore systems

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Effects of program compression

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JOURNAL OF systems ARCHITECTURE 2007年第10期53卷 679-688页

作者： Heikkinen, Jari Takala, Jarmo Tampere Univ Technol Inst Digital & Comp Syst FIN-33101 Tampere Finland

The size of the program code has become a critical design constraint in embedded systems, especially in handheld, battery operated devices. Large program codes require large memories, which increase the size and cost of the chip. In addition, the power consumption is increased due to higher memory I/O bandwidth. Program compression is one of the most often used methods to reduce the size of the program code. In this paper, two compression approaches, dictionary-based compression and instruction template-based compression, were evaluated on a customizable processor architecture with parallel resources. The effects on area and power consumption were measured. Dictionary-based compression reduced the area at best by 77% and power consumption by 73%. Instruction template-based compression resulted in increase in both area and power consumption and hence turned out to be impractical. (C) 2007 Elsevier B.V. All rights reserved.

关键词： TTA VLIW embedded computing dictionary compression instruction template

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European research in embedded systems

European research in embedded systems

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6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Tsarchopoulos, Panagiotis Embedded Systems Unit European Commission

ISBN: (纸本)3540364102

Digital information technology has revolutionized the world within less than four decades. It has taken the step from mainframe computers, mainly operated as hosts in computing centres, to desktops and laptops, connected by networks and found nearly on all office desks and tables today. computers have become every day tools deeply integrated into all kinds of activities of our life.

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Manycore Performance Analysis using Timed Configuration Graphs

Manycore Performance Analysis using Timed Configuration Grap...

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international conference on embedded computer systems -architectures, modeling and simulation

作者： Bengtsson, Jerker Svensson, Bertil Halmstad Univ Ctr Res Embedded Syst Halmstad Sweden

ISBN: (纸本)9781424445011

The programming complexity of increasingly parallel processors calls for new tools to assist programmers in utilising the parallel hardware resources. In this paper we present a set of models that we have developed to form part of a tool which is intended for iteratively tuning the mapping of dataflow graphs onto manycores. One of the models is used for capturing the essentials of manycores that are identified as suitable for signal processing and which we use as target architectures. Another model is the intermediate representation in the form of a timed configuration graph, describing the mapping of a dataflow graph onto a machine model. Moreover, this IR can be used for performance evaluation using abstract interpretation. We demonstrate how the models can be configured and applied in order to map applications on the Raw processor. Furthermore, we report promising results on the accuracy of performance predictions produced by our tool. It is also demonstrated that the tool can be used to rank different mappings with respect to optimisation on throughput and end-to-end latency.

关键词： Mapping

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Multi-objective optimal controller synthesis for heterogeneous embedded systems

Multi-objective optimal controller synthesis for heterogeneo...

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6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Jozwiak, Lech Gawlowski, Dominik Slusarczyk, Aleksander Eindhoven Univ Technol Fac Elect Engn POB 513 NL-5600 MB Eindhoven Netherlands

ISBN: (纸本)1424401550

The recent spectacular progress in modern microelectronics created a big stimulus towards development of mobile, autonomous, embedded and re-configurable systems, but also resulted in man), difficult to solve issues, as power and energy crisis or increased leakage power, that are especially serious for this sort of systems. What prevents the (re)configurable heterogeneous embedded systems from becoming one of the main practically used paradigms is mainly inadequate support of the development methodologies and EDA-tools for efficient mapping of applications and producing power, energy, and speed optimized systems. As a part of our research that aims at development of effective methods and EDA-tools for the heterogeneous (re-)configurable embedded system synthesis, we performed a comparative analysis of several representative commercial and academic synthesis methods and tools for the FPGA-targeted controller synthesis. In this paper, the automatic hardware synthesis for the heterogeneous embedded systems is considered, when focusing on the efficient multi-objective controller synthesis. In particular, a part of results and conclusions from our analysis, and effective solutions of some problems observed are discussed.

关键词： embedded systems

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Algorithmic and memory optimizations on multiple application mapping onto FPGAs 17

Algorithmic and memory optimizations on multiple application...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Sidiropoulos, Harry Koutras, Ioannis Soudris, Dimitrios Siozios, Kostas Natl Tech Univ Athens Sch Elect & Comp Engn Zografos Greece Aristotle Univ Thessaloniki Dept Phys Thessaloniki Greece

ISBN: (纸本)9781538634370

Field Programmable Gate Arrays (FPGAs) offer a low power flexible accelerator alternative due to their inherent parallelism. Reprogrammability, although its their key feature, it is used almost exclusively on design time due to the constrains imposed by the modern CAD tools that require even days to run and tens of GB of RAM. In order to effectively utilize FPGAs on run time we propose a novel methodology and the supporting toolflow that enable efficient mapping of multiple applications onto heterogeneous FPGAs. With the use of a floorplanning step, memory optimizations and custom memory allocators, we alleviate the constrains imposed by CAD tools, and provide a proof of concept that application mapping onto FPGAs can be done on run time. Experimental results prove the efficiency of the introduced solution, as we achieve application's mapping 40x faster on average compared to a state-of-art approach, without performance degradation and with 12x on average reduced memory usage.

关键词： Field programmable gate arrays Tools Kernel Random access memory Memory management Optimization Hardware Field programmable gate arrays random access machine Store management computer hardware Mapping onto Runtime Kernel Memory Memory design year

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Platform-aware Dynamic Data Type Refinement Methodology for Radix Tree Data Structures 15

Platform-aware Dynamic Data Type Refinement Methodology for ...

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international conference on embedded computer systems architectures modeling and simulation

作者： Papastergiou, Thomas Papadopoulos, Lazaros Soudris, Dimitrios Natl Tech Univ Athens Sch Elect & Comp Engn GR-10682 Athens Greece

ISBN: (纸本)9781467373111

Modern embedded systems are now capable of executing complex and demanding applications that are often based on large data structures. The design of the critical data structures of the application affects the performance and the memory requirements of the whole system. Dynamic Data Structure Refinement methodology provides optimizations, mainly in list and array data structures, which are based on the application's features and access patterns. In this work, we extend various aspects of the methodology: First, we integrate radix tree optimizations. Then, we provide a set of platform-aware data structure implementations, for performing optimizations based on the hardware features. The extended methodology is evaluated using a wide set of synthetic and real-world benchmarks, in which we achieved performance and memory trade-offs up to 29.6%. Additionally, Pareto optimal data structure implementations that were not available by the previous methodology, are identified with the extended one.

关键词： Data structures memory requirements Root Radix Base of a number system tree data structures embedded systems data types Refining Not Available computer hardware

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MPSoCSim: An extended OVP Simulator for modeling and Evaluation of Network-on-Chip based heterogeneous MPSoCs 15

MPSoCSim: An extended OVP Simulator for Modeling and Evaluat...

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international conference on embedded computer systems architectures modeling and simulation

作者： Wehner, Philipp Rettkowski, Jens Kleinschmidt, Tobias Goehringer, Diana Ruhr Univ Bochum Bochum Germany

ISBN: (纸本)9781467373111

In this paper a SystemC simulator for Network-on-Chip (NoC) based Multiprocessor systems-on-Chip (MPSoCs) is presented. The simulator currently supports mesh topology with wormhole switching and several routing algorithms such as XY-, a minimal West-First and an adaptive West-First algorithm. The impact of routing algorithms regarding performance can be analyzed by means of the presented simulator. In order to simulate a heterogeneous MPSoC, ARM processors and MicroBlazes can be attached to the NoC. Processor and peripheral models used within the test platforms are provided by Imperas/OVP. Moreover, traffic generators are available to analyze the system. An additional SystemC component enables the readout of simulation time from within the application. For evaluation of the simulator multiple platforms and applications were put under test and compared with a hardware implementation. The comparison shows that the simulator improves the development of MPSoCs by early estimation of system requirements.

关键词： MPSoC simulator Network-on-Chip heterogeneous MPSoC routing algorithms OVP

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