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Energy efficient stream-based configurable architecture for embedded platforms

Energy efficient stream-based configurable architecture for ...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Frederico Pratas Pedro Tomás Pedro Trancoso Leonel Sousa INESC-ID/IST Technical University of Lisbon Lisbon Portugal Department of Computer Science University of Cyprus Nicosia Cyprus

Reconfigurable hardware can be used as an energy and performance efficient co-processing solution to accelerate certain types of applications. To facilitate the design of hardware accelerators we have proposed a methodology that adopts the stream-based computing model and the usage of Graphics Processing Units as prototyping platforms. In this paper we go a step further and propose a new modular architecture for low-power reconfigurable systems to easily map the stream-based algorithms. In particular, the architecture consists of a semi-programable accelerator set that can be adapted to the application needs in terms of functional units and number of streaming engines. The proposed embedded architecture mates the flexibility of reconfigurable hardware with the advantages of stream computing for the strict needs of embedded reconfigurable devices. We show a possible organization for this architecture. Moreover, we provide a general case study to analyze the scalability of the proposed architecture in an Altera FPGA. Our experimental results show that a significant speed-up can be achieved compared to general purpose processors using low-power FPGA devices. Our preliminary estimates show that it is also possible to achieve energy savings of up to 118x.

关键词： computer architecture Hardware Kernel Algorithm design and analysis Organizations Field programmable gate arrays Program processors

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Rigorous design of cyber-physical systems

Rigorous design of cyber-physical systems

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Joseph Sifakis EPFL and Verimag Laboratory France

Cyber-physical systems (CPS) break with traditional systems such as desktop computers and servers, in various ways: (1) they are instrumented in order to interact with physical environments; (2) they are interconnected to allow interaction between people and objects in entirely new modes; (3) they must be smart to ensure predictability of events and optimal use of resources. Currently, we lack theory methods and tools for building cost-effectively trustworthy CPS. In this talk, I will show how and why CPS challenge our capabilities for ensuring their trustworthiness. I will advocate for a coherent scientific foundation of CPS design and will discuss three main scientific challenges: (1) Marrying physicality and computation; (2) Correctness-by-construction; (3) Adaptivity. Meeting these challenges is a prerequisite for moving from empirical to rigorous design. This can be formalized as a sound, scalable and accountable process leading to trustworthy and optimized implementations from: (1) an application software; (2) models of its execution infrastructure; and (3) models of its physical environment. Soundness is achieved through translation of the languages used along the design process into a single and expressive host language rooted in clean operational semantics. Scalability and accountability can be ensured by using correct-by-construction source-to-source transformations in the host language. The talk will conclude with an overview of the BIP rigorous design flow developed at Verimag and EPFL.

关键词： Computational modeling Adaptation models Laboratories Abstracts computers Servers Instruments

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An efficient asymmetric distributed lock for embedded multiprocessor systems

An efficient asymmetric distributed lock for embedded multip...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Jochem H. Rutgers Marco J.G. Bekooij Gerard J.M. Smit Department of EEMCS University of Twente AE Enschede The Netherlands

Efficient synchronization is a key concern in an embedded many-core system-on-chip (SoC). The use of atomic read-modify-write instructions combined with cache coherency as synchronization primitive is not always an option for shared-memory SoCs due to the lack of suitable IP. Furthermore, there are doubts about the scalability of hardware cache coherency protocols. Existing distributed locks for NUMA multiprocessor systems do not rely on cache coherency and are more scalable, but exchange many messages per lock. This paper introduces an asymmetric distributed lock algorithm for shared-memory embedded multiprocessor systems without hardware cache coherency. Messages are exchanged via a low-cost inter-processor communication ring in combination with a small local memory per processor. Typically, a mutex is used over and over again by the same process, which is exploited by our algorithm. As a result, the number of messages exchanged per lock is significantly reduced. Experiments with our 32-core system show that when having locks in SDRAM, 35% of the memory traffic is lock related. In comparison, our solution eliminates all of this traffic and reduces the execution time by up to 89%.

关键词： Synchronization Servers Tiles System-on-a-chip Hardware SDRAM Bandwidth

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A co-simulation approach for system-level analysis of embedded control systems

A co-simulation approach for system-level analysis of embedd...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Michael Glaß Jürgen Teich Liyuan Zhang Friedrich-Alexander-Universitat Erlangen-Nurnberg Erlangen Bayern DE Hardware/Software Co-Design University of Erlangen-Nuremberg

Control applications have become an integral part of modern networked embedded systems. However, there often exists a gap between control engineering and system design. The control engineer has detailed knowledge about the algorithms but is abstracting from the system architecture and implementation. On the other hand, the system designer aims at achieving high-quality implementations based on quality constraints specified by the control engineer. This may result in either an overdesigned system in case the specifications are pessimistic or an unsafe system behavior when specifications are too optimistic. Thus, future design automation approaches have to consider the quality of control applications both as design objectives and design constraints to achieve safe yet highly optimized system implementations. The work at hand introduces an automatic tool flow at the Electronic System Level (ESL) that enables the optimization of a system implementation with quality of control being introduced as a principal design objective, like the maximum braking distance, while respecting constraints like maximum slip to ensure maneuverability of a car. The gap between mathematically well-defined models for system synthesis and common analysis techniques for control quality is bridged by co-simulation: A SystemC-based virtual prototype of a distributed controller implementation is combined with high-level models of the plants specified in Matlab/Simulink. Through a model transformation, the traditional development process of control applications is combined with state-of-the-art ESL techniques, ensuring model consistency while enabling a high degree of automation.

关键词： Sensors Actuators MATLAB Delay

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Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures

Towards future adaptive multiprocessor systems-on-chip: An i...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Fabrice Lemonnier Philippe Millet Gabriel Marchesan Almeida Michael Hübner Jürgen Becker Sébastien Pillement Olivier Sentieys Martijn Koedam Shubhendu Sinha Kees Goossens Christian Piguet Marc-Nicolas Morgan Romain Lemaire Thales Research & Technology Palaiseau cedex Institute of Information Processing Technology Karlsruhe Institute of Technology (KIT) Karlsruhe Germany Embedded Systems for Information Technolozv Ruhr-University Bochum Bochum Germany University of Rennes 1- IRISA Lannion France Universite de Rennes 1 Rennes Bretagne FR Eindhoven University of Technology Eindhoven The Netherlands Centre Suisse d'Electronique et de Microtechnique SA Neuchatel NeuchÃ¢tel CH CEA-Leti Minatec Campus Grenoble France

This paper introduces adaptive techniques targeted for heterogeneous manycore architectures and introduces the FlexTiles platform, which consists of general purpose processors with some dedicated accelerators. The different components are based on low power DSP cores and an eFPGA on which dedicated IPs can be dynamically configured at run-time. These features enable a breakthrough in term of computing performance while improving the on-line adaptive capabilities brought from smart heuristics. Thus, we propose a virtualisation layer which provides a higher abstraction level to mask the underlying heterogeneity present in such architectures. Given the large variety of possible use cases that these platforms must support and the resulting workload variability, offline approaches are no longer sufficient because they do not allow coping with time changing workloads. The upcoming generation of applications include smart cameras, drones, and cognitive radio. In order to facilitate the architecture adaptation under different scenarios, we propose a programming model that considers both static and dynamic behaviors. This is associated with self adaptive strategies endowed by an operating system kernel that provides a set of functions that guarantee quality of service (QoS) by implementing runtime adaptive policies. Dynamic adaptation will be mainly used to reduce both overall power consumption and temperature and to ease the problem of decreasing yield and reliability that results from submicron CMOS scales.

关键词： computer architecture Digital signal processing Program processors Hardware Nickel Quality of service Power demand

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Predictable dynamic embedded data processing

Predictable dynamic embedded data processing

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Marc Geilen Sander Stuijk Twan Basten Eindhoven University of Technology Department of Electrical Engineering Eindhoven The Netherlands Embedded Systems Institute Eindhoven The Netherlands

Cyber-physical systems interact with their physical environment. In this interaction, non-functional aspects, most notably timing, are essential to correct operation. In modern systems, dynamism is introduced in many different ways. The additional complexity threatens timely development and reliable operation. Applications often have different modes of operation with different resource requirements and different levels of required quality-of-service. Moreover, multiple applications in dynamically changing combinations share a platform and its resources. To preserve efficient development of such systems, dynamism needs to be taken into account as a primary concern, not as a verification or tuning effort after the design is done. This requires a model-driven design approach in which timing of interaction with the physical environment is taken into consideration; formal models capture applications and their platforms in the physical environment. Moreover, platforms with resources and resource arbitration are needed that allow for predictable and reliable behavior to be realized. Run-time management is further required to deal with dynamic use-cases and dynamic trade-offs encountered at run-time. In this paper, we present a model-driven approach that combines model-based design and synthesis with development of platforms that support predictable, repeatable, composable realizations and a run-time management approach to deal with dynamic use-cases at run-time. A formal, compositional model is used to exploit Pareto-optimal trade-offs in the system use. The approach is illustrated with dataflow models with dynamic application scenarios, a predictable platform architecture and run-time resource management that determines optimal trade-offs through an efficient knapsack heuristic.

关键词： Tiles Payloads Computational modeling Schedules Hardware Synchronization

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System-on-Chip deployment with MCAPI abstraction and IP-XACT metadata

System-on-Chip deployment with MCAPI abstraction and IP-XACT...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Lauri Matilainen Lasse Lehtonen Joni-Matti Määttä Erno Salminen Timo D. Hämäläinen Department of Computer Systems Tampere University of Technology Tampere Finland

IP-XACT, the recent IEEE1685 standard, defines metadata format for IP packing and integration in System-on-Chip designs. It was originally proposed for hardware descriptions, but we have extended it for software, HW/SW mappings and application communication abstraction. The latter is realized with Multicore Association MCAPI that is a lightweight message passing interface. In this paper we present as a work-in-progress how we utilize all these to deploy and move application tasks between different platforms for FPGA prototyping, execution acceleration or verification. The focus is on the metadata format since it is a foundation for automation and tool development. The design flow is illustrated with two case studies: A motion JPEG encoder and a 12-node workload model of video object plane decoder (VOPD). These are deployed to PC and Altera and Xilinx FPGA boards in five variations. The results are reported as the deployment time for both non-recurring and deployment specific tasks. Setting up a new deployment is a matter of hours when there is an IP-XACT library of HW and SW components.

关键词： System analysis and design Libraries Field programmable gate arrays System-on-a-chip Standards IP networks Generators

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Memory bounds for the distributed execution of a hierarchical Synchronous Data-Flow graph

Memory bounds for the distributed execution of a hierarchica...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Karol Desnos Maxime Pelcat Jean-Francois Nezan Slaheddine Aridhi IETR INSA Rennes CNRS UMR 6164 UEB Rennes Texas Instruments France Villeneuve Loubet France

This paper presents an application analysis technique to define the boundary of shared memory requirements of Multiprocessor System-on-Chip (MPSoC) in early stages of development. This technique is part of a rapid prototyping process and is based on the analysis of a hierarchical Synchronous Data-Flow (SDF) graph description of the system application. The analysis does not require any knowledge of the system architecture, the mapping or the scheduling of the system application tasks. The initial step of the method consists of applying a set of transformations to the SDF graph so as to reveal its memory characteristics. These transformations produce a weighted graph that represents the different memory objects of the application as well as the memory allocation constraints due to their relationships. The memory boundaries are then derived from this weighted graph using analogous graph theory problems, in particular the Maximum-Weight Clique (MWC) problem. State-of-the-art algorithms to solve these problems are presented and a heuristic approach is proposed to provide a near-optimal solution of the MWC problem. A performance evaluation of the heuristic approach is presented, and is based on hierarchical SDF graphs of realistic applications. This evaluation shows the efficiency of proposed heuristic approach in finding near optimal solutions.

关键词： Memory management Resource management Computational modeling Schedules Heuristic algorithms Context

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K-Periodic schedules for evaluating the maximum throughput of a Synchronous Dataflow graph

K-Periodic schedules for evaluating the maximum throughput o...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Bruno Bodin Alix Munier-Kordon Benoît Dupont de Dinechin KALRAY SA Montbonnot FRANCE LIP6-UPMC Place Jussieu Paris FRANCE

Synchronous Dataflow graphs, introduced by Lee and Messerschmitt in 1987, are a well-known formalism commonly used to model data-exchanges between parallel processes. This model was extensively studied in the last two decades because of the importance of its applications. However, the determination of a maximal throughput is a difficult question, for which no polynomial time algorithm exists to date. In this context, several authors proved that a K-Periodic schedule, where K is a vector of no polynomially bounded values, reaches the maximum throughput. On the other hand, a 1-Periodic schedule may be built polynomially, but without any guarantee on the throughput achieved. Therefore, the investigated problem is the trade-off between the schedule size induced by the vector K (called the periodicity vector) and its corresponding throughput. Necessary and sufficient conditions for the existence of K-Periodic schedules are first shown for any fixed value in the vector K; the computation of the maximum throughput of a K-Periodic schedule is deduced. A set of dominant values of K is exhibited, and a relationship between the optimal throughput of these values is proved. Some real-life experiments measure the variation of the throughput according to K.

关键词： Schedules Throughput Vectors Polynomials Computational modeling Complexity theory Production

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A quantitative analysis of fixed-point LDPC-decoder implementations using hardware-accelerated HDL emulations

A quantitative analysis of fixed-point LDPC-decoder implemen...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Matthias Korb Tobias G. Noll Chair of Electrical Engineering and Computer Systems RWTH Aachen University Aachen Germany

Using hardware-accelerated HDL emulators of fixed-point implementations has several advantages in comparison to C-based simulations: The high degree of parallelism for example of field-programmable gate-array based hardware accelerators promise an increased emulation throughput. Furthermore, the HDL model of the considered circuit can be used in the following design process making an additional verification dispensable. For a system analysis of different low-density parity-check (LDPC) decoders such an emulator is practically inevitable from a throughput perspective: the outstanding error correction capability of those decoders allowing for bit-error rates (BER) of well below 10 -10 requires a simulative decoding of billions of blocks. In this work, an HDL-based emulator is used. The designed HDL model is highly parameterizable and includes an LDPC decoder and high-quality Box-Muller-based white Gaussian-noise generators to create rare error-events. Using this emulator a comparison of the decoding capability of different fixed-point decoder implementations has been performed. Additionally, accurate cost-models are used for estimating the hardware costs of the different decoder implementations which enable an identification of Pareto-optimal decoder implementations. Finally, the achievable emulator throughput is discussed and compared to the simulation throughput of a speed optimized C-model.

关键词： Decoding Noise Hardware Iterative decoding Algorithm design and analysis Hardware design languages

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