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Reconfigurable miniature sensor nodes for condition monitoring

Reconfigurable miniature sensor nodes for condition monitori...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Teemu Nyländen Jani Boutellier Karri Nikunen Jari Hannuksela Olli Silvén Computer Science and Engineering Laboratory Electronics Laboratory University of Oulu Finland

The wireless sensor networks are being deployed at escalating rate for various application fields. The ever growing number of application areas requires a diverse set of algorithms with disparate processing needs. The wireless sensor networks also need to adapt to the prevailing energy conditions and processing requirements. The preceding reasons rule out the use of a single fixed design. Instead a general purpose design that can rapidly adapt to different conditions and requirements is desired. In lieu of the traditional inflexible wireless sensor node consisting of a micro-controller, radio transceiver, sensor array and energy storage, we propose a rapidly reconfigurable miniature sensor node, implemented with a transport triggered architecture processor on a low-power Flash FPGA. Also power consumption and silicon area usage comparison between 16-bit fixed and floating point and 32-bit floating point implementations is presented in this paper. The implemented processors and algorithms are intended for rolling bearing condition monitoring, but can be fully extended for other applications as well.

关键词： Wireless sensor networks Algorithm design and analysis Silicon Power demand Monitoring Energy storage Condition monitoring

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A template-based methodology for efficient microprocessor and FPGA accelerator co-design

A template-based methodology for efficient microprocessor an...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Angeliki Kritikakou Francky Catthoor George S. Athanasiou Vasilios Kelefouras Costas Goutis Dep. Electrical & Computer Engineering Univ. of Patras Patras Greece Dep. Electrical Engineering (ESAT) Inter-university Micro-Electronics (IMEC) KULeuven Leuven Belgium

embedded applications usually require Software/Hardware (SW/HW) designs to meet the hard timing constraints and the required design flexibility. Exhaustive exploration for SW/HW designs is a very time consuming task, while the adhoc approaches and the use of partially automatic tools usually lead to less efficient designs. To support a more efficient codesign process for FPGA platforms we propose a systematic methodology to map an application to SW/HW platform with a custom HW accelerator and a microprocessor core. The methodology mapping steps are expressed through parametric templates for the SW/HW Communication Organization, the Foreground (FG) Memory Management and the Data Path (DP) Mapping. Several performance-area tradeoff design Pareto points are produced by instantiating the templates. A real-time bioimaging application is mapped on a FPGA to evaluate the gains of our approach, i.e. 44,8% on performance compared with pure SW designs and 58% on area compared with pure HW designs.

关键词： Program processors Kernel IP networks Memory management Organizations Real-time systems Field programmable gate arrays

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From Scilab to multicore embedded systems: Algorithms and methodologies

From Scilab to multicore embedded systems: Algorithms and me...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： George Goulas Panayiotis Alefragis Nikolaos S. Voros Christos Valouxis Christos Gogos Nikolaos Kavvadias Grigoris Dimitroulakos Kostas Masselos Diana Goehringer Steven Derrien Daniel Ménard Olivier Sentieys Michael Huebner Timo Stripf Oliver Oey Juergen Becker Gerard Rauwerda Kim Sunesen Dimitrios Kritharidis Nikolaos Mitas Technological Educational Institute of Mesolonghi Greece Technological Educational Institute of Epirus Greece University of Peloponnese Greece Fraunhofer-Institute of Optronics System Technologies and Image Exploitation Germany Université de Rennes I INRIA Research Institute France Ruhr-University of Bochum Germany Karlsruher Institut fur Technologie Karlsruhe Baden-WÃ¼rttemberg DE Karlsruhe Institute of Technology Germany Recore Systems The Netherlands Intracom S.A. Telecom Solutions Greece

While advances in processor architecture continues to increase hardware parallelism, parallel software creation is hard. There is an increasing need for tools and methodologies to narrow the entry gap for non-experts in parallel software development as well as to streamline the work for experts. This paper presents the methodology and algorithms for the creation of parallel software written in Scilab source code for multicore embedded processors in the context of the “Architecture oriented paraLlelization for high performance embedded Multicore systems using scilAb” (ALMA) EU FP7 project. The ALMA parallelization approach in a nutshell attempts to manage the complexity of the task by alternating focus between very localized and holistic view program optimization strategies.

关键词： Tiles Parallel processing Optimization Multicore processing Software VLIW

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RobotML, a domain-specific language to design, simulate and deploy robotic applications

RobotML, a domain-specific language to design, simulate and ...

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3rd international conference on simulation, modeling, and Programming for Autonomous Robots, SIMPAR 2012

作者： Dhouib, Saadia Kchir, Selma Stinckwich, Serge Ziadi, Tewfik Ziane, Mikal LIST Laboratory of Model Driven Engineering for Embedded Systems CEA Point Courrier 94 Gif-sur-Yvette F-91191 France UMR CNRS 7606 LIP6-MoVe Université Pierre et Marie Curie Paris France UMR CNRS 6072 GREYC Université de Caen-Basse Normandie ENSICAEN Caen France UMI IRD 209 UMMISCO IFI Vietnam National University Hanoi Viet Nam

ISBN: (纸本)9783642343261

A large number of robotic software have been developed but cannot or can hardly interoperate with each other because of their dependencies on specific hardware or software platform is hard-wired into the code. Consequently, robotic software is hard and expensive to develop because there is little opportunity of reuse and because low-level details must be taken into account in early phases. Moreover, robotic experts can hardly develop their application without programming knowledge or the help of programming experts and robotic software is difficult to adapt to hardware or target-platform changes. In this paper we report on the development of RobotML, a Robotic modeling Language that eases the design of robotic applications, their simulation and their deployment to multiple target execution platforms. © 2012 Springer-Verlag Berlin Heidelberg.

关键词： Robot programming

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2012 international conference on Mechanical Engineering and Intelligent systems, ICMEIS 2012

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2012 international conference on Mechanical Engineering and Intelligent systems, ICMEIS 2012

ISBN: (纸本)9783037854693

The proceedings contain 234 papers. The special focus in this conference is on the mechanical engineering and intelligent systems. The topics include: design and fluent simulation of impeller for axial maglev heart pump;stability of wind power turbine's magnetic bearing;the research of the CO2 wireless monitoring system based on TC35;study of FCLSD algorithm performance based on LTE system;direction of arrival estimation for coherent signals in GPS receiver;design and implementation of a trusted SoC chip;research on internet of things based on SOPC;subcarrier allocation in cognitive radio systems;identification and equalization of nonlinear channel based on ANFIS;a macromodel of memristor using symbolically defined devices;the application of I2C bus in mobile phone;frequency offset estimation in cell search for TD-SCDMA UE;reduced complexity FSD algorithm for MIMO detection;using composite classifier systems to predict protein locations;study on the mechanism of vigor change of phoebe zhennan seed;extraction of flavonoids from clovers;CoMSIA study of a series of n-dichloroacetyl oxazolidine derivatives;physico-chemically weighted kernel for SVM protein classification;estimation of forest carbon storage based on airborne LiDAR data;energy balance analysis in Hainan province's agriculture sector;comprehensive diagnosis of kuyehe flood series change-point;research on Chinese named entity recognition based on ontology;research on the EM modeling of optimization of PCB grounded via;research and application of human-simulated intelligent controller;the control and model of synchronous generator on ship;crash recovery for embedded main memory database and design a kind of family embedded health care system.

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OSR-Lite: Fast and deadlock-free NoC reconfiguration framework

OSR-Lite: Fast and deadlock-free NoC reconfiguration framewo...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Alessandro Strano Davide Bertozzi Francisco Triviño José L. Sánchez Francisco J. Alfaro José Flich University of Ferrara ENDIF Department Ferrara Italy Universidad de Castilla-La Mancha Computing Systems Department s/n Albacete Spain Universitat Politécnica de Valéncia Department of Computer Engineering Valencia Spain

Current and future on-chip networks will feature an enhanced degree of reconfigurability. Power management and virtualization strategies as well as the need to survive to the progressive onset of wear-out faults are root causes for that. In all these cases, a non-intrusive and efficient reconfiguration method is needed to allow the network to function uninterruptedly over the course of the reconfiguration process while remaining deadlock-free. This paper is inspired by the overlapped static reconfiguration (OSR) protocol developed for off-chip networks. However, in its native form its implementation in NoCs is out-of-reach. Therefore, we provide a careful engineering of the NoC switch architecture and of the system-level infrastructure to support a cost-effective, complete and transparent reconfiguration process. Performance during the reconfiguration process is not affected and implementation costs (critical path and area overhead) are proved to be fully affordable for a constrained system. Less than 250 cycles are needed for the reconfiguration process of an 8×8 2D mesh with marginal impact on system performance.

关键词： Routing Switches System recovery System-on-a-chip Protocols Network topology

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Counting stream registers: An efficient and effective snoop filter architecture

Counting stream registers: An efficient and effective snoop ...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Aanjhan Ranganathan Ali Galip Bayrak Theo Kluter Philip Brisk Edoardo Charbon Paolo Ienne ETH Zürich System Security Group Zürich Switzerland Ecole Poly technique Fédérale de Lausanne (EPFL) School of Computer and Communication Sciences Lausanne Switzerland Department of Engineering and Information Technology Bern University of Applied Sciences Bern Switzerland Department of Computer Science and Engineering University of California Riverside Riverside CA USA Department of Micro-electronics and Computer Engineering Delft University of Technology Delft The Netherlands

We introduce a counting stream register snoop filter, which improves the performance of existing snoop filters based on stream registers. Over time, this class of snoop filters loses the ability to filter memory addresses that have been loaded, and then evicted, from the caches that are filtered; they include cache wrap detection logic, which resets the filter whenever the contents of the cache have been completely replaced. The counting stream register snoop filter introduced here replaces the cache wrap detection logic with a direct-mapped update unit and augments each stream register with a counter, which acts as a validity checker; loading new data into the cache increments the counter, while replacements, snoopy invalidations, and evictions decrement it. A cache wrap is detected whenever the counter reaches zero. Our experimental evaluation shows that the counting stream register snoop filter architecture improves the accuracy compared to traditional stream register snoop filters for representative embedded workloads.

关键词： Registers Radiation detectors Benchmark testing Energy consumption Information filters

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Simultaneous reconfiguration of issue-width and instruction cache for a VLIW processor

Simultaneous reconfiguration of issue-width and instruction ...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Fakhar Anjam Stephan Wong Luigi Carro Gabriel L. Nazar Mateus B. Rutzig Computer Engineering Laboratory Delft University of Technology Delft The Netherlands Instituto de Informatica Universidade Federal Do Rio Grande Do Sui Bairro Agronomia - Porto Alegre - RS Brasil

This paper presents an analysis on the impact of simultaneous instruction cache (I-cache) and issue-width reconfiguration for a very long instruction word (VLIW) processor. The issue-width of the processor can be adjusted at run-time to be 2-issue, 4-issue, or 8-issue, and the I-cache can be reconfigured in terms of associativity, cache size, and line *** observe that, compared to reconfiguring only the I-cache for a fixed issue-width core, reconfiguring the issue-width and I-cache together can further reduce the execution time, energy consumption, and/or the energy-delay product (EDP). The results for the MiBench and the PowerStone benchmark suites show that compared to “2-issue + the best I-cache”, “4-issue + the best I-cache” can reduce execution time, energy consumption, and EDP by up to 37%, 11%, and 36%, respectively, for different applications. Similarly, compared to “2-issue + the best I-cache”, “8-issue + the best I-cache” can reduce execution time and EDP by up to 46% and 30%, respectively, for different applications.

关键词： Energy consumption VLIW Registers Benchmark testing Tuning Power demand Organizations

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Hardware/software specialization through aspects: The LARA approach

Hardware/software specialization through aspects: The LARA a...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： João M. P. Cardoso Tiago Carvalho João Teixeira Pedro C. Diniz Fernando Gonçalves Zlatko Petrov Universidade do Porto Porto Porto PT Departamento de Engenharia Informatica Universidade do Porto Faculdade de Engenharia (FEUP) Porto Portugal INESC-ID Lisboa Portugal CoreWorks S.A Lisboa Portugal Honeywell International s.r.o Czech Republic

LARA is a programming language being developed to complement application code in a host programming language with instrumentation code, for monitoring, logging, and debugging, user's knowledge about specific characteristics of the application, non-functional requirements, and compiler, mapping and synthesis strategies to guide/control design-flows, especially the ones used to map computations to FPGA-based systems. This paper shows how the aspect-oriented approach provided by LARA allows developers to specify complementary program information that can be used by LARA aware design-flows to promote customized FPGA-based software/hardware implementations. Program and compiler/mapping specialization take advantage of specific properties of applications to optimize and customize specific application modules and software/hardware implementations, e.g., according to usage contexts. We illustrate the concept using a hotspot function from a real-life, industrial, application. The results show the importance of program specialization in deriving hardware/software implementations with higher-performance.

关键词： Hardware Context Software Optimization Arrays Field programmable gate arrays

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An FPGA-based probability-aware fault simulator

An FPGA-based probability-aware fault simulator

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： David May Walter Stechele Technische Universitat Munchen Munchen Bayern DE

A recent approach to deal with the challenges that come along with the shrinking feature size of CMOS circuits is probabilistic computing. Those challenges, such as noise or process variations, result in a certain probabilistic behavior of the circuit and its gates. Probabilistic Computing, also referred to as pCMOS, does not try to avoid the occurrence of errors, but tries to determine the probability of errors at the output of the circuit, and to limit it to a value that the specific application can tolerate. Past research has shown that probabilistic computing has potential to drastically reduce the power consumption of circuits by scaling the supply voltage of gates to a value where they become non-deterministic, while tolerating a certain amount of probabilistic behavior at the output. Therefore, one main task in the design of pCMOS circuits is to determine the error probabilities at the output of the circuit, given a combination of error probabilities at the gates. In earlier work, pCMOS circuits have been characterized by memory-consuming and complex analytical calculations or by time-consuming software-based simulations. Hardware-accelerated emulators exist in large numbers, but miss the support of injecting errors with specified probabilities into as many circuit elements the user specifies at the same time. In this paper, we propose an FPGA-based fault simulator that allows for fast error probability classification, injection of errors at gate- and RT-level, and that is furthermore independent on the target architecture. Moreover, we demonstrate the usefulness of such a simulator by characterizing the probabilistic behavior of two benchmark circuits and reveal their energy-saving capability.

关键词： Integrated circuit modeling Error probability Field programmable gate arrays Probabilistic logic Instruments Logic gates Circuit faults

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