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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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Physical modeling of Concrete-Core-Radiant cooling system in Upper-Egypt

Physical modeling of Concrete-Core-Radiant cooling system in...

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10th Annual international Energy Conversion Engineering conference, IECEC 2012

作者： Fahim, Ahmed A. Medhat A. Electro-Mechanical Research Institute Housing and Building National Research Centre HBRC 1770-Giza Cairo Egypt

ISBN: (纸本)9781624101908

Building envelope heat gain in tropic regions is considered as one of the affecting portions on the global building thermal loads, for that, cooling with ventilation are mandatory for about nine months per year. Different treatments for controlling building envelope, thermal storage and its peaks were investigated. This paper is devoted to the physical modeling for Thermally Activated Building systems 'TABS' especially the Concrete-Core-Radiant-Slab, 'CCRS' cooling system in roofs and typical partitioned slab constructions. These investigations were achieved by using five real standard size samples having 0.75 m Length, 0.75 m Width, 0.12 m Thickness with embedded 15mm diameter plastic PE pipes with different layouts, on which each construction is exposed to conditions similar to reality. With the aid of custom made test facility, external slabs surface, slab core temperatures, embedded pipe temperatures and heat flux intensities were experimentally measured during simulated climatic condition periods at Al-Minya governorate, the first southern city at Upper Egypt governorates. Climatic conditions were simulated based on averaged weekly temperature distributions recorded over a year leading to real year simulation within real 52-Days 'The duration of one experiment'. Measurements are conducted with the aid of state-of-the-art probes and sensing elements that wired to data acquisition and controlling unit which are managed via pre-programmed computer handmade software. Almost two months were required to execute one experiment. Each experiment provides valuable and huge collected data. These gained data allow for better understanding of the actual behaviors of TAB system and the expectations of the thermal impacts on buildings. While, results show that CCRS can not work alone for exposed roofs without external shading and efficient thermal insulation. Although, TAB system shows an effective cooling capacity from 40.0W/m2 to 55.0W/m2 but it can shave the peak loads and

关键词： Roofs

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Architecture-level fault-tolerance for biomedical implants

Architecture-level fault-tolerance for biomedical implants

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Robert M. Seepers Christos Strydis Georgi N. Gaydadjiev Faculty of Electrical Engineering Mathematics and Computer Science Delft University of Technology Netherlands Department of Computer Science and Engineering Chalmers University of Technology Sweden

In this paper, we describe the design and implementation of a new fault-tolerant RISC-processor architecture suitable for a design framework targeting biomedical implants. The design targets both soft and hard faults and is original in efficiently combining as well as enhancing classic fault-tolerance techniques. The proposed architecture allows run-time tradeoffs between performance and fault tolerance by means of instruction-level configurability. The system design is synthesized for UMC 90nm CMOS standard-process and is evaluated in terms of fault coverage, area, average power consumption, total energy consumption and performance for various duplication policies and test-sequence schedules. It is shown that area and power overheads of approximately 25% and 32%, respectively, are required to implement our techniques on the baseline processor. The major overheads of the proposed architecture are performance (up to 107%) and energy consumption (up to 157%). It is observed that the average power consumption is often reduced when a higher degree of fault tolerance is targeted. It is shown that test sequences can effectively be scheduled during the available program stalls and that nearly all soft faults are tolerated by using instruction duplication. The main advantages of the proposed architecture are the high portability of the introduced architecture-level fault-tolerance techniques, the flexibility in trading processor overheads for required fault-tolerance degree as well as affordable area and power consumption overheads.

关键词： Fault tolerance Fault tolerant systems Circuit faults Registers Runtime Hardware computer architecture

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BEE technology overview

BEE technology overview

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Joseph Rothman Chen Chang BEE cube Fremont CA USA

This presentation will focus on a technology overview of the BEE4 and miniBEE FPGA based reconfigurable platforms. BEEcube supplies advanced system level FPGA prototyping platforms, targeting a wide range of uses including: multi-core computer architecture, wireless communications, 100Gbps+ networking solutions, HD video processing, signal intelligence, radar/sonar array, and High Performance Computing (HPC) needs. This overview will review features, capabilities, unique technology and uses of BEE platforms on both, its state of the art Virtex 6 based multi-array FPGA BEE4™ system, and introduce the first Research in a Box solution, the miniBEE™. miniBEE offers a combination of the latest FPGA, multicore CPU, high-speed networking technology all tightly coupled in one integrated cost effective solution targeting the research and lab community. This flexible system replaces the need for disjointed FPGA boards, PCs, networking devices, and test equipment. The presentation will describe how both algorithm oriented researchers as well as seasoned FPGA experts can utilize BEE technology to achieve their proof of concept or application level prototyping goals based on real time and real world data or conditions. Unique BEE technologies covered include its' symmetrical Honeycomb Architecture, Full Speed Sting I/O interface, Application Control and Debugging Nectar OS, and the BEEcube Platform Studio software environment. The presentation plans to include BEE technology in action, for real-time imaging manipulation or as a flexible testing platform, an Arbitrary Waveform Generation example.

关键词： Field programmable gate arrays computer architecture Real-time systems USA Councils Abstracts Wireless communication High definition video

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Efficient Handling of Arrays in Dataflow Process Networks

Efficient Handling of Arrays in Dataflow Process Networks

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Daniel Baudisch Jens Brandt Klaus Schneider Embedded Systems Group Department of Computer Science University of Kaiserslautern Germany

ISBN: (纸本)9781467321648

Dataflow process networks (DPN) have been proposed as a programming model for distributed parallel systems that have communication paths with unpredictable latencies. The purely data-driven execution of DPNs does not require a global coordination and therefore allows one to easily map DPNs to many parallel hardware and software architectures with distributed memories. Problems due to shared memory communication like data races do not exist since the communication is done via point-to-point FIFO buffers between the process nodes. On the other hand, this distributed programming model leads to high communication costs if large data structures like arrays have to be communicated between nodes. This paper addresses the reduction of the communication costs due to arrays that are processed by -- and therefore sent between -- DPN nodes. The presented methods are given at a high level of abstraction and do not impose specific constraints on the used target architectures. Our experimental results show clearly the advantage of our approach compared to the standard message passing between the nodes.

关键词： Arrays Computational modeling Writing embedded systems Programming Hardware

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Hybrid simulation for extensible processor cores 12

Hybrid simulation for extensible processor cores

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Design, Automation and Test in Europe conference and Exhibition

作者： Jovana Jovic Sergey Yakoushkin Luis Murillo Juan Eusse Rainer Leupers Gerd Ascheid Institute for Communication Technologies and Embedded Systems RWTH Aachen University Aachen Germany

ISBN: (纸本)9783981080186

Due to their good flexibility-performance trade-off, Application Specific Instruction-set Processors (ASIPs) have been identified as a valuable component in modern embedded systems, especially the extensible ones, achieving good cost-efficiency trade-offs. Since the generation of the described hardware is usually automated to a high extent, in order to deliver an ASIP-based design in due time, developers are limited by the performance of the underlying simulation techniques for software development. On the other hand, the Hybrid Processor simulation technology (HySim), which enables dynamic run-time switching between native and instruction-accurate simulation, has reported high speed-up values for some fixed architectures. This paper presents enhanced HySim technology for extensible cores, based on a layered simulation infrastructure. This technology has shown a speed-up on a per-function basis of two orders of magnitude for a realistic MIMO OFDM benchmark on a multi-core platform with customized Xtensa cores by Tensilica.

关键词： Registers Instruments Switches Computational modeling computer architecture Synchronization embedded systems

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Design and implementation of real time simulator with Modelica

Design and implementation of real time simulator with Modeli...

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IEEE international conference on System Engineering and Technology

作者： M. Hakim Adiprasetya Ary Setijadi Prihatmanto Sekolah Teknik Elektro dan Informatika Institut Teknologi Bandung Indonesia

The usefulness of a simulation is determined by the validity and results of the simulation that can be used by a user to experiment with the system being simulated. In order to to develop a flexible simulator system with a long useful life, an abstraction needs to be introduced in the modeling and validation proses to separate it from the simulation engine itself. The aim is to develop an architecture that can separate the modeling proses of a simulation from the simulation engine that is being used. The language used to model the simulation is Modelica. The Modelica file is converted into the C programming language using tools provided from OpenModelica that is then integrated to the real-time simulator runtime developed in this thesis. This paper discusses the design and implementation of two different simulator architectures. These two architectures are the multi-threaded and non-threaded real-time simulator runtime. The conclusion of the testing and analysis done towards the two architectures is that the non-threaded architecture results in the most valid simulation producing simulation values closest to the real value and is able to fulfill the hard-real time requirements of the simulation.

关键词： Real-time systems Data models Engines Runtime Games Instruction sets computer architecture

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Hardware accelerator for self adaptive augmented reality systems

Hardware accelerator for self adaptive augmented reality sys...

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international conference on High Performance Computing & simulation (HPCS)

作者： Tarek Frikha Nader Benamor Kais Loukil Agnes Ghorbel Mohamed Abid Jean-Philippe Diguet CES-Laboratory National Engineering School of Sfax Sfax SUD University Sfax Tunisia Lab-STICC University Bretagne Sud Lorient France

The emergency of multimedia applications particularly in mobile embedded systems puts new challenges for the design of such systems. The major difficulty is the embedded system's reduced energy and computational resources that must be carefully used to execute complex application often in unpredictable environments. So the system architecture must be energy efficient and flexible enough to adapt resources to application requirements to manage the environment architectures and mobile's constraints. The augmented reality is a very promising 3D embedded multimedia application. It's based on the addition of specific 3D's animations on a video flow. In this paper, we describe our concept of flexible architecture and we give implementation results based on Pixel Shader Accelerator. This is the first step of the project and we compare various hardware and software implementation.

关键词： Hardware computer architecture Software Filling Geometry Extremities Image color analysis

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Acceleration of Monte-Carlo molecular simulations on hybrid computing architectures

Acceleration of Monte-Carlo molecular simulations on hybrid ...

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IEEE international conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： Claus Braun Stefan Holst Hans-Joachim Wunderlich Juan Manuel Castillo Joachim Gross Institute of Computer Architecture and Computer Engineering University of Stuttgart Germany Institute of Thermodynamics and Thermal Process Engineering University of Stuttgart Germany

Markov-Chain Monte-Carlo (MCMC) methods are an important class of simulation techniques, which execute a sequence of simulation steps, where each new step depends on the previous ones. Due to this fundamental dependency, MCMC methods are inherently hard to parallelize on any architecture. The upcoming generations of hybrid CPU/GPGPU architectures with their multi-core CPUs and tightly coupled many-core GPGPUs provide new acceleration opportunities especially for MCMC methods, if the new degrees of freedom are exploited correctly. In this paper, the outcomes of an interdisciplinary collaboration are presented, which focused on the parallel mapping of a MCMC molecular simulation from thermodynamics to hybrid CPU/GPGPU computing systems. While the mapping is designed for upcoming hybrid architectures, the implementation of this approach on an NVIDIA Tesla system already leads to a substantial speedup of more than 87× despite the additional communication overheads.

关键词： Computational modeling computer architecture Monte Carlo methods Kernel Thermodynamics Electric potential Electrostatics

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Scalable Performance Predictions of Distributed Peer-to-Peer Applications

Scalable Performance Predictions of Distributed Peer-to-Peer...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Bogdan Florin Cornea Julien Bourgeois The Tung Nguyen Didier El-Baz DISC FEMTO-ST Institute University of Franche-Comté Montbeliard France CNRS LAAS Université de Toulouse Toulouse France

Recently, a new environment for high performance peer-to-peer distributed computing was proposed. This environment, named P2PDC, addresses stable or volatile systems communicating in a decentralized manner using the self-adaptive protocol P2PSAP. P2PDC is devoted to task parallel applications like numerical simulation problems or optimization problems solved via parallel or distributed iterative algorithms. For distributed applications meant to run with P2PDC, a performance prediction tool named dPerf was proposed. dPerf combines static and dynamic analysis with trace-based simulation to provide scientist with information about the execution of their large scale numerical simulation applications. dPerf addresses real parallel and distributed numerical simulation and optimisation applications written in C, C++ or Fortran for P2PDC. This paper introduces an enhancement of the dPerf tool which provides scalable performance prediction results. Scaling is done with respect to (i) network configuration and (ii) number of peers. Scaling predictions based on network configuration is achieved through trace-based simulation, where various architectures can be studied. Scaling predictions based on the number of peers implies analyzing the communication topology and modifying trace files prior to simulation. We present experimental results obtained for the obstacle problem, a C/P2PDC implementation of the code used in mechanics and finance. Prediction for this application is computed under real conditions, with a reduced slowdown and by providing user with scalable results.

关键词： Peer to peer computing Topology computer architecture Predictive models Scalability Computational modeling Benchmark testing

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modeling of Networked Automation systems for simulation and model checking of time behavior

Modeling of Networked Automation Systems for simulation and ...

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IEEE SSD international Multi-conference on systems, Signals and Devices

作者： Birgit Vogel-Heuser Jens Folmer Georg Frey Liu Liu Holger Hermanns Arnd Hartmanns Chair of Automation and Information Systems Technische Universität München Garching Munich Germany Chair of Automation University of Saarland Saarbruecken Germany Chair for Dependable Systems and Software University of Saarland Saarbruecken Germany

In terms of fulfilling the customers' needs, Networked Automation systems (NAS) have gained increasing significance in various industries, e.g. machine and plant automation over the past years. The advantages of NAS lie in enhanced dependability, flexibility and configurability, thereby overcoming various shortcomings of centralized automation systems. Besides, verification of the time behavior of NAS is still a challenge for engineers. There is a lack in an appropriate modeling notation for automation engineers as well in tool support to estimate or even verify the time behavior. This paper presents a method for modeling real-time requirements and properties of NAS and a concept for its combination with NAS simulation and mechanized verification. This enables the comparison of different architectures regarding their time behavior.

关键词： Automation Unified modeling language Analytical models Stochastic processes Real time systems computer architecture Data models

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