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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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A Class of Backpressure Algorithms for Networks embedded in Hyperbolic Space with Controllable Delay-Throughput Trade-off 12

A Class of Backpressure Algorithms for Networks Embedded in ...

引用

ACM international Workshop on modeling, Analysis and simulation of Wireless and Mobile systems

作者： Eleni Stai John S. Baras Symeon Papavassiliou Institute of Communications and Computer Systems School of Electrical & Computer Engineering National Technical University of Athens Athens Zografou 15780 Greece Institute for Systems Research Department of Electrical & Computer Engineering University of Maryland College Park MD 20742 USA

ISBN: (纸本)9781450316286

Future communications consist of an increasing number of wireless parts, while simultaneously need to support the widespread multimedia applications imposed by social networks. These human-machine systems, driven by both real time social interactions and the challenges of the wireless networks' design, call for efficient and easy to implement, distributed cross-layer algorithms for their operation. Performance metrics such as throughput, delay, trust, energy consumption, need to be improved and optimized aiming at high quality communications. We investigate the coveted throughput-delay trade-off in static wireless multihop networks based on a "computer-aided" design of the backpressure scheduling/routing algorithm for networks embedded in hyperbolic space. Both routing and scheduling exploit the hyperbolic distances to orient the packets to the destination and prioritize the transmissions correspondingly. The proposed design provides us with the freedom of controlling its theoretical throughput; optimality and of counterbalancing its practical performance through simulations, leading to significant improvements of the throughput-delay trade-off.

关键词： Wireless Networks Greedy Embedding Hyperbolic Geometry Delay Throughput Wireless networks Lobachevskian geometry hyperbolic coordinates Throughput BACK PRESSURE tradeoffs Network delay

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Preservation of LTL properties in desynchronized systems

Preservation of LTL properties in desynchronized systems

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ACM and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： Yu Bai Jens Brandt Klaus Schneider Embedded Systems Group Department of Computer Science University of Kaiserslautern Germany

The synchronous programming model is perfect for modeling, simulation, verification and implementation of reactive systems. While this paradigm can be directly implemented as hardware circuits, multithreaded software implementations are typically based on asynchronous threads. For this reason, an efficient multithreaded software implementation of a synchronous program requires a so-called desynchronization that could however potentially violate the already verified properties of the synchronous program. In this paper, we therefore present a theory to check whether properties verified for a synchronous system are preserved by a desynchronization. In particular, we prove a theorem based on directed-flow equivalence that specifies the requirements of delay relations among system variables that a desynchronization has to meet.

关键词： Computational modeling Delay Synchronization Context Integrated circuit modeling embedded systems

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Abstract system-level models for early performance and power exploration

Abstract system-level models for early performance and power...

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Asia and South Pacific Design Automation conference

作者： Andreas Gerstlauer Suhas Chakravarty Manan Kathuria Parisa Razaghi Electrical and Computer Engineering University of Texas Austin USA

With increasing complexity of today's embedded systems, research has focused on developing fast, yet accurate high-level and executable models of complete platforms. These models address the need for hardware/software co-simulation of the entire system at early stages of the design. Traditional models tend to be either slow or inaccurate. In this paper, we present ingredients for a class of abstract, high-level platform models that enable fast yet accurate performance and power simulation of application execution on heterogeneous multi-core/-processor architectures. Models are based on host-compiled simulation of the application code, which is instrumented with timing and power information. Back-annotated source code is further augmented with abstract OS and processor models that are integrated into standard co-simulation backplanes. The efficiency of the modeling platform has been evaluated by applying an industrial-strength benchmark, demonstrating the feasibility and benefits of such models for rapid, early exploration of the power, performance and cost design space. Results show that an accurate Pareto set of solutions can be obtained in a fraction of the time needed with traditional simulation and modeling approaches.

关键词： Timing Computational modeling Accuracy Time domain analysis Time varying systems Multicore processing Kernel

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Statistical extraction and modeling of inductance considering spatial correlation

Statistical extraction and modeling of inductance considerin...

引用

作者： Hao, Zhigang Tan, Sheldon X.-D. Tlelo-Cuautle, E. Relles, Jacob Hu, Chao Yu, Wenjian Cai, Yici Shi, Guoyong Shanghai Jiao Tong University Shanghai 200240 China University of California Riverside CA 92521 United States INAOE Puebla Mexico Tsinghua University Beijing 10084 China

In this paper, we present a novel method for statistical inductance extraction and modeling for interconnects considering process variations. The new method, called statHenry, is based on the collocation-based spectral stochastic method where orthogonal polynomials are used to represent the statistical processes. The coefficients of the partial inductance orthogonal polynomial are computed via the collocation method where a fast multi-dimensional Gaussian quadrature method is applied with sparse grids. To further improve the efficiency of the proposed method, a random variable reduction scheme is used. Given the interconnect wire variation parameters, the resulting method can derive the parameterized closed form of the inductance value. We show that both partial and loop inductance variations can be significant given the width and height variations. This new approach can work with any existing inductance extraction tool to extract the variational partial and loop inductance or impedance. Experimental results show that our method is orders of magnitude faster than the Monte Carlo method for several practical interconnect structures. © 2011 Springer Science+Business Media, LLC.

关键词： Monte Carlo methods

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modeling and design of a Folded Cascode bulk driven OTA

Modeling and design of a Folded Cascode bulk driven OTA

引用

international conference on Design and Technology of Integrated systems in Nanoscale Era (DTIS)

作者： Intissar Toihria Tixier Thierry Laboratory Electronics Telecommunications Computer Engineering School in Chemistry Physics Electronics CPE Lyon Lyon France

Analog circuit design is often based on a large number of simulations which strongly depends on the mastery of CAD tools and competence of the designer. In this context, the automated design of analog architectures becomes a necessity of design to solve the problem of simulation time. More importantly, accelerating the design cycle of the analog block, taking into account many constraints and finally formalizing the experience of analogiciens designers. In this paper we present a method for modeling the performance parameters of analog architectures, this is for the optimization of optimal sizing of transistors constituting the circuit to achieve the desired characteristics. This work is done following a modeling of the functioning of the Operational Amplifier using mathematical formulation software “Maxima”. The formulation is based on the SPICE level 1 model of the MOS transistor. Finally, the elaboration of the model is developed under MATLAB. The proposed method is presented and applied to the modeling and design of a Folded Cascode bulk driven OTA using a 0.35μm CMOS technology. simulations with Cadence Spectrum are presented and compared with manual calculations and also to numerical calculations that have shown the effectiveness of the proposed methodology. Then, we determine the optimal parameters of the operational amplifier, which accord, maximum, to the desired specifications.

关键词： Transistors Semiconductor device modeling Mathematical model Solid modeling Integrated circuit modeling Mirrors Adaptation models

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Managing Communication Latency-Hiding at Runtime for Parallel Programming Languages and Libraries

Managing Communication Latency-Hiding at Runtime for Paralle...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Mads Ruben Burgdorff Kristensen Brian Vinter Niels Bohr Institute University of Copenhagen Denmark

This work introduces a runtime model for managing communication with support for latency-hiding. The model enables non-computer science researchers to exploit communication latency-hiding techniques seamlessly. For compiled languages, it is often possible to create efficient schedules for communication, but this is not the case for interpreted languages. By maintaining data dependencies between scheduled operations, it is possible to aggressively initiate communication and lazily evaluate tasks to allow maximal time for the communication to finish before entering a wait state. We implement a heuristic of this model in DistNumPy, an auto-parallelizing version of numerical Python that allows sequential NumPy programs to run on distributed memory architectures. Furthermore, we present performance comparisons for six benchmarks with and without automatic latency-hiding. The results shows that our model reduces the time spent on waiting for communication as much as 27 times, from a maximum of 54% to only 2% of the total execution time, in a stencil application.

关键词： Arrays Runtime Computational modeling computer languages Parallel processing Libraries Schedules

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A Basic Analysis of the Application on Linux and μC/O Dual-core embedded Operating System in Engineering Practice

A Basic Analysis of the Application on Linux and μC/O Dual-...

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The 2nd international conference on computer-Aided Design, Manufacturing, modeling and simulation(CDMMS 2012)

作者： Li lin Shan Chan-ji Luo jun Xu nan Department of Physics Zhaotong University Department of Foreign Languages Zhaotong University

ISBN: (纸本)9783037855409

With the development of linux and μC/O dual-core embedded operating system,its research areas have been broadened wider and *** paper aims to illustrate its importance in engineering practice on the basis of its application in the technological process of injection molding machines and numerical control machines to arrive at its natural conclusion that dual-core system has a brighter and wider prospect by using Linux and μC /OS to solve the problems of Linux because it is more and more widely applied in engineering,mechanical control systems and many other fields such as mobile communications as well as digitalized network,and now is becoming more and more demanded with the rapid development of scientific technology.

关键词： Linux,ΜC/OS,Operating System,Injection Molding Machines,Numerical Control Machines,Mechanical Control

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Admission Control and Channel Allocation of Multi-item Requests for Real-Time Data Broadcast

Admission Control and Channel Allocation of Multi-item Reque...

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IEEE international conference on embedded and Real-Time Computing systems and Applications (RTCSA)

作者： Jingsong Lv Victor C.S. Lee Minming Li Enhong Chen School of Computer Science and Technology University of Science and Technology Hefei Anhui China USTC-CityU Joint Advanced Research Institute Suzhou China Department of Computer Science City University of Hong Kong Hong Kong China

Owing to its potential to satisfy all outstanding requests for the same data item with a single response, on-demand data broadcast becomes a widely accepted approach to dynamic and scalable wireless information dissemination. In some emerging applications, such as road traffic navigation system, users prefer to request multiple dependent data items at a time. In addition, requests usually have deadline constraints for real-time applications. However, in existing works, clients will not know that their requests cannot be satisfied until the deadlines expire. In this paper, admission control is introduced to data broadcast systems such that clients can be informed in advance in the case that their requests have no hope to be satisfied so that earlier remedial actions can be taken. Furthermore, a matching based allocation scheme is proposed to maximize data sharing among requests in multi-channel architectures. simulation results show that our proposed algorithms have better performance and quality of service (QoS) than traditional algorithms.

关键词： Admission control Resource management Channel allocation Bandwidth Real time systems Servers

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Ice simulation Using GPGPU

Ice Simulation Using GPGPU

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Shadi Alawneh Dennis Peters Electrical and Computer Engineering Faculty of Engineering and Applied Science Memorial University Saint John's NEW Canada

simulation of the behaviour of a ship operating in pack ice is a computationally intensive process to which General Purpose Computing on Graphical Processing Units (GPGPU) can be applied. In this paper we present an efficient parallel implementation of such a simulator developed using the NVIDIA Compute Unified Device Architecture (CUDA). We have conducted an experiment to measure the relative performance of the parallel and serial versions of the simulator by running both versions on several different ice fields for several iterations to compare the performance. Our results show speed up of up to 77 times, reducing simulation time for a small ice field from over 88 minutes to about 68 seconds.

关键词： Ice Graphics processing unit Kernel Computational modeling Data models Instruction sets Marine vehicles

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Mapping the PRAM model onto the Intel SCC many-core processor

Mapping the PRAM model onto the Intel SCC many-core processo...

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international conference on High Performance Computing & simulation (HPCS)

作者： Carsten Clauss Stefan Lankes Thomas Bemmerl Chair for Operation Systems RWTH Aachen University Aachen Germany

The Parallel Random Access Machine (PRAM) model describes an abstract register machine for analyzing the complexity and scalability of parallel algorithms. Unfortunately, it is not possible to implement this model directly in hardware but it is at least possible to emulate this abstract model on more realistic parallel machines. Moreover, the recent evolution of processor architectures towards a forthcoming many-core era seems to indicate that PRAM-derived hardware architectures may even become important in the near future. The Single-chip Cloud computer (SCC) is a recent example for an experimental many-core processor. By means of this processor, researchers have the opportunity to investigate the requirements of tomorrow's software design and programming models. In this paper, we discuss if and how the PRAM model could be mapped onto the SCC by exploiting its many-core related hardware features.

关键词： Phase change random access memory Computational modeling Synchronization Emulation Hardware Radiation detectors Parallel algorithms

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