embeddedsystems and their design trajectories are becoming increasingly complex, and there is a growing demand for performance, reliability, energy efficiency and low cost. To cope with these challenges, decision mak...
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At the nanoscale domain, the simulation, design, and optimization time of the circuits have increased significantly due to high-integration density, increasing technology constraints, and complex device models. This n...
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At the nanoscale domain, the simulation, design, and optimization time of the circuits have increased significantly due to high-integration density, increasing technology constraints, and complex device models. This necessitates fast design space exploration techniques to meet the shorter time to market driven by consumer electronics. This paper presents non-polynomial metamodels (surrogate models) using neural networks to reduce the design optimization time of complex nano-CMOS circuit with no sacrifice on accuracy. The physical design aware neural networks are trained and used as metamodels to predict frequency, locking time, and power of a PLL circuit. Different architectures for neural networks are compared with traditional polynomial functions that have been generated for the same circuit characteristics. Thorough experimental results show that only 100 sample points are sufficient for neural networks to predict the output of circuits with 21 design parameters within 3% accuracy, which improves the accuracy by 56% over polynomial metamodels. The generated metamodels are used to perform optimization of the PLL using a bee colony algorithm. It is observed that the non-polynomial (using neural networks) metamodels achieve more accurate results than polynomial metamodels in shorter optimization time.
Grid-based visualization system can aggregate and share geographically distributed data sources, analysis facilities and visualization systems, and also offer transparent data access capabilities. We develop a web-bas...
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Grid-based visualization system can aggregate and share geographically distributed data sources, analysis facilities and visualization systems, and also offer transparent data access capabilities. We develop a web-based visualization system on the grid. The system consists of three components: the WebSheet, the web server and the visualization server. The front-end of the system provides the users with the web-based access interface built on JSP, and the embedded VisPortal provides grid access portal for the users. The middle part of the system is the web server which aims to manipulate, dispatch, utilize grid resources and mediate the interaction between the user and the grid. The back-end of the system is the visualization server and we build one based on Vis5D as a grid, which delivers grid-based visualization services of 5-D gridded datasets generated from the numerical weather models.
Synthesizing aliasing-free space compactor for built-in self-testing of very large scale integration circuits and systems is of great importance, especially because of the design paradigm shift in recent years from sy...
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Synthesizing aliasing-free space compactor for built-in self-testing of very large scale integration circuits and systems is of great importance, especially because of the design paradigm shift in recent years from system-on-board to system-on-chip. This paper investigates and provides additional results on a recently developed approach to designing aliasing-free space compaction hardware targeting particularly embedded cores-based system-on-chips for single stuck-line faults, extending well-known concept from conventional switching theory, viz. that of compatibility relation as used in the minimization of incomplete sequential machines. For a pair of response outputs of the circuit under test, the method introduces the notion of fault detection compatibility and conditional fault detection compatibility (conditional upon some other response output pair being simultaneously fault detection compatible) with respect to two-input XOR/XNOR logic. The process is illustrated with design details of space compactors for the international Symposium on Circuits and systems (ISCAS 85) combinational (and ISCAS 89 full-scan sequential) benchmark circuits using simulation programs ATALANTA and FSIM, attesting to the importance of the technique from the viewpoint of simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, thereby making it an appropriate choice in commercial design environments.
This paper introduces an Y-chart methodology for performance estimation based on high level models for both application and architecture. As embedded devices are more and more complex, the choice of the best suited ar...
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embedded multimedia and wireless applications require a model-based design approach in order to satisfy stringent quality and cost constraints. The Model-of-Computation (MoC) should appropriately capture system dynami...
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The increasing software content in current and future embeddedsystems has forced academia and industry to devise new programming methodologies. Only with new methods, software productivity will keep the pace with use...
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Virtual prototypes are widely employed in today's development of embedded hardware and software. To model and simulate the VPs, SystemC has been adopted as a standard language tool. With SystemC, hardware modules ...
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Software synthesis from an initial specification model becomes a critical issue in the ESL design methodology as hardware platforms are often reused and more processors are involved in the target platform. Since embed...
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We consider software transactional memory (STM) concurrency control in multicore embedded real-time software. We design an Earliest-Deadline-First (EDF) contention manager (CM) to augment STM's obstruction-free pr...
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