检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

2,723 篇 会议
57 册 图书
54 篇 期刊文献

馆藏范围

2,834 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,289 篇 工学
- 1,120 篇 计算机科学与技术...
- 591 篇 软件工程
- 287 篇 电气工程
- 159 篇 电子科学与技术（可...
- 150 篇 控制科学与工程
- 137 篇 信息与通信工程
- 50 篇 机械工程
- 44 篇 动力工程及工程热...
- 19 篇 仪器科学与技术
- 19 篇 建筑学
- 18 篇 材料科学与工程（可...
- 18 篇 安全科学与工程
- 17 篇 土木工程
- 16 篇 生物医学工程（可授...
- 14 篇 交通运输工程
- 14 篇 航空宇航科学与技...
- 13 篇 力学（可授工学、理...
- 12 篇 生物工程
- 11 篇 光学工程
275 篇 理学
- 173 篇 数学
- 81 篇 系统科学
- 38 篇 物理学
- 33 篇 统计学（可授理学、...
- 14 篇 化学
- 14 篇 生物学
142 篇 管理学
- 119 篇 管理科学与工程(可...
- 52 篇 工商管理
- 30 篇 图书情报与档案管...
21 篇 经济学
- 21 篇 应用经济学
20 篇 法学
- 20 篇 社会学
11 篇 医学
6 篇 教育学
5 篇 农学
3 篇 军事学
1 篇 文学
1 篇 艺术学

主题

763 篇 computational mo...
616 篇 computer archite...
361 篇 hardware
222 篇 embedded systems
144 篇 analytical model...
142 篇 embedded system
134 篇 computer simulat...
128 篇 application soft...
123 篇 mathematical mod...
117 篇 field programmab...
112 篇 real time system...
103 篇 program processo...
91 篇 embedded computi...
89 篇 kernel
84 篇 software
83 篇 computer science
82 篇 parallel process...
81 篇 registers
73 篇 control systems
72 篇 algorithm design...

机构

10 篇 school of electr...
9 篇 rhein westfal th...
8 篇 institute for co...
8 篇 center for embed...
7 篇 center for embed...
7 篇 department of co...
6 篇 eindhoven univer...
6 篇 computer systems...
6 篇 natl tech univ a...
6 篇 computer systems...
6 篇 institute for co...
6 篇 fraunhofer iese ...
5 篇 school of automa...
5 篇 school of electr...
5 篇 university of za...
5 篇 embedded systems...
5 篇 university of te...
5 篇 national cims en...
5 篇 the university o...
5 篇 eindhoven univer...

作者

19 篇 leupers rainer
16 篇 soudris dimitrio...
16 篇 ascheid gerd
14 篇 dimitrios soudri...
13 篇 rainer leupers
12 篇 gerd ascheid
12 篇 takala jarmo
12 篇 pimentel andy d.
11 篇 blume holger
11 篇 holger blume
10 篇 andy d. pimentel
10 篇 jung matthias
9 篇 mohamed abid
9 篇 fornaciari willi...
9 篇 pnevmatikatos di...
9 篇 kostas siozios
9 篇 christian haubel...
9 篇 andreas gerstlau...
9 篇 wehn norbert
8 篇 f. fummi

语言

2,817 篇 英文
9 篇 其他
9 篇 中文

检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

共 2834 条记录，以下是1271-1280 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Fully-automatic derivation of exact program-flow constraints for a tighter worst-case execution-time analysis

Fully-automatic derivation of exact program-flow constraints...

引用

2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Marref, Amine Department of Computer Science Umm Al-Qura University Makkah Saudi Arabia

ISBN: (纸本)9781457708008

Obtaining tight worst-case execution-time (WCET) estimations of real-time tasks is crucial since overly-pessimistic estimations are deemed impractical. One way of making WCET estimations tighter is to incorporate more program-flow information e.g., context-sensitive loop bounds, infeasible-path and same-path information, etc. In this paper we present and evaluate a completely automatic analysis that dynamically derives program-flow information to use in WCET analysis. Flow information is derived by a combination of test-data generation and parsing of program-execution traces to obtain flow-fact hypotheses which are then fed to a model checker to establish their correctness. Experimental evaluation shows that our method help achieve considerable tightness in WCET estimations at a manageable cost. © 2011 IEEE.

关键词： Model checking

来源：评论

学校读者我要写书评

暂无评论

Calibration and validation of software performance models for pedestrian detection systems

Calibration and validation of software performance models fo...

引用

2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Kiesel, Rainer Streubühr, Martin Haubelt, Christian Löhlein, Otto Teich, Jürgen Department Environment Perception GR/PAP Daimler AG Ulm Germany Hardware/Software Co-Design Department of Computer Science University of Erlangen Nuremberg Germany

ISBN: (纸本)9781457708008

In recent years, road vehicles have seen a tremendous increase on driver assistance systems like lane departure warning, traffic sign recognition, or pedestrian detection. The development of efficient and cost-effective electronic control units that meet the necessary real-time performance for these systems is a complex challenge. Often, Electronic System-Level design tackles the challenge by simulation-based performance evaluation, although, the quality of system-level performance simulation approaches is not yet evaluated in detail. In this paper, we present the calibration and validation of a system-level performance simulation model. For evaluation, an automotive pedestrian detection algorithm is studied. Especially the varying number of pedestrians has a significant impact to the system performance and makes the prediction of execution time difficult. As test cases we used typical sequences and corner cases recorded by an experimental car. Our evaluation results indicate that prediction of execution times with an average error of 3.1% and a maximum error of 7.9% can be achieved. Thereby, simulated and measured execution times of a software implementation are compared. © 2011 IEEE.

关键词： Calibration

来源：评论

学校读者我要写书评

暂无评论

Multicore Communications API (MCAPI) implementation on an FPGA multiprocessor

Multicore Communications API (MCAPI) implementation on an FP...

引用

2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Matilainen, Lauri Salminen, Erno Hämäläinen, Timo D. Hämäläinen, Marko Tampere University of Technology Department of Computer Systems P.O. Box 553 33101 Tampere Finland

ISBN: (纸本)9781457708008

The design and implementation of an application programming interface (API) is a trade-off between abstraction it provides and overheads it causes. This paper presents an implementation of Multicore Communications API (MCAPI) on a heterogeneous platform consisting of FPGA-based multiprocessor system-on-chip (MPSoC) connected via PCIe to an external CPU board. The purpose is to provide a unified programming API to different processor and OS types as well as hardware IP-blocks. MCAPI is shown to meet these requirements. We show the MCAPI transport implementation on three processors and two buses, measure the overhead cost, and analyze the effort required to port an application from a PC to the MPSoC. The measured library memory footprint is less than 25KB and the roundtrip communication latency is diminishing low only few dozen clock cycles compared to non-MCAPI implementation. © 2011 IEEE.

关键词： Field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Scalable multi-core simulation using parallel dynamic binary translation

Scalable multi-core simulation using parallel dynamic binary...

引用

2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Almer, Oscar Böhm, Igor Von Koch, Tobias Edler Franke, Björn Kyle, Stephen Seeker, Volker Thompson, Christopher Topham, Nigel Institute for Computing Systems Architecture University of Edinburgh United Kingdom Software Engineering for Embedded Systems Group Technical University Berlin Germany

ISBN: (纸本)9781457708008

In recent years multi-core processors have seen broad adoption in application domains ranging from embedded systems through general-purpose computing to large-scale data centres. simulation technology for multi-core systems, however, lags behind and does not provide the simulation speed required to effectively support design space exploration and parallel software development. While state-of-the-art instruction set simulators (Iss) for single-core machines reach or exceed the performance levels of speed-optimised silicon implementations of embedded processors, the same does not hold for multi-core simulators where large performance penalties are to be paid. In this paper we develop a fast and scalable simulation methodology for multi-core platforms based on parallel and just-in-time (Jit) dynamic binary translation (Dbt). Our approach can model large-scale multi-core configurations, does not rely on prior profiling, instrumentation, or compilation, and works for all binaries targeting a state-of-the-art embedded multi-core platform implementing the ARCompact instruction set architecture (Isa). We have evaluated our parallel simulation methodology against the industry standard Splash-2 and Eembc MultiBench benchmarks and demonstrate simulation speeds up to 25,307 Mips on a 32-core 86 host machine for as many as 2048 target processors whilst exhibiting minimal and near constant overhead. © 2011 IEEE.

关键词： embedded systems

来源：评论

学校读者我要写书评

暂无评论

FPGA based application specific processing for sensor nodes

FPGA based application specific processing for sensor nodes

引用

2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Nyländen, Teemu Janhunen, Janne Hannuksela, Jari Silvén, Olli Computer Science and Engineering Laboratory University of Oulu Finland Centre for Wireless Communications University of Oulu Finland

ISBN: (纸本)9781457708008

Energy efficient sensor nodes are among the rapidly expanding applications for embedded systems technology. Typically, the processing resources in sensor nodes are based on programmable micro-controllers and digital signal processors, and the same processing architecture is used regardless of the actual task of the node. This regularly results in at least an order of magnitude over-provisioning of resources, and in higher power consumption than would be needed by tightly application specific processing solutions. Currently, experiments show that Flash FPGA technology enables implementing precisely provisioned processing for sensor nodes with energy efficiency that rivals off-the-shelf processor solutions. The expected competitiveness originates from savings in silicon real-estate, and lowered software overheads, as inherently parallel tasks can be offloaded to dedicated hardware accelerators on the same die with a microcontroller unit, and radio baseband. The results pave the way for a novel type of self-powered sensor nodes whose processing resources are configured according to their tasks. © 2011 IEEE.

关键词： Sensor nodes

来源：评论

学校读者我要写书评

暂无评论

A hardware accelerated configurable ASIP architecture for embedded real-time video-based driver assistance applications

A hardware accelerated configurable ASIP architecture for em...

引用

2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Schewior, Gregor Flatt, Holger Dolar, Carsten Banz, Christian Blume, Holger Leibniz Universität Hannover Institute of Microelectronic Systems Appelstr. 4 30167 Hannover Germany

ISBN: (纸本)9781457708008

In this paper, a flexible HW architecture for video-based driver assistance applications is presented. It comprises a customizable and extensible processor template and several task-specific HW accelerators. The proposed heterogeneous architecture allows utilization of the programmable processor core for control and low data rate tasks. For the acceleration of computationally intensive tasks of the application, special functional units and custom instructions can be added to the processor template to form an application specific instruction set processor (ASIP). Moreover, dedicated HW accelerators can be attached to the ASIP. To compare the diverse design options, a shape detection application for traffic sign detection is utilized as case study. It is shown that single tasks of a pure software implementation can be significantly accelerated by usage of special functional units by a factor of up to 35 and by usage of HW accelerators of up to 243. The proposed architecture has been mapped onto an FPGA and it could be shown that a realtime capable system can be realized. © 2011 IEEE.

关键词： Automobile drivers

来源：评论

学校读者我要写书评

暂无评论

ADL-based specification of implementation styles for functional simulators

ADL-based specification of implementation styles for functio...

引用

2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Penry, David A. Cahill, Kurtis D. Department of Electrical and Computer Engineering Brigham Young University Provo UT United States

ISBN: (纸本)9781457708008

Functional simulators find widespread use as sub-systems within microarchitectural simulators. The speed of functional simulators is strongly influenced by the implementation style of the functional simulator, e.g. interpreted vs. binary-translated simulation. Speed is also strongly influenced by the level of detail of the interface the functional simulator presents to the rest of the timing simulator. This level of detail may change during design space exploration, requiring corresponding changes to the interface and the simulator. However, for many implementation styles, changing the interface is difficult. As a result, architects may choose either implementation styles which are more malleable or interfaces with more detail than is necessary. In either case, simulation speed is traded for simulator design time. We show that this tradeoff is unnecessary if an orthogonal-specification design principle is practiced: specify how a simulator is to be implemented separately from what it is implementing and then synthesize a simulator from the combined specifications. We show that the use of an Architectural Description Language (ADL) with constructs for implementation style specification makes it possible to synthesize interfaces with different implementation styles with reasonable effort. © 2011 IEEE.

关键词： Simulators

来源：评论

学校读者我要写书评

暂无评论

Parametrized hardware architectures for the lucas primality test

Parametrized hardware architectures for the lucas primality ...

引用

2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Le Masle, Adrien Luk, Wayne Moritz, Csaba Andras Department of Computing Imperial College London United Kingdom BlueRISC Inc. Amherst MA United States

ISBN: (纸本)9781457708008

We present our parametric hardware architecture of the NIST approved Lucas probabilistic primality test. To our knowledge, our work is the first hardware architecture for the Lucas test. Our main contributions are a hardware architecture for calculating the Jacobi symbol based on the binary Jacobi algorithm, a pipelined modular add-shift module for calculating the Lucas sequences, methods for dependence analysis and for scheduling of the Lucas sequences computation. Our architecture implemented on a Virtex-5 FPGA is 30% slower but 3 times more energy efficient than the software version running on a Intel Xeon W3505. Our fastest 45 nm ASIC implementation is 3.6 times faster and 400 times more energy efficient than the optimised software implementation in comparable technology. The performance scaling of our architecture is much better than linear in area. Different speed/area/energy trade-offs are available through parametrization. The cell count and the power consumption of our ASIC implementations make them suitable for integration into an embedded system whereas our FPGA implementation would more likely benefit server applications. © 2011 IEEE.

关键词： Field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

High level quantitative hardware prediction modeling using statistical methods

High level quantitative hardware prediction modeling using s...

引用

2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Meeuws, Roel Galuzzi, Carlo Bertels, Koen Computer Engineering Lab Delft University of Technology Netherlands

ISBN: (纸本)9781457708008

With the increasing proliferation of heterogeneous and reconfigurable computing, it has become essential to have efficient prediction models to drive early HW-SW partitioning and co-design. In this paper, we present a high level quantitative prediction modeling approach that accurately models the relation between hardware and software metrics, based on several statistical techniques. The proposed approach generates models that predict hardware performance indicators for reconfigurable components, such as the number of slices, the number of flip-flops, and the number of wires. It utilizes automatic model selection, artificial neural networks, (logistic) regression, and data transformations. These models take a high-level language description as input, enabling hardware prediction in the early design stages. We calibrate the models for two sets of tools targeting Xilinx and Altera FPGAs, where we report, for example, and error of 14% for the number of multipliers in case of Xilinx and an error of only 18% for the number of wires in case of Altera. To provide a realistic evaluation, we validate the approach using 181 kernels, contrary to the majority of the existing techniques, which use libraries of tens of kernels at most. © 2011 IEEE.

关键词： Forecasting

来源：评论

学校读者我要写书评

暂无评论

Vector processor customization for FFT

Vector processor customization for FFT

引用

2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Spinean, Bogdan Kuzmanov, Georgi Gaydadjiev, Georgi Computer Engineering Laboratory Faculty EEMCS Delft University of Technology Netherlands

ISBN: (纸本)9781457708008

Processors and memory systems suffer from a growing performance gap between them. Each technology generation increases the on-chip performance capabilities however, memory bandwidth increases at a much slower pace. Therefore, overall performance improvements are constrained by the available memory bandwidth. In this paper, we address the memory bandwidth problem of vector processors by introducing hardware customizations which drastically reduce the memory transfers required by the FFT computation. We show that an FFT transform of length equal to the machine size Z can be performed using only O(Z) memory accesses, hence we reduce the memory bandwidth requirement by an order of O(log(Z)) compared to a conventional vector machine. We achieve bandwidth reduction by extending a classic IBM S/370 vector architecture for better register re-use. Our hardware extension completely eliminates the input bit reversal phase of the Cooley-Tukey FFT algorithm. Synthesis results suggest that our extension does not impact the machine cycle time and has a small hardware area overhead of the vector register file of under 4.5% while potentially improving vector performance by a factor of 7.5 for Z = 256. © 2011 IEEE.

关键词： Fast Fourier transforms

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共284页 << < 124 125 126 127 128 129 130 131 132 133 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：