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Task-based parallel H.264 video encoding for explicit communication architectures

Task-based parallel H.264 video encoding for explicit commun...

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2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Alvanos, Michail Tzenakis, George Nikolopoulos, Dimitrios S. Bilas, Angelos 100 N. Plastira Av. Vassilika Vouton Heraklion GR-70013 Greece Department of Computer Science University of Crete P.O.Box 2208 Heraklion GR-71409 Greece

ISBN: (纸本)9781457708008

Future multi-core processors will necessitate exploitation of fine-grain, architecture-independent parallelism from applications to utilize many cores with relatively small local memories. We use c264, an end-to-end H.264 video encoder for the Cell processor based on x264, to show that exploiting fine-grain parallelism remains challenging and requires significant advancement in runtime support. Our implementation of c264 achieves speedup between 4.7× and 8.6× on six synergistic processing elements (SPEs), compared to the serial version running on the power processing element (PPE). We find that the programming effort associated with efficient parallelization of c264 at fine granularity is highly non-trivial. Hand optimizations may improve performance significantly but are limited eventually by the code restructuring they require. We assess the complexity of exploiting fine-grain parallelism in realistic applications, by identifying optimizations of c264 and the effort they require. © 2011 IEEE.x.

关键词： Video signal processing

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High throughput and scalable architecture for unified transform coding in embedded H.264/AVC video coding systems

High throughput and scalable architecture for unified transf...

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2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Dias, Tiago Lopez, Sebastian Roma, Nuno Sousa, Leonel INESC-ID Lisbon Rua Alves Redol 9 1000-029 Lisbon Portugal ISELPI Lisbon Rua Alves Redol 9 1000-029 Lisbon Portugal ISTTU Lisbon Rua Alves Redol 9 1000-029 Lisbon Portugal IUMAULPGC Rua Alves Redol9 1000-029 Lisbon Portugal

ISBN: (纸本)9781457708008

An innovative high throughput and scalable multi-transform architecture for H.264/AVC is presented in this paper. This structure can be used as a hardware accelerator in modern embedded systems to efficiently compute the 4×4 forward/inverse integer DCT, as well as the 2-D 4×4 / 2×2 Hadamard transforms. Moreover, its highly flexible design and hardware efficiency allows it to be easily scaled in terms of performance and hardware cost to meet the specific requirements of any given video coding application. Experimental results obtained using a Xilinx Virtex-4 FPGA demonstrate the superior performance and hardware efficiency levels provided by the proposed structure, which presents a throughput per unit of area at least 1.8× higher than other similar recently published designs. Furthermore, such results also showed that this architecture can compute, in realtime, all the above mentioned H.264/AVC transforms for video sequences with resolutions up to UHDV. © 2011 IEEE.

关键词： Field programmable gate arrays (FPGA)

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A Power-Aware Online Scheduling Algorithm for Streaming Applications in embedded MPSoC

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20th international Workshop on Power and Timing modeling, Optimization and simulation

作者： Sassolas, Tanguy Ventroux, Nicolas Boudouani, Nassima Blanc, Guillaume CEA LIST Embedded Comp Lab F-91191 Gif Sur Yvette France

ISBN: (纸本)9783642177514

As application complexity grows, embedded systems move to multiprocessor architectures to cope with the computation needs. The issue for multiprocessor architectures is to optimize the processing resources usage and power consumption to reach a higher energy efficiency. These optimizations are handled by scheduling techniques. To tackle this issue we propose a global online scheduling algorithm for streaming applications. It takes into account data dependencies between pipeline tasks to optimize processor usage and reduce power consumption through the use of DPM and DVFS modes. An implementation of the algorithm on a virtual platform, executing a WCDMA application, demonstrates up to 45% power consumption gain while guaranteeing regular data throughput.

关键词： scheduling low-power multiprocessor streaming applications

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A queueing theoretic approach for performance evaluation of low-power multi-core embedded systems

A queueing theoretic approach for performance evaluation of ...

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29th IEEE international conference on computer Design 2011, ICCD 2011

作者： Munir, Arslan Gordon-Ross, Ann Ranka, Sanjay Department of Electrical and Computer Engineering University of Florida Gainesville FL United States Department of Computer and Information Science and Engineering University of Florida Gainesville FL United States

ISBN: (纸本)9781457719523

With Moore's law supplying billions of transistors on-chip, embedded systems are undergoing a transition from single-core to multi-core to exploit this high transistor density for high performance. However, the optimal layout of these multiple cores along with the memory subsystem (caches and main memory) to satisfy power, area, and often stringent real-time constraints is a challenging design endeavor. The short time-to-market constraint of embedded systems exacerbates this design challenge and necessitates the architectural modeling of embedded systems to reduce the time-to-market by expediting target applications to device/architecture mapping. In this paper, we present a queueing theoretic approach for modeling multi-core embedded systems that provides a quick and inexpensive performance evaluation both in terms of time and resources as compared to the development of multi-core simulators and running benchmarks on these simulators. We also calculate chip area and power consumption for different multi-core embedded architectures with a varying number of processor cores and cache configurations to provide a comparative analysis of multicore embedded architectures in terms of performance, area, and power consumption. Our performance and power results indicate that multi-core embedded system architectures that leverage shared last-level caches (LLCs) provide the best LLC performance per watt but may introduce main memory response time and throughput bottlenecks for high cache miss rates, whereas architectures leveraging a hybrid of private and shared LLCs alleviate main memory bottlenecks at the expense of reduced performance per watt. © 2011 IEEE.

关键词： Queueing theory

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Functional unit sharing between stacked processors in 3D integrated systems

Functional unit sharing between stacked processors in 3D int...

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2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Borodin, Demid Siauw, Winston Dan Cotofana, Sorin Computer Engineering Laboratory Faculty of Electrical Engineering Mathematics and Computer Science Delft University of Technology Mekelweg 4 2628 CD Delft Netherlands

ISBN: (纸本)9781457708008

The emerging Through Silicon Via (TSV) based 3D integration technology provides the means to stack two or more dies, enabling a low-latency interface between them. Apart of the immediate advantages of such an approach, e.g., short wires, it also opens research avenues for 3D organizations of computation platforms. In this line of reasoning we propose in this paper to share resources between stacked processors while focusing on Functional Units (FUs) inter-die sharing. The purpose of FU sharing is two fold: (i) it enables inexpensive fault tolerance by allowing, when possible, redundant instruction execution on idle FUs of processors located on other stack dies;and (ii) it can result in performance improvements by remotely executing instructions on idle FUs located on other dies in the 3D stack, when more instructions than locally available FUs are issuable. We evaluated the potential implications of our proposal on a 3D system built with two stacked processors (dies). In this case only a limited error detection capability is enabled and the experimental results indicate that our scheme covers on average 46% of the executed instructions. When performance improvement is targeted an average speedup of 6.9% can be achieved for the applications running on the considered two die stack. © 2011 IEEE.

关键词： Dies

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Smart cache: A self adaptive cache architecture for energy efficiency

Smart cache: A self adaptive cache architecture for energy e...

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2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Sundararajan, Karthik T. Jones, Timothy M. Topham, Nigel School of Informatics University of Edinburgh United Kingdom Computer Laboratory University of Cambridge United Kingdom

ISBN: (纸本)9781457708008

The demand for low-power embedded systems requires designers to tune processor parameters to avoid excessive energy wastage. Tuning on a per-application or per-application-phase basis allows a greater saving in energy consumption without a noticeable degradation in performance. On-chip caches often consume a significant fraction of the total energy budget and are therefore prime candidates for adaptation. Fixed-configuration caches must be designed to deliver low average memory access times across a wide range of potential applications. However, this can lead to excessive energy consumption for applications that do not require the full capacity or associativity of the cache at all times. Furthermore, in systems where the clock period is constrained by the access times of level-1 caches, the clock frequency for all applications is effectively limited by the cache requirements of the most demanding phase within the most demanding application. This results in both performance and energy efficiency that represents the lowest common denominator across the applications. In this paper we present a Set and way Management cache Architecture for Run-Time reconfiguration (Smart cache), a cache architecture that allows reconfiguration in both its size and associativity. Results show the energy-delay of the Smart cache is on average 14% better than state-of-the-art cache reconfiguration architectures. We then leverage the flexibility provided by our cache to dynamically reconfigure the hierarchy as a program runs. We develop a decision tree based machine learning model to control the adaptation and automatically reconfigure the cache to the best configuration. Results show an average reduction in energy-delay product of 17% in the data cache (just 1% away from an oracle result) and 34% in the level-2 cache (just 5% away from an oracle), with an overall performance degradation of less than 2% compared with a baseline statically-configured cache. © 2011 IEEE.

关键词： Energy efficiency

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Adaptive resource allocation for streaming applications

Adaptive resource allocation for streaming applications

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2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Ter Braak, Timon D. Toersche, Hermen A. Kokkeler, André B.J. Smit, Gerard J.M. Computer Architecture for Embedded Systems Group Department of Electrical Engineering Mathematics and Computer Science University of Twente P.O. Box 217 7500 AE Enschede Netherlands

ISBN: (纸本)9781457708008

Streaming applications often have latency and throughput requirements due to timing critical signal processing, or the time critical interaction with their environment. Mapping such applications to a multi-core architecture is commonly done at design-time to be able to analyze the complex design-space. However, such design-flows cannot deal with a dynamic platform or a dynamic set of applications. Hardware faults and resources claimed by other applications may render the assumed available resources inaccessible. To avoid the assumptions posed on the state of the platform by a fixed resource allocation, applications should be designed with location transparency in mind. Applications must be analyzed at design-time to determine the required resource budget, independent of which specific resources will be allocated. Sufficient performance can be guaranteed when such applications are mapped onto an architecture in which each resource is arbitrated using a budget scheduler. Within the Cutting edge Reconfigurable ICs for Stream Processing (CRISP) project, a many-core platform is developed that adheres to these requirements. Using the configuration features of the platform, the system is able to control at run-time what resources are being used by the applications. This paper shows that run-time resource allocation can effectively adapt to the available set of resources, providing partial distribution transparency to the user. As an example, a GNSS receiver is mapped to the platform containing faulty hardware components. A few resources remain critical, but in most cases the faulty components can be circumvented, such that adequate resources can be allocated to the application at run-time. © 2011 IEEE.

关键词： Budget control

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On-chip dynamic programming networks using 3D-TSV integration

On-chip dynamic programming networks using 3D-TSV integratio...

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2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Al-Dujaily, Ra'Ed Mak, Terrence Zhou, Kuan Lam, Kai-Pui Meng, Yicong Yakovlev, Alex Poon, Chi-Sang School of Electrical Electronic and Computer Engineering Newcastle University United Kingdom Department of Electrical and Electronic Engineering New Hampshire University United States Department of Systems Engineering Chinese University of Hong Kong Hong Kong Hong Kong Harvard-MIT Health Sciences and Technology Massachusetts Institute of Technology United States

ISBN: (纸本)9781457708008

Recent technological advances in three-dimensional (3D) semiconductor fabrication have provided a promising platform for realizing densely interconnected multicore, multiprocessor, and networks-on-chip (NoC) based systems. As the on-chip complexity grows significantly with the number of computational, control, and communication units, design considerations and the provision for efficient run-time resources management in large-scale system becomes critical. We have developed an on-chip distributed dynamic-programming (DP) network [3] [5] for a range of applications including optimal paths planning [6], dynamic routing [5] and deadlock detection [2]. This paper presents a design of DP-network, implemented in a fully stacked 3-layer three-dimensional (3D) through-silicon via (TSV) 150 nm CMOS technology through MIT Lincoln Lab [1]. The vertical inter-unit communication is achieved by means of TSV, and the mesh interconnection provides a natural minimal area overhead associated with this communication. The prototype circuit measures 2mm×2mm. Test results demonstrated the effectiveness of such a DP-network for deadlock detection and the computational delay is less than 9 ns for detecting deadlock from a large-scale network. This work provides promising results for future networks-on-chip application using 3D embedded DP-network. © 2011 IEEE.

关键词： Network-on-chip

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Optimal Design-Space Exploration of Streaming Applications

Optimal Design-Space Exploration of Streaming Applications

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22nd IEEE international conference on Application-Specific systems, architectures and Processors (ASAP)

作者： Padmanabhan, Shobana Chen, Yixin Chamberlain, Roger D. Washington Univ Dept Comp Sci & Engn St Louis MO 63130 USA

ISBN: (纸本)9781457712920

Many embedded and scientific applications are pipelined (i.e.,streaming) and deployed on application-specific systems. Typically, there are several design parameters in the algorithms and architectures used that impact the tradeoff between different metrics of application performance as well as resource utilization. Efficient automatic exploration of this design space is the goal of our research. We present a global optimization framework comprising a domain-specific variation of branch-and-bound that reduces search complexity by exploiting the topology of the application's pipelining. We exploit the topological information to discover decomposability through the canonical Jordan block form. The reduction in search complexity for four real-world streaming applications (drawn from the literature) is significant, ranging from a million-fold reduction in search space size to a reduction factor of 10 billion. All four optimization problems are thereby solvable in reasonable time.

关键词： Clocks Computational modeling computer architecture Network topology Optimization Throughput Topology application specific systems branch-and-bound canonical Jordan block form computational complexity embedded applications global optimization framework optimal design space exploration optimisation pipeline processing resource allocation resource utilization scientific applications search complexity streaming applications tree searching

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modeling Dynamically Reconfigurable systems for simulation-based Functional Verification

Modeling Dynamically Reconfigurable Systems for Simulation-b...

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IEEE 19th Annual international Symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Gong, Lingkan Diessel, Oliver Univ New S Wales Sch Comp Sci & Engn Sydney NSW 2052 Australia

ISBN: (纸本)9780769543017

Dynamically Reconfigurable systems (DRS), which allow logic to be partially reconfigured during run-time, are promising candidates for embedded and high-performance systems. However, their architectural flexibility introduces a new dimension to the functional verification problem. Dynamic reconfiguration requires the designer to consider new issues such as synchronizing, isolating and initializing reconfigurable modules. Furthermore, by exposing the FPGA architecture to the application specification, it has made functional verification dependent on the physical implementation. This paper studies simulation as the most fundamental approach to the functional verification of DRS. The main contribution of this paper is in proposing a verification-driven top-down modeling methodology that guides designers in refining their reconfigurable system design from the behavioral level to the register transfer level. We assess the feasibility of our methodology via a case study involving the design of a generic partial reconfiguration platform.

关键词： Computational modeling computer bugs Data models Dynamically Reconfigurable systems FPGA FPGA architecture Field programmable gate arrays Functional Verification Hardware design languages Kernel Libraries Top-down modeling methodology application specification dynamically reconfigurable systems embedded system embedded systems formal specification formal verification high-performance system reconfigurable architectures register transfer level simulation-based functional verification verification-driven top-down modeling methodology

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