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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

共 2831 条记录，以下是121-130 订阅

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A Unifying Logic Encryption Security Metric 18

A Unifying Logic Encryption Security Metric

引用

18th international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Sisejkovic, Dominik Leupers, Rainer Ascheid, Gerd Metzner, Simon Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst Aachen Germany Hensoldt Cyber GmbH Ottobrunn Germany

ISBN: (纸本)9781450364942

The globalization of the IC supply chain has brought forth the era of fabless companies. Due to security issues during design and fabrication processes, various security concerns have risen, ranging from IP piracy and reverse engineering to hardware Trojans. Logic encryption has emerged as a mitigation against these threats. However, no generic metrics for quantifying the security of logic encryption algorithms has been reported so far, making it impossible to formally compare diferent approaches. In this paper, we propose a unifying metric, capturing the key security aspects of logic encryption algorithms. The metric is evaluated on state-of-the- art algorithms and benchmarks.

关键词： Hardware security security metrics obfuscation logic encryption

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Adaptive Runtime Exploiting Sparsity in Tensor of Deep Learning Neural Network on Heterogeneous systems 17

Adaptive Runtime Exploiting Sparsity in Tensor of Deep Learn...

引用

17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Peng, Kuo-You Fu, Sheng-Yu Liu, Yu-Ping Hsu, Wei-Chung Natl Taiwan Univ New Taipei Taiwan

ISBN: (纸本)9781538634370

Deep neural networks have been widely applied in many areas, such as computer vision, natural language processing and information retrieval. However, due to the high computation and memory demands, deep learning applications have not been adopted in edge learning. In this paper, we exploit the sparsity in tensors to reduce the computation overheads and memory demands. Unlike other approaches which rely on hardware accelerator designs or sacrifice model accuracy for the performance by pruning parameters, we adaptively partition and deploy the workload to heterogeneous devices to reduce computation and memory requirements and increase computing efficiency. We had implemented our partitioning algorithms in Google's TensorFlow and evaluated on an AMD Kaveri system, which is an HSA-based heterogeneous computing system. Our method has effectively reduced the computation time, cache accesses, and cache miss rates, without impacting the accuracy of the learning models. Our approach achieves 66% and 88% speedup for the lenet-5 model and the lenet-1024-1024 model, respectively. For reducing memory traffic, our approach reduces 71% instruction cache references, 32% data cache references. Our system has also improved cache miss rate from 1.6% to 0.5% during the training of the lenet-1024-1024 model.

关键词： Neurons Computational modeling Training Sparse matrices Machine learning Heterogeneous networks Tensile stress Heterogeneous networks Sparse matrix Tensile stress Computational modeling Tensor HETEROGENEOUS SYSTEM Functional training Neurons Memory Memory Partitioning algorithms Machine Learning cache miss Training Artificial Intelligence

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ESL Power Estimation using Virtual Platforms with Black Box Processor Models 15

ESL Power Estimation using Virtual Platforms with Black Box ...

引用

international conference on embedded computer systems architectures modeling and simulation

作者： Schuermans, Stefan Onnebrink, Gereon Leupers, Rainer Ascheid, Gerd Chen, Xiaotao Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst Aachen Germany Huawei Technol Co Ltd Bridgewater NJ USA

ISBN: (纸本)9781467373111

Processor models for electronic system level (ESL) simulations are usually provided by their vendors as binary object code. Those binaries appear as black boxes, which do not allow to observe their internals. This prevents the application of most existing ESL power estimation methodologies. To remedy this situation, this work presents an estimation methodology for the case of black box models. The evaluation for the ARM Cortex-A9 processor shows that the proposed approach is able to achieve a high accuracy. In comparison to hardware power measurements obtained from the OMAP4460 chip on the PandaBoard, the ESL estimation error is below 5%.

关键词： English as Second Language PROCESSOR BLACK-BOX power estimation Power measurement Vendors Boxes Buxus sempervirens

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Multi-objective topology optimization for networked embedded systems

Multi-objective topology optimization for networked embedded...

引用

6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Streichert, Thilo Haubelt, Christian Teich, Juergen Univ Erlangen Nurnberg D-8520 Erlangen Germany

ISBN: (纸本)1424401550

In this paper, a new methodology is presented for topology optimization of networked embedded systems as they occur in automotive and avionic systems and partially in wireless sensor networks. By introducing a model which is (1.) suitable for heterogeneous networks with different communication bandwidths, (2.) modeling of routing restrictions, and (3.) flexible binding of tasks onto processors, current design issues of networked embedded systems can be investigated. On the basis of this model, the presented methodology firstly allocates the required resources which can be communication links as well as computational nodes and secondly binds the functionality onto the nodes and the data dependencies onto the links such that no routing restrictions will be violated or capacities on communication links will be exceeded. By applying Evolutionary Algorithms, we are able to consider multiple objectives simultaneously during the optimization process and allow for a subsequent unbiased decision making. An experimental evaluation as well as a demonstration of a case study from the field of automotive electronics will show the applicability of the presented approach.

关键词： Heterogeneous networks

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Performance evaluation of memory management configurations in linux for an OS-level design space exploration

引用

international conference on embedded computer systems - architectures, modeling and simulation

作者： Park, Sangsoo Shin, Heonshik Univ Michigan Dept Elect Engn & Comp Sci 2260 Hayward St Ann Arbor MI 48109 USA Seoul Natl Univ Sch Comp Sci Seoul South Korea

ISBN: (纸本)9783540736226

The objective of this paper is to analyze how the memory management configuration in Linux influences run-time performance of embedded systems. Extensive experiments confirm that the configuration of the memory management subsystem significantly affects the overall execution time, the memory performance, and the system call overhead. Our quantitative experimental results will help embedded systems designers to understand the effect of memory management configurations on the applications within a system, and contribute to the design of more efficient systems with an OS-level design space exploration.

关键词： computer operating systems

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Domain-specific modeling of power aware distributed real-time embedded systems

Domain-specific modeling of power aware distributed real-tim...

引用

6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Madl, Gabor Dutt, Nikil Univ Calif Irvine Ctr Embedded Comp Syst Irvine CA 92697 USA

ISBN: (纸本)3540364102

This paper provides two contributions to the research on applying domain-specific modeling languages to distributed real-time embedded (DRE) systems. First, we present the ALDERIS platform-independent visual language for component-based system development. Second, we demonstrate the use of the ALDERIS language on a helicopter autopilot DRE design. The ALDERIS language is based on the concept of platform-based design, and explicitly captures asynchronous event-driven component interactions as well as the underlying platform for the computation. Unlike most modeling languages, ALDERIS has formally defined semantics providing a way for the formal verification of dense real-time properties and energy consumption.

关键词： embedded systems

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Efficient Hardware Implementation of Data-Flow Parallel embedded systems

Efficient Hardware Implementation of Data-Flow Parallel Embe...

引用

international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Quinton, Patrice Chana, Anne-Marie Derrien, Steven Univ Europeenne Bretagne ENS Cachan Bretagne F-35170 Bruz France

ISBN: (纸本)9781467322973;9781467322966

Many modern computing systems deal with streams of data, which have to be processed in parallel in order to be handled in real-time. This is in particular the case for some kind of cyber physical systems, which process data provided by physical devices. We consider here an approach to generate efficient hardware for-a particular class of-such systems, which relies upon the polyhedral model. Flexible parallel components, described by the ALPHA functional language, are modelled and assembled using a scheduling method which combines the synchronous data-flow principle of balance equations, and the polyhedral scheduling technique. The modelling of flexible components relies on a simple, affine-periodic, delayable and stretchable time model, which allows a full system to be assembled and synthesized by combining the component hardware descriptions with automatically generated wrappers. We illustrate this method on a simplified WCDMA system and we discuss the relationship of this approach with stream languages, latency-insensitive design, and multidimensional data-flow systems.

关键词： computer hardware Flexible components Parallel Lines Hydrologic models streams embedded systems Equation Cyber-physical systems assemblies rivers Functional programming WRAPPERS

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On the modeling of Error Functions as High Dimensional Landscapes for Weight Initialization in Learning Networks 16

On the Modeling of Error Functions as High Dimensional Lands...

引用

international conference on embedded computer systems - architectures, modeling and simulation (SAMOS)

作者： Julius Mahale, Gopinath Sumana, T. Adityakrishna, C. S. BITS Pilani Dept Phys Hyderabad Andhra Pradesh India BITS Pilani Dept Comp Sci Hyderabad Andhra Pradesh India Indian Inst Sci CAD Lab Bengaluru India

ISBN: (纸本)9781509030767

Next generation deep neural networks for classification hosted on embedded platforms will rely on fast, efficient, and accurate learning algorithms. Initialization of weights in learning networks has a great impact on the classification accuracy. In this paper we focus on deriving good initial weights by modeling the error function of a deep neural network as a high-dimensional landscape. We observe that due to the inherent complexity in its algebraic structure, such an error function may conform to general results of the statistics of large systems. To this end we apply some results from Random Matrix Theory to analyse these functions. We model the error function in terms of a Hamiltonian in N-dimensions and derive some theoretical results about its general behavior. These results are further used to make better initial guesses of weights for the learning algorithm.

关键词： Learning algorithms

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Efficiency measures for multimedia SOCs

引用

international conference on embedded computer systems - architectures, modeling and simulation

作者： Jeschke, Hartwig Leibniz Univ Hannover Inst Mikroelect Syst D-30167 Hannover Germany

ISBN: (纸本)9783540736226

This paper discusses efficiency measures for the evaluation of high performance multimedia systems on a chip (SOC), considering a throughput rate R, chip size A, power dissipation P, and a flexibility criterion F. Based on the analysis of recently published multimedia chips, the paper shows equivalences between the ratio of R over AP, a weighted sum on 1/R, A P, and a fuzzy multicriteria analysis on R, A, P. The paper indicates the fuzzy multicriteria analysis as generalization of the other efficiency measures, which can be easily applied to multiple cost and performance criteria. Because of the application of fuzzy set theory, the multicriteria approach supports quantitative criteria with a physical background as well as qualitative criteria by linguistic variables.

关键词： embedded systems

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TimeCube: A Manycore embedded Processor with Interference-Agnostic Progress Tracking

TimeCube: A Manycore Embedded Processor with Interference-Ag...

引用

13th international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Gupta, Anshuman Sampson, Jack Taylor, Michael Bedford Univ Calif San Diego San Diego CA 92103 USA

ISBN: (纸本)9781479901036

Recently introduced processors such as Tilera's Tile Gx100 and Intel's 48-core SCC have delivered on the promise of high performance per watt in manycore processors, making these architectures ostensibly as attractive for low-power embedded processors as for cloud services. However, these architectures space-multiplex the microarchitectural resources between many threads to increase utilization, which leads to potentially large and varying levels of interference. This decorrelates CPU-time from actual application progress and decreases the ability of traditional software to accurately track and finely control application progress, hindering the adoption of manycore processors in embedded computing. In this paper we propose Progress Time as the counterpart of CPU-time in space-multiplexed systems and show how it can be used to track application progress. We also introduce TimeCube, a manycore embedded processor that uses dynamic execution isolation and shadow performance modeling to provide an accurate online measurement of each application's Progress Time. Our evaluation shows that a 32-core TimeCube processor can track application progress with less than 1% error even in the presence of a 6x average worst-case slowdown. TimeCube also uses Progress Times to perform online architectural resource management that leads to a 36% improvement in throughput compared to existing microarchitectural resource allocation schemes. Overall, the results argue for adding the requisite microarchitectural structures to support Progress Time in manycore chips for embedded systems.

关键词： cloud computing embedded systems interference microprocessor chips multiprocessing systems resource allocation

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