Dynamically Reconfigurable systems (DRS), which allow logic to be partially reconfigured during run-time, are promising candidates for embedded and high-performance systems. However, their architectural flexibility in...
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ISBN:
(纸本)9780769543017
Dynamically Reconfigurable systems (DRS), which allow logic to be partially reconfigured during run-time, are promising candidates for embedded and high-performance systems. However, their architectural flexibility introduces a new dimension to the functional verification problem. Dynamic reconfiguration requires the designer to consider new issues such as synchronizing, isolating and initializing reconfigurable modules. Furthermore, by exposing the FPGA architecture to the application specification, it has made functional verification dependent on the physical implementation. This paper studies simulation as the most fundamental approach to the functional verification of DRS. The main contribution of this paper is in proposing a verification-driven top-down modeling methodology that guides designers in refining their reconfigurable system design from the behavioral level to the register transfer level. We assess the feasibility of our methodology via a case study involving the design of a generic partial reconfiguration platform.
Real-Time embeddedsystems must respect a wide range of non-functional properties, including safety, respect of deadlines, power or memory consumption. We note that correct hardware resource dimensioning requires taki...
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ISBN:
(纸本)9780769543819
Real-Time embeddedsystems must respect a wide range of non-functional properties, including safety, respect of deadlines, power or memory consumption. We note that correct hardware resource dimensioning requires taking into account the impact of the whole software, both the user code and the underlying runtime environment. AADL allows one to precisely capture all of them. In this article, we evaluate the AADL modeling to define memory architectures, and then verification rules to assess that the memory is correctly dimensioned. We use the REAL domain-specific language to express memory requirements (such as layout or size) and then validate them on a case-study using the VxWorks real-time kernel.
Modern embeddedsystems are increasingly likely to be distributed across multiple devices and platforms that must interact with high precision across wireless networks. Traditional ways of managing the wireless radio ...
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ISBN:
(纸本)9780769544397
Modern embeddedsystems are increasingly likely to be distributed across multiple devices and platforms that must interact with high precision across wireless networks. Traditional ways of managing the wireless radio spectrum suffer from two fundamental limitations, which the research presented in this paper addresses: (1) spectrum is divided a priori into static coarse-grained partitions without reference to details of particular applications;and (2) partitions are non-overlapping, which although beneficial to reduce interference prevents a much greater utilization of the spectrum through carefully allowing overlap of spectrum allocations. To overcome these limitations, we propose an approach to spectrum allocation based on dynamic allocation of diverse portions of the overall spectrum and overlapping allocations to increase utilization. This paper makes three main contributions to the state of the art in spectrum management for embeddedsystems: (1) it examines how memory management techniques such as Knuth's buddy algorithm can be applied to spectrum management, in the face of transmission failures that may arise from the physical environment;(2) it extends that approach to consider transmission failures resulting from interference, when overlapping regions of spectrum are allocated to increase utilization;and (3) it presents results of simulation experiments we conducted to evaluate those approaches, which demonstrate their efficacy and suggest future extensions based on them.
In this paper we present a structured hardware/software codesign approach to modeling and development of embeddedsystems for many-core platforms. Our method is based on the combination of three technologies that are ...
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ISBN:
(纸本)9783642183805
In this paper we present a structured hardware/software codesign approach to modeling and development of embeddedsystems for many-core platforms. Our method is based on the combination of three technologies that are not commonly used in such a context: a.) programmable hardware, b.) high-level computing model and programming language, and c.) hybrid hardware/software compilation. Resulting benefits are better reliability and performance, as well as higher productivity, portability and scalability thanks to a fully integrated design flow. We shall also show that our method is promising in terms of resource-efficiency and in particular energy-efficiency. An application from the medical ICT area will serve as a proof of concept.
The proceedings contain 25 papers. The topics discussed include: low-overhead virtualization of mobile platforms;a method-based ahead-of-time compiler for android applications;studying optimal spilling in the light of...
ISBN:
(纸本)9781450307130
The proceedings contain 25 papers. The topics discussed include: low-overhead virtualization of mobile platforms;a method-based ahead-of-time compiler for android applications;studying optimal spilling in the light of SSA;an efficient heuristic for instruction scheduling on clustered VLIW processors;graph-coloring and treescan register allocation using repairing;a unified approach to eliminate memory accesses early;an evaluation of different modeling techniques for iterative compilation;a novel thread scheduler design for polymorphic embeddedsystems;realizing near-true voltage scaling in variation-sensitive L1 caches via fault buffers;FFT-cache: a flexible fault-tolerant cache architecture for ultra low voltage operation;smart cache cleaning: energy efficient vulnerability reduction in embedded processors;cost-effective safety and fault localization using distributed temporal redundancy;and stochastic computing: embracing errors in architecture and design of processors and applications.
A major concern of current and future on-chip systems is the thermal problem i.e. electrical energy is dissipated leading to high chip temperatures. Short term effects may include transient malfunctioning whereas long...
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ISBN:
(纸本)9783642241536;9783642241543
A major concern of current and future on-chip systems is the thermal problem i.e. electrical energy is dissipated leading to high chip temperatures. Short term effects may include transient malfunctioning whereas long-term effects may lead to deteriorating functionality (e.g. increased signal travel times) or to irreversible damage due to, for example, electro-migration. The problem worsens with the inception of 3D architectures as the per-surface dissipated electrical energy is larger, e.g. our evaluation shows an increase of 37.5% in peak temperature in an architecture with 2 layers compared to a single layer architecture. Our proposed concept addresses thermal problems in 3D-stacked many-core architectures resulting from high power densities. A hierarchical agent-based thermal management system initiates a proactive task migration onto cooler processing resources while a communication virtualization layer dynamically adapts and protects connectivity between (migrated) tasks and external I/Os.
Architecture exploration for embeddedsystems is becoming an indispensable tool for System-on-Chip designers. This process requires the evaluation of many architectures that are generated during the exploration proces...
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embeddedsystems and their design trajectories are becoming increasingly complex, and there is a growing demand for performance, reliability, energy efficiency and low cost. To cope with these challenges, decision mak...
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embeddedsystems and their design trajectories are becoming increasingly complex, and there is a growing demand for performance, reliability, energy efficiency and low cost. To cope with these challenges, decision making early in the development trajectory needs to be supported by appropriate modeling and analysis. To achieve this support, we need to find the modeling abstractions that allow extensive design-space exploration, tune these modeling abstractions towards the users, and integrate support for different types of modeling and analysis.
The development of electronic technology today has allowed the implementation of complex architectures, which led to the emergence of multicore processors technology. Multicore architectures are built from superscalar...
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embedded multimedia and wireless applications require a model-based design approach in order to satisfy stringent quality and cost constraints. The Model-of-Computation (MoC) should appropriately capture system dynami...
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embedded multimedia and wireless applications require a model-based design approach in order to satisfy stringent quality and cost constraints. The Model-of-Computation (MoC) should appropriately capture system dynamics, support analysis and synthesis, and allow low-overhead model-driven implementations. This combination poses a significant challenge. The Scenario-Aware DataFlow (SADF) MoC has been introduced to address this challenge. This paper surveys SADF, and compares dataflow MoCs in terms of their ability to capture system dynamics, their support for analysis and synthesis, and their implementation efficiency.
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