检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

2,723 篇 会议
57 册 图书
54 篇 期刊文献

馆藏范围

2,834 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,289 篇 工学
- 1,120 篇 计算机科学与技术...
- 591 篇 软件工程
- 287 篇 电气工程
- 159 篇 电子科学与技术（可...
- 150 篇 控制科学与工程
- 137 篇 信息与通信工程
- 50 篇 机械工程
- 44 篇 动力工程及工程热...
- 19 篇 仪器科学与技术
- 19 篇 建筑学
- 18 篇 材料科学与工程（可...
- 18 篇 安全科学与工程
- 17 篇 土木工程
- 16 篇 生物医学工程（可授...
- 14 篇 交通运输工程
- 14 篇 航空宇航科学与技...
- 13 篇 力学（可授工学、理...
- 12 篇 生物工程
- 11 篇 光学工程
275 篇 理学
- 173 篇 数学
- 81 篇 系统科学
- 38 篇 物理学
- 33 篇 统计学（可授理学、...
- 14 篇 化学
- 14 篇 生物学
142 篇 管理学
- 119 篇 管理科学与工程(可...
- 52 篇 工商管理
- 30 篇 图书情报与档案管...
21 篇 经济学
- 21 篇 应用经济学
20 篇 法学
- 20 篇 社会学
11 篇 医学
6 篇 教育学
5 篇 农学
3 篇 军事学
1 篇 文学
1 篇 艺术学

主题

763 篇 computational mo...
616 篇 computer archite...
361 篇 hardware
222 篇 embedded systems
144 篇 analytical model...
142 篇 embedded system
134 篇 computer simulat...
128 篇 application soft...
123 篇 mathematical mod...
117 篇 field programmab...
112 篇 real time system...
103 篇 program processo...
91 篇 embedded computi...
89 篇 kernel
84 篇 software
83 篇 computer science
82 篇 parallel process...
81 篇 registers
73 篇 control systems
72 篇 algorithm design...

机构

10 篇 school of electr...
9 篇 rhein westfal th...
8 篇 institute for co...
8 篇 center for embed...
7 篇 center for embed...
7 篇 department of co...
6 篇 eindhoven univer...
6 篇 computer systems...
6 篇 natl tech univ a...
6 篇 computer systems...
6 篇 institute for co...
6 篇 fraunhofer iese ...
5 篇 school of automa...
5 篇 school of electr...
5 篇 university of za...
5 篇 embedded systems...
5 篇 university of te...
5 篇 national cims en...
5 篇 the university o...
5 篇 eindhoven univer...

作者

19 篇 leupers rainer
16 篇 soudris dimitrio...
16 篇 ascheid gerd
14 篇 dimitrios soudri...
13 篇 rainer leupers
12 篇 gerd ascheid
12 篇 takala jarmo
12 篇 pimentel andy d.
11 篇 blume holger
11 篇 holger blume
10 篇 andy d. pimentel
10 篇 jung matthias
9 篇 mohamed abid
9 篇 fornaciari willi...
9 篇 pnevmatikatos di...
9 篇 kostas siozios
9 篇 christian haubel...
9 篇 andreas gerstlau...
9 篇 wehn norbert
8 篇 f. fummi

语言

2,817 篇 英文
9 篇 其他
9 篇 中文

检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

共 2834 条记录，以下是1321-1330 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Architecture design space exploration of run-time scalable issue-width processors

Architecture design space exploration of run-time scalable i...

引用

international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Ralf Koenig Timo Stripf Jan Heisswolf Juergen Becker Karlsruhe Institute of Technology Karlsruhe Germany

Reconfigurable chip multiprocessors realizing very long instruction word (VLIW) processors of dynamically-scalable issue width enable resource-aware adaptation to diverse processing requirements. The execution performance of such clustered VLIW processors is significantly influenced by different design parameters of the fundamental processing cores. In this paper we present a design space exploration addressing the following design parameters: the register file size, number of issue slots, inter cluster move bandwidth, and latency. We thereby investigate the quantitative performance impact of each parameter as well their interdependency for 18 benchmarks of different processing domains. Our results show that the cluster configuration significantly influences the processing performance: the performance loss compared to theirs unclustered architectures can be as low as 2% but also may exceed 100%.

关键词： Registers Program processors Tiles VLIW Bandwidth Benchmark testing computer architecture

来源：评论

学校读者我要写书评

暂无评论

Fully-automatic derivation of exact program-flow constraints for a tighter worst-case execution-time analysis

Fully-automatic derivation of exact program-flow constraints...

引用

international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Amine Marref Department of Computer Science Umm Al-Qura University Makkah Saudi Arabia

Obtaining tight worst-case execution-time (WCET) estimations of real-time tasks is crucial since overly-pessimistic estimations are deemed impractical. One way of making WCET estimations tighter is to incorporate more program-flow information e.g., context-sensitive loop bounds, infeasible-path and same-path information, etc. In this paper we present and evaluate a completely automatic analysis that dynamically derives program-flow information to use in WCET analysis. Flow information is derived by a combination of test-data generation and parsing of program-execution traces to obtain flow-fact hypotheses which are then fed to a model checker to establish their correctness. Experimental evaluation shows that our method help achieve considerable tightness in WCET estimations at a manageable cost.

关键词： Estimation Hardware Correlation Analytical models Context modeling Predictive models Timing

来源：评论

学校读者我要写书评

暂无评论

Optimizing distributed architectures to improve performance on checkpointing applications

Optimizing distributed architectures to improve performance ...

引用

13th IEEE international Workshop on FTDCS 2011, the 8th international conference on ATC 2011, the 8th international conference on UIC 2011 and the 13th IEEE international conference on HPCC 2011

作者： Núñez, Alberto Fernández, Javier Carretero, Jesús Prada, Laura Blaum, Mario Computer Architecture Group Computer Science Department University Carlos III de Madrid Spain IBM Almaden Research Center San Jose CA United States

ISBN: (纸本)9780769545387

Nowadays, satisfying the global throughput targets of each application in High Performance Computing systems is a difficult task because of the high number of architectural configurations having a considerable impact on the overall system performance, such as the number of storage servers, features of the communication links, number of CPU cores per node, etc. In this paper we have performed a thorough study of the compared performance of scaling up HPC cluster architectures using a checkpointing application model. This study is specifically focused on multi-core HPC clusters and the scaling process is oriented towards the three main resources: computing power, communications and storage. The main goal of this work is to evaluate and analyze how evolves both scalability and bottlenecks existent on different HPC multi-core architectures using different architectural configurations. In order to achieve this goal, a set of simulation experiments has been achieved using a simulation framework, called SIMCAN, specifically designed for modeling and simulating HPC architectures. The results obtained show that the computing power is well suited thanks to the multi-core processors, while the problems are found on the storage and on the communications channels, being the storage network the main bottleneck. © 2011 IEEE.

关键词： Computing power

来源：评论

学校读者我要写书评

暂无评论

Instruction buffer with limited control flow and loop nest support

Instruction buffer with limited control flow and loop nest s...

引用

international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Vladimír Guzma Teemu Pitkänen Jarmo Takala Department of Computer Systems Tampere University of Technology Tampere Finland

In this work, we present a minimalistic, energy efficient implementation of instruction buffer. We use loop detection and execution trace analysis to find most commonly executed loops in already scheduled application and tailor instruction buffer size to the size of most commonly executed loop(s). In addition to our previous work, we allow buffering of loops with limited control flow (early exit from the loop or early return to the beginning of the loop). We also show how analysis of loop nests can decrease the number of times loop body is copied from memory into the buffer. Our results show that in case of favorable loop nest, we can execute all but initial loop iterations from the instruction buffer, keeping instruction memory in the deselect mode.

关键词： Buffer storage Radiation detectors Memory management Logic gates Energy consumption Registers Discrete cosine transforms

来源：评论

学校读者我要写书评

暂无评论

TCEMC: A co-design flow for application-specific multicores

TCEMC: A co-design flow for application-specific multicores

引用

international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Pekka O. Jääskeläinen Erno O. Salminen Carlos S. de La Lama Jarmo H. Takala Jose Ignacio Martinez Department of Computer Systems Tampere University of Technology Tampere Finland Department of Computer Architecture Universidad Rey Juan Carlos Madrid Spain

Contemporary embedded systems are often designed as Multiprocessor System-on-Chips (MPSoC) which include multiple processors and other peripherals on a single chip. In contrast to general purpose multiprocessors, the design of an embedded MPSoC is usually customized to the requirements of the application domain. The need for fast time to market of new embedded MPSoC designs calls for a rapid design flow of the included customized processors. This paper proposes a Multicore Application-Specific Instruction Set Processor (MCASIP) co-design flow that exploits parallel programming languages as the application description format. The designer can capture the parallelism of the algorithm and exploit specialized instructions using a single high-level programming language. Parallelism of the designed MCASIP architectures can be scaled both at instruction and task levels, enabling easy exploration of the MCASIP design space. This paper describes the design flow and its key technical challenges, and demonstrates its scalability potential. The presented preliminary results show promise for an efficient multiprocessor design methodology.

关键词： Instruction sets Multicore processing Libraries Parallel processing Programming

来源：评论

学校读者我要写书评

暂无评论

Challenges of multi- and many-core architectures for electronic system-level design

Challenges of multi- and many-core architectures for electro...

引用

international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Kim Grüttner Philipp A. Hartmann Philipp Reinkemeier Frank Oppenheimer Wolfgang Nebel Philipp Reinkemeier and Frank Oppenheimer OFFIS – Institute for Information Technology Oldenburg Germany OFFIS - Institute for Information Technology Oldenburg Germany Carl von Ossietzky Universität Faculty II Department of Computer Science Oldenburg Germany

In today's design of embedded systems the software part is increasingly important. Over the last years we have observed a shift from hardware to software added value. With the rise of multi- and many-core platforms even more complex software systems can be implemented. To efficiently map software applications to such architectures, the impact of platform decisions with respect to the hardware and the software infrastructure (OS, scheduling policies, priorities, mapping) has to be explored in early design phases. In this work, we discuss the challenges of the multi- and many-core design-space. We give an overview of our existing SystemC™-based OSSS design flow including software multitasking in system-level models. We propose extensions towards multi- and many-core platform models and discuss which aspects of the system behaviour can be captured. Since this is work in progress we end up with challenges which have not been solved until now and propose new concepts to overcome the current limitations.

关键词： computer architecture Hardware Synchronization Program processors Operating systems Runtime

来源：评论

学校读者我要写书评

暂无评论

Special session on “What's next for ESL”

Special session on “What's next for ESL”

引用

international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Christian Haubelt University of Erlangen-Nuremberg DE

With the continuous increase in size, complexity and heterogeneity, the EDA community has to face the new challenges of designing future embedded systems. In this context, novel Electronic System Level (ESL) design flows are expected to significantly increase productivity by optimizing such systems across hardware/software boundaries while considering tens to hundreds of processing cores simultaneously. However, due to the complex nature of ESL design, future design flows have to integrate novel solutions in high speed virtual prototyping for early validation and performance evaluation as well as mapping and design space exploration to generate competitive high quality implementations. Moreover, novel synthesis approaches for embedded software and communication synthesis become mandatory to guarantee an efficient usage of processing and communication resources. The special session on “What's next for ESL” is composed of four papers. One paper discusses architectural issues in the multi-processor era with a focus on communication refinement. Two papers present the state-of the-art in future trends in embedded software synthesis in the presence of multi-core architectures. One of these papers focuses on the role of software synthesis in the overall ESL design flow, whereas the second one focuses on model-based software synthesis approaches. Finally, one paper presents future challenges in design space exploration when performed on the Electronic System Level.

关键词： Space exploration embedded software Hardware Communities Productivity Virtual prototyping

来源：评论

学校读者我要写书评

暂无评论

Multicore Communications API (MCAPI) implementation on an FPGA multiprocessor

Multicore Communications API (MCAPI) implementation on an FP...

引用

international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Lauri Matilainen Erno Salminen Timo D. Hämäläinen Marko Hännikäinen Department of Computer Systems Tampere University of Technology Tampere Finland

The design and implementation of an application programming interface (API) is a trade-off between abstraction it provides and overheads it causes. This paper presents an implementation of Multicore Communications API (MCAPI) on a heterogeneous platform consisting of FPGA-based multiprocessor system-on-chip (MPSoC) connected via PCIe to an external CPU board. The purpose is to provide a unified programming API to different processor and OS types as well as hardware IP-blocks. MCAPI is shown to meet these requirements. We show the MCAPI transport implementation on three processors and two buses, measure the overhead cost, and analyze the effort required to port an application from a PC to the MPSoC. The measured library memory footprint is less than 25KB and the roundtrip communication latency is diminishing low - only few dozen clock cycles - compared to non-MCAPI implementation.

关键词： Field programmable gate arrays Hardware Software Programming Multicore processing Message systems

来源：评论

学校读者我要写书评

暂无评论

Calibration and validation of software performance models for pedestrian detection systems

Calibration and validation of software performance models fo...

引用

international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Rainer Kiesel Martin Streubühr Christian Haubelt Otto Löhlein Jürgen Teich Department Environment Perception (GR/PAP) Daimler AG Ulm Germany Department of Computer Science University of Erlangen–Nuremberg Germany

In recent years, road vehicles have seen a tremendous increase on driver assistance systems like lane departure warning, traffic sign recognition, or pedestrian detection. The development of efficient and cost-effective electronic control units that meet the necessary real-time performance for these systems is a complex challenge. Often, Electronic System-Level design tackles the challenge by simulation-based performance evaluation, although, the quality of system-level performance simulation approaches is not yet evaluated in detail. In this paper, we present the calibration and validation of a system-level performance simulation model. For evaluation, an automotive pedestrian detection algorithm is studied. Especially the varying number of pedestrians has a significant impact to the system performance and makes the prediction of execution time difficult. As test cases we used typical sequences and corner cases recorded by an experimental car. Our evaluation results indicate that prediction of execution times with an average error of 3.1% and a maximum error of 7.9% can be achieved. Thereby, simulated and measured execution times of a software implementation are compared.

关键词： Software Calibration Estimation Accuracy Dynamic scheduling Computational modeling Processor scheduling

来源：评论

学校读者我要写书评

暂无评论

FPGA based application specific processing for sensor nodes

FPGA based application specific processing for sensor nodes

引用

international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Teemu Nyländen Janne Janhunen Jari Hannuksela Olli Silvén Computer Science and Engineering Laboratory University of Oulu Finland Centre of Wireless Communications Computer Science and Engineering Laboratory University of Oulu Finland

Energy efficient sensor nodes are among the rapidly expanding applications for embedded systems technology. Typically, the processing resources in sensor nodes are based on programmable micro-controllers and digital signal processors, and the same processing architecture is used regardless of the actual task of the node. This regularly results in at least an order of magnitude over-provisioning of resources, and in higher power consumption than would be needed by tightly application specific processing solutions. Currently, experiments show that Flash FPGA technology enables implementing precisely provisioned processing for sensor nodes with energy efficiency that rivals off-the-shelf processor solutions. The expected competitiveness originates from savings in silicon real-estate, and lowered software overheads, as inherently parallel tasks can be offloaded to dedicated hardware accelerators on the same die with a microcontroller unit, and radio baseband. The results pave the way for a novel type of self-powered sensor nodes whose processing resources are configured according to their tasks.

关键词： Cyclones Random access memory Field programmable gate arrays computer architecture Wireless sensor networks Power dissipation Energy consumption

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共284页 << < 129 130 131 132 133 134 135 136 137 138 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：