With Moore's law supplying billions of transistors on-chip, embeddedsystems are undergoing a transition from single-core to multi-core to exploit this high transistor density for high performance. However, the op...
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With Moore's law supplying billions of transistors on-chip, embeddedsystems are undergoing a transition from single-core to multi-core to exploit this high transistor density for high performance. However, the optimal layout of these multiple cores along with the memory subsystem (caches and main memory) to satisfy power, area, and often stringent real-time constraints is a challenging design endeavor. The short time-to-market constraint of embeddedsystems exacerbates this design challenge and necessitates the architectural modeling of embeddedsystems to reduce the time-to-market by expediting target applications to device/architecture mapping. In this paper, we present a queueing theoretic approach for modeling multi-core embeddedsystems that provides a quick and inexpensive performance evaluation both in terms of time and resources as compared to the development of multi-core simulators and running benchmarks on these simulators. We also calculate chip area and power consumption for different multi-core embeddedarchitectures with a varying number of processor cores and cache configurations to provide a comparative analysis of multicore embeddedarchitectures in terms of performance, area, and power consumption. Our performance and power results indicate that multi-core embedded system architectures that leverage shared last-level caches (LLCs) provide the best LLC performance per watt but may introduce main memory response time and throughput bottlenecks for high cache miss rates, whereas architectures leveraging a hybrid of private and shared LLCs alleviate main memory bottlenecks at the expense of reduced performance per watt.
The concept of "Microgrid" is one of the most promising architectures expected to support the transition from present to future Electricity Grids by integrating large amounts of Renewable Energy Sources. The...
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Abstract models are means to assist system architects in the evaluation process of hardware/software architectures and then to cope with the still increasing complexity of embeddedsystems. Efficient methods are neces...
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Abstract models are means to assist system architects in the evaluation process of hardware/software architectures and then to cope with the still increasing complexity of embeddedsystems. Efficient methods are necessary to correctly model system architectures and to make possible early performance evaluation and fast exploration of the design space. In this paper, we present the use of a specific modeling approach to improve evaluation of non-functional properties of embeddedsystems. The contribution is about a computation method defined to improve modeling of properties used for assessment of architecture performances. This method favors creation of abstract transaction level models and leads to significantly reducing simulation time but still preserving accuracy of results. The benefits of the proposed approach for evaluation of performances of system architectures are highlighted through analysis of two specific case studies.
Due to increasing complexity of communication infrastructures in the automotive domain, reliable models are necessary in order to assist designers in the development process of networked embeddedsystems. In this cont...
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Due to increasing complexity of communication infrastructures in the automotive domain, reliable models are necessary in order to assist designers in the development process of networked embeddedsystems. In this context, transaction level modeling, supported by languages as SystemC, is a promising solution to assess performances of networked architectures with a good compromise between accuracy and simulation speed. This article presents the application of a specific modeling approach for performance evaluation of a networked embedded system inspired from the automotive domain. The considered approach is illustrated by the modeling of a video transmission system made of three electronic controller units and based on a specific power line communication protocol. The created model incorporates description of various communication layers and simulation of the model allows evaluation of time properties and memory cost inferred.
Neural networks present a fundamentally different model of computation from conventional sequential hardware, making it inefficient for very-large-scale models. Current neuromorphic devices do not yet offer a fully sa...
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ISBN:
(纸本)9781424496365
Neural networks present a fundamentally different model of computation from conventional sequential hardware, making it inefficient for very-large-scale models. Current neuromorphic devices do not yet offer a fully satisfactory solution even though they have improved simulation performance, in part because of fixed hardware, in part because of poor software support. SpiNNaker introduces a different approach, the "neuromimetic" architecture, that maintains the neural optimisation of dedicated chips while offering FPGA-like universal configurability. Central to this parallel multiprocessor is an asynchronous event-driven model that uses interrupt-generating dedicated hardware on the chip to support real-time neural simulation. In turn this requires an event-driven software model: a rethink as fundamental as that of the hardware. We examine this event-driven software model for an important hardware subsystem, the previously-introduced virtual synaptic channel. Using a scheduler-based system service architecture, the software can "hide" low-level processes and events from models so that the only event the model sees is "spike received". Results from simulation on-chip demonstrate the robustness of the system even in the presence of extremely bursty, unpredictable traffic, but also expose important model-level tradeoffs that are a consequence of the physical nature of the SpiNNaker chip. This event-driven subsystem is the first component of a library-based development system that allows the user to describe a model in a high-level neural description environment and be able to rely on a lower layer of system services to execute the model efficiently on SpiNNaker. Such a system realises a general-purpose platform that can generate an arbitrary neural network and run it with hardware speed and scale.
Real-Time embeddedsystems must respect a wide range of non-functional properties, including safety, respect of deadlines, power or memory consumption. We note that correct hardware resource dimensioning requires taki...
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Real-Time embeddedsystems must respect a wide range of non-functional properties, including safety, respect of deadlines, power or memory consumption. We note that correct hardware resource dimensioning requires taking into account the impact of the whole software, both the user code and the underlying run time environment. AADL allows one to precisely capture all of them. In this article, we evaluate the AADL modeling to define memory architectures, and then verification rules to assess that the memory is correctly dimensioned. We use the REAL domain-specific language to express memory requirements (such as layout or size) and then validate them on a case-study using the VxWorks real-time kernel.
The synchronous model of computation (MoC) has been successfully used for the design of embeddedsystems having a local control like hardware circuits and single-threaded software, while its application to distributed...
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The synchronous model of computation (MoC) has been successfully used for the design of embeddedsystems having a local control like hardware circuits and single-threaded software, while its application to distributed parallel embeddedsystems is still a challenge. In contrast, other MoCs such as data-flow process networks (DPNs) directly match with these architectures. In this paper, we therefore present a translation of synchronous systems to data-flow process networks, thereby bridging the gap between synchronous and asynchronous MoCs. We use the resulting DPNs to generate CAL code for the Open DF package, which offers important features for embedded system design.
The increasing complexity of communication infrastructures in the automotive domain implies the use of reliable models to assist designers in the development process of networked embeddedsystems. In this context, tra...
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The increasing complexity of communication infrastructures in the automotive domain implies the use of reliable models to assist designers in the development process of networked embeddedsystems. In this context, transaction level modeling, supported by languages as SystemC, is a promising solution to assess performances of networked architectures with a good compromise between accuracy and simulation speed. This article presents the modeling and performance evaluation of a video transmission system supported by three electronic controller units and based on a specific power line communication protocol. The created model incorporates the various communication layers considered. The simulation of the model allows the evaluation of time properties and memory cost inferred.
The Extreme-scale Simulator (xSim) is a recently developed performance investigation toolkit that permits running high-performance computing (HPC) applications in a controlled environment with millions of concurrent e...
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The Extreme-scale Simulator (xSim) is a recently developed performance investigation toolkit that permits running high-performance computing (HPC) applications in a controlled environment with millions of concurrent execution threads. It allows observing parallel application performance properties in a simulated extreme-scale HPC system to further assist in HPC hardware and application software co-design on the road toward multi-petascale and exascale computing. This paper presents a newly implemented network model for the xSim performance investigation toolkit that is capable of providing simulation support for a variety of HPC network architectures with the appropriate trade-off between simulation scalability and accuracy. The taken approach focuses on a scalable distributed solution with latency and bandwidth restrictions for the simulated network. Different network architectures, such as star, ring, mesh, torus, twisted torus and tree, as well as hierarchical combinations, such as to simulate network-on-chip and network-on-node, are supported. Network traffic congestion modeling is omitted to gain simulation scalability by reducing simulation accuracy.
Architecture exploration for embeddedsystems is becoming an indispensable tool for System-on-Chip designers. This process requires the evaluation of many architectures that are generated during the exploration proces...
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Architecture exploration for embeddedsystems is becoming an indispensable tool for System-on-Chip designers. This process requires the evaluation of many architectures that are generated during the exploration process. The evaluation process has a significant impact on the quality of the results and could consume a substantial amount of CPU time. Accordingly, the evaluation process should provide enough accuracy to guide the optimization process to promising points in the design space in reasonable time. In this paper an efficient approach for performance evaluation of embeddedsystems is proposed. Several cycle-accurate simulations are performed for commercial embedded processors used in our study. The simulation results are used to build Artificial Neural Network (ANN) models with accuracy up to 90% compared to cycle-accurate simulations with a very significant time saving.
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