检索结果-内蒙古大学图书馆

international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Klimke, Jens Themann, Philipp Klas, Christoph Eckstein, Lutz Rhein Westfal TH Aachen Inst Kraftfahrzeuge Ika Adv Driver Assistance Syst D-52074 Aachen Germany

ISBN: (纸本)9781479937707

The use of driver models within advanced driver assistance systems (ADAS) allows anticipating the driving behavior of the vehicle and all traffic participants in the close vicinity. This valuable information could considerably improve the performance as well as the acceptance of ADAS. Consequently complex driver models need to be integrated in embedded systems. This work, first of all, aims to summarize important driver models described in literature. Based upon this a suitable approach to implement a driver model on an embedded system is derived. The model used, focuses on the longitudinal driving and lane change behavior of drivers. The system architecture is derived and optimized for real-time execution. The driver model is analyzed in detailed simulations. Test drives in a small scale naturalistic driving study are used to validate the driver model. This paper defines a standard driver model to be implemented as part of the DESERVE platform within the Artemis project "DESERVE". As embedded automotive hardware the dSpace MicroAutoBox II is used. The paper summarizes approaches and examples to use the generated prediction data in ADAS like ACC.

关键词： Advanced driver assistance systems

来源：评论

学校读者我要写书评

暂无评论

On-chip communication in run-time assembled reconfigurable systems

On-chip communication in run-time assembled reconfigurable s...

引用

6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Sedcole, Pete Cheung, Peter Y. K. Constantinides, George A. Luk, Wayne Univ London Imperial Coll Sci Technol & Med Dept Elect & Elect Engn London England Univ London Imperial Coll Sci Technol & Med Dept Comp London England

ISBN: (纸本)1424401550

embedded systems in Field-Programmable Gate Arrays can be customised and adaptive if assembled from modular components at run time. This paper describes techniques for modelling inter-module channel behaviour based on statistical time division multiplexing. Where modules communicate over shared media, the proposed techniques enable systematic development of on-chip communication infrastructure to support run-time instantiation of components. Our techniques also allow system designers to guarantee that logical communication requirements between the adjunct modules can be satisfied by the infrastructure. An in-depth analysis is presented, and then verified with cycle-accurate simulations for the Sonic-on-chip reconfigurable platform for real-time video applications.

关键词： embedded systems

来源：评论

学校读者我要写书评

暂无评论

A side-channel attack resistant programmable PKC coprocessor for embedded applications

A side-channel attack resistant programmable PKC coprocessor...

引用

international conference on embedded computer systems - architectures, modeling and simulation

作者： Mentens, Nele Sakiyama, Kazuo Batina, Lejla Preneel, Bart Verbauwhede, Ingrid Katholieke Univ Leuven ESAT SCD COSIC Kasteelpk Arenberg 10 B-3001 Heverlee Belgium

ISBN: (纸本)9781424410583

This paper describes the design of a programmable coprocessor for Public Key Cryptography (PKC) on an FPGA. The implementation provides a very broad range of functions together with countermeasures against Side-Channel Analysis (SCA) attacks. The functions are implemented in a hierarchical manner, where all levels are accessible by the user. This makes the coprocessor very flexible and particularly suitable to be used in embedded environments where the border between hardware and software needs to be decided depending on the application. Especially for RSA, the resulting implementation on an XC3S5000 FPGA, from the low-cost Spartan series of XiIinx, shows comparable performance figures compared to the state-of-the-art in PKC coprocessors.

关键词： Public key cryptography

来源：评论

学校读者我要写书评

暂无评论

A Framework for Exploring Alternative Fault-Tolerant Schemes Targeting 3-D Reconfigurable architectures 16

A Framework for Exploring Alternative Fault-Tolerant Schemes...

引用

international conference on embedded computer systems - architectures, modeling and simulation (SAMOS)

作者： Siozios, Kostas Savidis, Ioannis Soudris, Dimitrios Natl Tech Univ Athens Sch Elect & Comp Engn Athens Greece Drexel Univ Dept Elect & Comp Engn Philadelphia PA 19104 USA

ISBN: (纸本)9781509030767

For decades computer architects pursued one primary goal: performance. Transistor scaling has translated into remarkable gains in operating frequency and reduction in power consumption. However, increased complexity from the device to architecture levels impose several new challenges, including a decrease in dependability/reliability due to physical failures. Reconfigurable platforms are highly susceptible to scaling related complexity, typically resulting in higher power consumption as compared to application-specific integrated circuits. The concern becomes far more important in the 3-D integrated circuit (IC) domain as vertically stacked blocks exhibit increased thermal resistance to the heat sink. The degradation in dependability becomes an important design challenge, not only for safety critical systems, but for the majority of architectures. In this paper, a framework used to explore alternative fault-tolerant schemes is proposed that masks the degradation in reliability for 3-D FPGA platforms. simulation results at the RTL level highlight the benefits of the introduced solution, as the maximum operating frequency and power consumption are improved by 33% and 26%, respectively, as compared to similar state-of-the-art solutions.

关键词： Electric power utilization

来源：评论

学校读者我要写书评

暂无评论

HEVC In-Loop Filters GPU Parallelization in embedded systems 15

HEVC In-Loop Filters GPU Parallelization in Embedded Systems

引用

international conference on embedded computer systems architectures modeling and simulation

作者： de Souza, Diego F. Ilic, Aleksandar Roma, Nuno Sousa, Leonel Univ Lisbon IST INESC ID Rua Alves Redol 9 P-1000029 Lisbon Portugal

ISBN: (纸本)9781467373111

The added encoding efficiency and visual quality that is offered by the latest HEVC standard is mostly attained at the cost of a significant increase of the computational complexity at both the encoder and decoder. However, such added complexity greatly compromises the implementation of this standard in computational and energy constrained devices, including embedded systems, mobile and battery supplied devices. To circumvent this limitation, this paper proposes the exploitation of embedded GPU devices already equipping many state of the art SoCs to accelerate the HEVC in-loop filters (i.e. deblocking filter and sample adaptive offset). The presented approaches comprehensively exploit both fine and coarse-grained parallelization opportunities of these filters in an NVIDIA Tegra GPU. According to the conducted experimental evaluation, the proposed approach showed to be a remarkable strategy to satisfy the real-time requirements of the HEVC decoder, being able to filter each Ultra HD 4K intra frame in less than 20 ms (about 50 fps).

关键词： Filters embedded systems High efficiency video coding parallelization GRAPPER PICK UP Graphics Processing Unit ENCODER decoders state of the art complexity classes

来源：评论

学校读者我要写书评

暂无评论

Evaluation of Message Passing Synchronization Algorithms in embedded systems 14

Evaluation of Message Passing Synchronization Algorithms in ...

引用

international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Papadopoulos, Lazaros Walulya, Ivan Tsigas, Philippas Soudris, Dimitrios Barry, Brendan Natl Tech Univ Athens Sch Elect & Comp Engn GR-10682 Athens Greece Chalmers Comp Sci & Engn S-41296 Gothenburg Sweden Movidius Ltd Dublin Ireland

ISBN: (纸本)9781479937707

The constantly increasing computational power of the embedded systems is based on the integration of a large number of cores on a single chip. In such complex platforms, the synchronization of the accesses of the shared memory data is becoming a major issue, since it affects the performance of the whole system. This problem, which is currently a challenge in the embedded systems, has been studied in the High Performance Computing domain, where several message passing algorithms have been designed to efficiently avoid the limitations coming from locking. In this work, inspired from the work on message passing synchronization algorithms in the High Performance Computing domain we design and evaluate a set of synchronization algorithms for multi-core embedded platforms. We compare them with the corresponding lock-based implementations and prove that message passing synchronization algorithms can be efficiently utilized in multi-core embedded systems. By using message passing synchronization instead of lock-based, we managed to reduce the execution time of our benchmark up to 29.6%.

关键词： message passing multi-core embedded systems lock-free

来源：评论

学校读者我要写书评

暂无评论

System modeling and Multicore simulation Using Transactions

System Modeling and Multicore Simulation Using Transactions

引用

international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Anane, Amine Aboulhamid, El Mostapha Savaria, Yvon Univ Montreal Montreal PQ Canada

ISBN: (纸本)9781467322973;9781467322966

With the increasing complexity of digital systems that are becoming more and more parallel, a better abstraction to describe such systems has become a necessity. This paper shows how, by using the powerful mechanism of transactions as a con-currency model, and by taking advantage of. NET introspection and attribute programming capabilities, we were able to develop a system-level modeling and parallel simulation environment. We kept the same concepts to describe the architecture of high-level models, such as modules and communication channels. However, unlike SystemC, the behaviour is no longer described as processes and events but as transactions. We implemented scheduling algorithms in order to enable simulating a transactional models in parallel by taking advantage of a multicore machine. These algorithms take into account the dependency between transactions and the number of cores of the simulation machine. We studied two synchronisation strategies: one using locking and the other using partitioning. An experiment made on a WiFi 802.11a transmitter achieved a speedup of about 1.9 using two threads. With 8 threads, although the workload of individual transactions was not significant, we could reach a 5.1 speedup. When the workload is significant the speedup can reach 6.3.

关键词： systems modelling simulation testing machine Speeding Concurrency Model Workload Multi-core processors Digital system Scheduling algorithms hierarchical models Parallel Lines Simulated Environment THREADS Locking simulating

来源：评论

学校读者我要写书评

暂无评论

Exploration of distributed shared memory architectures for NoC-based multiprocessors

引用

JOURNAL OF systems ARCHITECTURE 2007年第10期53卷 719-732页

作者： Monchiero, Matteo Palermo, Gianluca Silvano, Cristina Villa, Oreste Politecn Milan Dipartimento Elettron & Informaz I-20133 Milan Italy

Multiprocessor system-on-chip (MP-SoC) platforms represent an emerging trend for embedded multimedia applications. To enable MP-SoC platforms, scalable communication-centric interconnect fabrics, such as networks-on-chip (NoCs), have been recently proposed. The shared memory represents one of the key elements in designing MP-SoCs to provide data exchange and synchronization support. This paper focuses on the energy/delay exploration of a distributed shared memory architecture, suitable for low-power on-chip multiprocessors based on NoC. A mechanism is proposed for the data allocation on the distributed shared memory space, dynamically managed by an on-chip hardware memory management unit (HwMMU). Moreover, the exploitation of the HwMMU primitives for the migration, replication, and compaction of shared data is discussed. Experimental results show the impact of different distributed shared memory configurations for a selected set of parallel benchmark applications from the power/-performance perspective. Furthermore, a case study for a graph exploration algorithm is discussed, accounting for the effects of the core mapping and the network topology on energy and performance at the system level. (C) 2007 Elsevier B.V. All rights reserved.

关键词： multiprocessor systems-on-chip network-on-chip design space exploration low-power design

来源：评论

学校读者我要写书评

暂无评论

Exposed Datapath Optimizations for Loop Scheduling 17

Exposed Datapath Optimizations for Loop Scheduling

引用

17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Kultala, Heikki O. Jaaskelainen, Pekka O. IJzerman, Johannes Lehtonen, Lasse K. Viitanen, Timo T. Makitalo, Markku J. Takala, Jarmo H. Tampere Univ Technol Tampere Finland

ISBN: (纸本)9781538634370

Transport Triggered Architecture (TTA) processors allow unique low level compiler optimizations such as software bypassing and operand sharing. Previously, these optimizations have mostly been performed inside single basic blocks, leaving much of their potential unused. In this work, software bypassing and operand sharing are integrated with loop scheduling, allowing optimizations over loop iteration boundaries. This considerably further reduces register file accesses and immediate value transfers on tight loops - in some cases even eliminating all register file accesses from the loop body. In the benchmarked 12 small loops, compared to traditional VLIW-style processors, on average 63% of register file reads and 77% of register file writes could be eliminated. Compared to a compiler which performs these optimizations only inside a basic block, on average 58% of register file reads, 28% of register file writes could be eliminated. The additional register access reductions allow both direct energy savings from fewer register accesses and indirect energy savings by allowing the use of simpler register files with less read and write ports and a simpler interconnect network with less transport buses.

关键词： Registers Program processors Optimization VLIW Processor scheduling computer architecture

来源：评论

学校读者我要写书评

暂无评论

A performance estimation flow for embedded systems with mixed software/hardware modeling

A performance estimation flow for embedded systems with mixe...

引用

2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Kriegel, Joffrey Pegatoquet, Alain Auguin, Michel Broekaert, Florian Thales Communications University of Nice Sophia Antipolis France University of Nice Sophia-Antipolis Sophia-Antipolis France Thales Communications Colombes France

ISBN: (纸本)9781457708008

This paper introduces an Y-chart methodology for performance estimation based on high level models for both application and architecture. As embedded devices are more and more complex, the choice of the best suited architecture not only in terms of processing power but also in power consumption becomes a tedious task. In this context, estimation tools are key components in architecture choice methodology. Obtained results show an error margin of less than 13% of estimation performance for a H.264 video decoder application on two different hardware platforms. © 2011 IEEE.

关键词： embedded systems

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：