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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

共 2831 条记录，以下是151-160 订阅

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Parallelism Extraction in embedded Software for Android Devices 15

Parallelism Extraction in Embedded Software for Android Devi...

引用

international conference on embedded computer systems architectures modeling and simulation

作者： Aguilar, Miguel Angel Eusse, Juan Fernando Ray, Projjol Leupers, Rainer Ascheid, Gerd Sheng, Weihua Sharma, Prashant Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst Aachen Germany Silexica Software Solut GmbH Aachen Germany Samsung R&D Inst Surrey England

ISBN: (纸本)9781467373111

In the last years the presence of embedded devices in everyday life has grown exponentially. The market of these devices imposes conflicting requirements such as cost, performance and energy. The use of Multiprocessor systems on Chip (MPSoCs) is a widely accepted solution to provide a trade-off between these demands. However, programming MPSoCs is still a cumbersome task. Several research efforts have addressed this challenge in two complementary directions: paradigms for parallel programming and tools for parallelism extraction. However, most of these efforts are focused on the high performance domain and they do not consider the characteristics of the underlying platform. In this paper, we present an approach to extract multiple forms of parallelism from sequential C code, which is applied to widespread Android mobile devices. We show the effectiveness of our work by parallelizing relevant embedded benchmarks on a quad-core Nexus 7 tablet.

关键词： Androids embedded software parallelism Synclitism Methyltestosterone embedded device Multiple forms Parallel programming everyday life C CODES

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Secure and authenticated communication in chip-level microcomputer bus systems with tree parity machines

Secure and authenticated communication in chip-level microco...

引用

international conference on embedded computer systems - architectures, modeling and simulation

作者： Muehlbach, Sascha Wallner, Sebastian Hamburg Univ Technol Comp Technol Inst D-2100 Hamburg Germany

ISBN: (纸本)9781424410583

The protection of chip-level microcomputer bus systems in embedded devices is essential to prevent the growing number of hardware hacking attacks. This paper presents an authenticated key exchange and encryption solution in order to ensure chip-level microcomputer bus systems via the Tree Parity Machine Rekeying Architecture (TPMRA). Due to this intention, a scalable TPMRA IP-core is designed and implemented in order to meet variable has performance requirements. It allows the authentication of the bus participants as well as the encryption of chip-to-chip bases from a single primitive. The solution is transparent and easy applicable to an arbitrary microcomputer bus system for embedded devices on the market A proof of concept implementation shows the applicability of the TPMRA in the standardized Advanced Microprocessor Bus Architecture (AMBA) by implementing the IP-core into the peripheral bus-to-bus interface (AHB-APB-bridge). It will be shown that the solution is latency free and can be used in order to protect the ARM bus system with a low hardware overhead considering all AMBA bus features.

关键词： secure bus systems embedded security AMBA bus system-on-chip tree parity machines

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A table-based application-specific prefetch engine for object-oriented embedded systems

A table-based application-specific prefetch engine for objec...

引用

6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Hessabi, Saahin Modarressi, Mehdi Goudarzi, Maziar Javanhemmat, Hani Sharif Univ Technol Dept Comp Engn Tehran Iran

ISBN: (纸本)1424401550

A table-based application-specific data prefetching mechanism is presented in this paper. This mechanism is proposed to improve the performance of the application specific instruction-set processors (ASIP) we develop customized to an object-oriented application. In this approach, we divide the data accesses of a class method into two conditional and unconditional parts. We supply the prefetch engine with the static information about each part to prefetch all data fields of an object required by a class method when the class method is invoked. Effective management of memory access patterns by dividing them based on the method to which they belong and storing the access information of nested loops using a simple structure are the merits of the proposed mechanism. In addition, by adding a prefetch flag to cache blocks, we eliminate a large number of prefetch related tag comparisons. The results show that the proposed mechanism reduces the cache miss ratio and prefetch related tag comparisons on average by 66% and 21%, respectively.

关键词： embedded systems

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Experimental Evaluation of Probabilistic Execution-Time modeling and Analysis Methods for SDF Applications on MPSoCs 19th

Experimental Evaluation of Probabilistic Execution-Time Mode...

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19th international conference on embedded computer systems: architectures, modeling, and simulation (SAMOS)

作者： Stemmer, Ralf Vu, Hai-Dang Gruettner, Kim Le Nours, Sebastien Nebel, Wolfgang Pillement, Sebastien Carl von Ossietzky Univ Oldenburg Oldenburg Germany Univ Nantes IETR UMR CNRS 6164 Nantes France OFFIS eV Oldenburg Germany

ISBN: (纸本)9783030275624;9783030275617

Early validation of software running on multi-processor platforms is fundamental to guarantee that real-time constraints will be fully met. In the domain of timing analysis probabilistic simulation techniques tackle the problem of scalability. However, creation of probabilistic SystemC models remains a difficult task and is not well supported for multiprocessors systems. In this paper we present a modeling workflow that will then be used for an experimental evaluation of probabilistic simulation techniques. For the modeling process a measurement-based approach is proposed to favor the creation of trustful models. The evaluated probabilistic simulation techniques demonstrate good potential to deliver fast yet accurate estimations for multi-processor systems.

关键词： Statistical Model Checking Probabilistic SystemC model Multi processor

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Generating stream based code from plain C

Generating stream based code from plain C

引用

5th international Workshop on embedded computer systems - architectures, modeling, and simulation

作者： Beemster, M van Someren, H Fitzpatrick, L van Royen, R ACE Associated Compiler Expert NL-1011 AB Amsterdam Netherlands

ISBN: (纸本)354026969X

The Stream model is a high level Intermediate Representation that can be mapped to a range of parallel architectures. The Stream model has a limited scope because it is aimed at architectures that reduce the control overhead of programmable hardware to improve the overall computing efficiency. While it has its limitations, the performance critical parts of embedded and media applications can often be compiled to this model. The automatic compilation to Stream programs from C code is demonstrated.

关键词： computer architecture

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Application modeling for Scalable simulation of Massively Parallel systems 17

Application Modeling for Scalable Simulation of Massively Pa...

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2015 IEEE 17th international conference on High Performance Computing and Communications (HPCC)

作者： Anger, Eric Yalamanchili, Sudhakar Dechev, Damian Hendry, Gilbert Wilke, Jeremiah Georgia Inst Technol Atlanta GA 30332 USA Univ Cent Florida Orlando FL USA Sandia Natl Labs Livermore CA USA

ISBN: (纸本)9781479989379

Macro-scale simulation has been advanced as one tool for application-architecture co-design to express operation of exascale systems. These simulations approximate the behavior of system components, trading off accuracy for increased evaluation speed. Application skeletons serve as the vehicle for these simulations, but they require accurately capturing the execution behavior of computation. The complexity of application codes, the heterogeneity of the platforms, and the increasing importance of simulating multiple performance metrics (e. g., execution time, energy) require new modeling techniques. We propose flexible statistical models to increase the fidelity of application simulation at scale. We present performance model validation for several exascale mini-applications that leverage a variety of parallel programming frameworks targeting heterogeneous architectures for both time and energy performance metrics. When paired with these statistical models, application skeletons were simulated on average 12.5 times faster than the original application incurring only 6.08% error, which is 12.5% faster and 33.7% more accurate than baseline models.

关键词： parallel architectures parallel programming power aware computing principal component analysis application-architecture codesign energy performance metrics exascale systems flexible statistical model heterogeneous architectures massively parallel systems parallel programming frameworks performance metrics performance model scalable simulation modeling statistical model time performance metrics Analytical models Computational modeling Data models Hardware Load modeling Predictive models Skeleton Performance metrics statistical models (nuclear) power aware computing Parallel programming Skeletons data models Load modeling Parallel architectures parallel system ANALYSIS MODELS Computational modeling Prediction models bone structure computer hardware simulating

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Risk and Architecture Factors in Digital Exposure Notification 20th

Risk and Architecture Factors in Digital Exposure Notificati...

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20th international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Krishnan, Archanaa S. Yang, Yaling Schaumont, Patrick Virginia Tech Blacksburg VA 24060 USA Worcester Polytech Inst Worcester MA 01609 USA

ISBN: (纸本)9783030609399;9783030609382

To effectively trace the infection spread in a pandemic, a large number of manual contact tracers are required to reach out to all possible contacts of infected users. Exposure notification, a.k.a. digital contact tracing, can supplement manual contact tracing to ease the burden on manual tracers and to digitally obtain accurate contact information. We study how risk emerges in security, privacy, architecture, and technology aspects of exposure notification systems. We provide potential overhead in using Bluetooth-based systems and discuss the architectural support required for other types of systems, and we wrap up with a discussion on architecture aspects to support these solutions.

关键词： Exposure notification Contact tracing Privacy preserving Privacy friendly architectures

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Performance and Energy evaluation of Spark applications on low-power SoC 16

Performance and Energy evaluation of Spark applications on l...

引用

international conference on embedded computer systems - architectures, modeling and simulation (SAMOS)

作者： Kachris, Christoforos Stamelos, Ioannis Soudris, Dimitrios Inst Commun & Comp Syst ICCS NTUA Athens Greece Natl Tech Univ Athens Athens Greece

ISBN: (纸本)9781509030767

Microservers have recently gained attention as low-cost, low power, reduced footprint servers that are mainly based on energy efficient processors such as the ones used in embedded systems. Microservers based on low-power embedded processors are mainly targeting lightweight applications or parallel applications that benefit most from individual low-power servers with sufficient I/O between nodes rather than high performance processors. In this paper we evaluate the mapping of Apache Spark on low-power SoC-based processors. Apache Spark is one of the most widely framework in cloud computing for batch and streaming data analytics. We evaluate the energy efficiency of low-power SoCs that are used in embedded system for the execution of several Spark applications. The performance evaluation shows that low-power SoCs have the potential to offer up to 3x higher energy efficiency compared to high performance processors typically used in data centers.

关键词： embedded systems

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Concurrent Memory Subsystem and Application Optimization for ASIP Design 16

Concurrent Memory Subsystem and Application Optimization for...

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international conference on embedded computer systems - architectures, modeling and simulation (SAMOS)

作者： Eusse, Juan Fernando Fernandez, Francisco Leupers, Rainer Ascheid, Gerd Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst ICE Aachen Germany

ISBN: (纸本)9781509030767

The design of an adequate memory subsystem is critical for the achievement of high performance in application specific and data plane processors. Applications running on such processors must fully exploit the memory hierarchy, so that the gains achieved due to hardware optimization are not invalidated by software inefficiency. This paper presents a framework that vertically integrates the process of memory subsystem design with application optimization and algorithmic exploration. Based on an abstract model, the framework is able to predict the impact that a customization in the memory hierarchy will have on performance, while applying optimization techniques to efficiently utilize it. To perform the aforementioned processes, the tool flow relies on source level information and a novel data model, avoiding the necessity for expensive cycle-accurate simulations. Throughout the evaluation, we show that the framework is capable of predicting memory-related performance metrics with an accuracy of +/- 10%, when compared to simulation. Furthermore, we show that the approach is significantly more efficient than simulation, and can lead to gains in designer's productivity up to a factor of 40x.

关键词： Application programs

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Highly-Parallel Special-Purpose Multicore Architecture for SystemC/TLM simulations 14

Highly-Parallel Special-Purpose Multicore Architecture for S...

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international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Ventroux, N. Peeters, J. Sassolas, T. Hoe, James C. CEA LIST Embedded Comp Lab F-91191 Gif Sur Yvette France Carnegie Mellon Univ Comp Architecture Lab CALCM Pittsburgh PA 15213 USA

ISBN: (纸本)9781479937707

The complexity of SystemC virtual prototyping is continuously increasing. Accelerating RTL/TLM SystemC simulations is essential to control future SoC development cost and time-to-market. In this paper, we present RAVES, a highly-parallel special-purpose multicore architecture that achieves simulation performance more efficiently by parallel execution of light-weight user-level threads on many small cores. We present a design study based on the virtual prototype of RAVES processors running a co-designed custom SystemC kernel. Our evaluation suggests that a 64-core RAVES processor can deliver up to 4.47x more simulation performance than a high-end x86 processor.

关键词： Virtual prototyping Multi-core processors parallel execution PROCESSOR simulating ARCHITECTURE Building construction

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