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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

共 2831 条记录，以下是181-190 订阅

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Adaptive Processor Architecture - Invited Paper

Adaptive Processor Architecture - Invited Paper

引用

international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Huebner, Michael Goehringer, Diana Tradowsky, Carsten Henkel, Joerg Becker, Juergen Ruhr Univ Bochum Chair Embedded Syst Informat Technol ESIT Bochum Germany Karlsruhe Inst Technol KIT Inst Data Proc & Elect IP E Karlsruhe Germany Karlsruhe Inst Technol KIT Inst Informat Proc Technol ITV Karlsruhe Germany Karlsruhe Inst Technol KIT 4Chair Embedded Syst CES Karlsruhe Germany

ISBN: (纸本)9781467322973;9781467322966

This paper introduces a novel methodology to adapt the microarchitecture of a processor at run-time. The goal is to tailor the internal architecture to the requirements of an application and the data to be processed. The latter parameter is normally not known at design time. This leads to the development of more general purpose processors which are capable to handle the data to be processed in any case. With the novel approach which keeps the microarchitecture of a processor flexible, the processor can start as a general purpose device and end up with a specific parameterization, comparable with application specific processor architectures. Furthermore, the increased degree of freedom which is enabled through the approach for a novel quality of processors is described.

关键词： Dynamic and partial processor reconfiguration FPGA internal configuration access port (lCAP) processor adaptation microarchitecture

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On the characterization of data cache vulnerability in high-performance embedded microprocessors

On the characterization of data cache vulnerability in high-...

引用

6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Wang, Shuai Hu, Jie Ziavras, Sotirios G. New Jersey Inst Technol Dept Elect & Comp Engn Newark NJ 07102 USA

ISBN: (纸本)1424401550

Energetic-particle induced soft errors in on-chip cache memories have become a major challenge in designing new generation reliable microprocessors. Uniformly applying conventional protection schemes such as error correcting codes (ECC) to SRAM caches may not be practical where performance, power, and die area are highly constrained, especially for embedded systems. In this paper, we propose to analyze the lifetime behavior of the data cache to identify its temporal vulnerability. For this vulnerability analysis, we develop a new lifetime model. Based on the new lifetime model, we evaluate the effectiveness of several existing schemes in reducing the vulnerability of the data cache. Furthermore, we propose to periodically invalidate clean cache lines to reduce the probability of errors being read in by the CPU. Combined with previously proposed early writeback strategies [1], our schemes achieve a substantially low vulnerability in the data cache, which indicate the necessity of different protection schemes for data items during various phases in their lifetime.

关键词： embedded systems

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Software synthesis in the ESL methodology for multicore embedded systems

Software synthesis in the ESL methodology for multicore embe...

引用

2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Ha, Soonhoi Oh, Hyunok School of Computer Science and Engineering Seoul National University Seoul Korea Republic of Department of Information Systems Hanyang University Seoul Korea Republic of

ISBN: (纸本)9781457708008

Software synthesis from an initial specification model becomes a critical issue in the ESL design methodology as hardware platforms are often reused and more processors are involved in the target platform. Since embedded software has different requirements from general purpose software, there are extensive researches being performed on devising a novel methodology of software synthesis. In this paper, we first summarize some key requirements of embedded software, and then provide an analysis and comparative overview of the state-of-the-art current approaches. Among all the approaches, our proposed programming platform approach pursues an interesting trade-off between static analyzability and expression capability. Based on the survey result, we anticipate the future directions of research in software synthesis techniques. © 2011 IEEE.

关键词： Economic and social effects

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Deploying OpenMP on an embedded Multicore Accelerator

Deploying OpenMP on an Embedded Multicore Accelerator

引用

13th international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Agathos, Spiros N. Dimakopoulos, Vassilios V. Mourelis, Aggelos Papadogiannakis, Alexandros Univ Ioannina Dept Comp Sci GR-45110 Ioannina Greece

ISBN: (纸本)9781479901036

Multiprocessor systems-on-chip (MPSoC) are now considered first-class citizens both in the embedded systems and in the high-performance computing arenas, in the form of specialized or general-purpose accelerators. Programming models for such systems is currently a hot research topic, and as a general rule require deep programmer knowledge of the underlying hardware architecture. In this paper we present the implementation of OpenMP, one of the most intuitive and productive programming models, on the STHORM accelerator. This particular platform provides a shared-memory substrate which OpenMP requires. An innovative feature of our design is the deployment of the OpenMP model both at the host and the fabric sides, in a seamless way, which provides the programmer with a simple but effective interface for offloading and executing OpenMP kernels on the MPSoC. The optimized runtime environment provides full OpenMP support despite its small footprint (less than 10KB for a 16-core cluster) and can sustain close-to-ideal speedups in computationally intensive applications. We detail on design issues we faced along with their solutions, given the limited available resources.

关键词： embedded systems multiprocessing systems shared memory systems system-on-chip

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Automatic Search-Space Compression in System-Level Design Space Exploration Using Deep Generative Models 21st

Automatic Search-Space Compression in System-Level Design Sp...

引用

21st international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Richthammer, Valentina Glass, Michael Ulm Univ Inst Embedded Syst Real Time Syst Ulm Germany

ISBN: (纸本)9783031045806;9783031045790

Major challenges for system-level Design Space Exploration (DSE) include (a) tremendous search-space sizes for modern many-core architectures and networked systems and (b) the preponderance of infeasible solutions in the search space from which no actual implementations can be derived. Since current DSE approaches are not equipped to handle these developments, we propose the integration of deep generative models into DSE to automatically compress large-scale search spaces, thus (I) reducing problem complexity faced by the optimizer while (II) learning a model of feasible solutions to focus the optimization on. The proposed approach is seamlessly integrated into state-of-the-art DSE flows, is complementary to existing search-space pruning techniques, and its potential to improve optimization quality by up to approximate to 66% is demonstrated for a variety of DSE problems.

关键词： Design automation Deep learning Compression

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Verilog-based simulation of hardware support for Data-flow concurrency on Multicore systems

Verilog-based simulation of hardware support for Data-flow c...

引用

13th international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Matheou, George Evripidou, Paraskevas Univ Cyprus Dept Comp Sci Nicosia Cyprus

ISBN: (纸本)9781479901036

Data-Driven Multithreading (DDM) is a threaded data-flow model that schedules threads for execution based on data availability. DDM is utilizing a Thread Scheduling Unit (TSU) for the management of the threads on sequential processors. In this work we present the hardware implementation of the TSU with synthesizable code using the Verilog HDL and its evaluation using the ISim simulator. The evaluation results show that the TSU is able to run at a maximum frequency of 180 MHz and consumes only 5% of the Xilinx Virtex-6 FPGA resources. The initial results obtained in this work will enable us to design an FPGA based DDM multicore chip consisting of several Microblaze cores driven by the TSU. Thus, we will be able to evaluate the performance of the novel threaded data-flow model and have direct comparison with the sequential model on the same hardware.

关键词： data flow computing field programmable gate arrays hardware description languages integrated circuit design microprocessor chips multiprocessing systems performance evaluation processor scheduling

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On STM concurrency control for multicore embedded real-time software

On STM concurrency control for multicore embedded real-time ...

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2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Fahmy, Sherif Ravindran, Binoy ECE Department Virginia Tech Blacksburg VA 24061 United States

ISBN: (纸本)9781457708008

We consider software transactional memory (STM) concurrency control in multicore embedded real-time software. We design an Earliest-Deadline-First (EDF) contention manager (CM) to augment STM's obstruction-free progress semantics. We establish the conditions under which STM/EDF-CM is competitive to lock-based and lock-free synchronization. Our experimental results reveal that STM/EDF-CM outperforms highly concurrent, fine-grain lock-based complex data structures, for which lock-free is often not viable. © 2011 IEEE.

关键词： Concurrency control

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A modular coprocessor architecture for embedded real-time image and video signal processing

引用

international conference on embedded computer systems - architectures, modeling and simulation

作者： Flatt, Holger Hesselbarth, Sebastian Fluegel, Sebastian Pirsch, Peter Leibniz Univ Hannover Inst Mikroelekt Syst Appelstr 4 D-30167 Hannover Germany

ISBN: (纸本)9783540736226

This paper presents a modular coprocessor architecture for embedded real-time image and video signal processing. Applications are separated into high-level and low-level algorithms and mapped onto a RISC and a coprocessor, respectively. The coprocessor comprises an optimized system bus, different application specific processing elements and I/O interfaces. For low volume production or prototyping, the architecture can be mapped onto FPGAs, which allows flexible extension or adaption of the architecture. Depending on the complexity of the coprocessor data paths, frequencies up to 150 MHz have been achieved on a Virtex II-Pro FPGA. Compared to a RISC processor, the performance gain for an SSD algorithm is more than factor 70.

关键词： Video signal processing

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Special session on 'brain-targeted and brain-inspired computing' 14

Special session on 'brain-targeted and brain-inspired comput...

引用

14th international conference on embedded computer systems: architectures, modeling and simulation, SAMOS 2014

作者： Strydis, Christos Erasmus Medical Center Netherlands

ISBN: (纸本)9781479937707

With the advent of diverse enabling technologies, brain-related research has, in recent years, been seriously amplified and has already started yielding impressive findings across various fronts. With respect to computing, these findings can be classified under two major categories: neuroinformatics and brain-inspired computing. By and large, neuroinformatics is the discipline, which conducts brain exploration chiefly through construction and evaluation of computational brain models. Conversely, brain-inspired computing strives to suitably migrate already understood brain mechanisms to non-biological systems in the hopes of building better, cheaper and/or smarter computing machines. Various challenges arise on each side of the spectrum, be it the need for executing increasingly accurate and massive brain models or the need for conceiving improved computer architectures for more efficient, brain-like computations. © 2014 IEEE.

关键词： computer architecture

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Using OpenMP Superscalar for Parallelization of embedded and Consumer Applications

Using OpenMP Superscalar for Parallelization of Embedded and...

引用

international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Andersch, Michael Chi, Chi Ching Juurlink, Ben TU Berlin Embedded Syst Architecture Dept D-10587 Berlin Germany

ISBN: (纸本)9781467322973

In the past years, research and industry have introduced several parallel programming models to simplify the development of parallel applications. A popular class among these models are task-based programming models which proclaim ease-of-use, portability, and high performance. A novel model in this class, OpenMP Superscalar, combines advanced features such as automated runtime dependency resolution, while maintaining simple pragma-based programming for C/C++. OpenMP Superscalar has proven to be effective in leveraging parallelism in HPC workloads. embedded and consumer applications, however, are currently still mainly parallelized using traditional thread-based programming models. In this work, we investigate how effective OpenMP Superscalar is for embedded and consumer applications in terms of usability and performance. To determine the usability of OmpSs, we show in detail how to implement complex parallelization strategies such as ones used in parallel H. 264 decoding. To evaluate the performance we created a collection of ten embedded and consumer benchmarks parallelized in both OmpSs and Pthreads.

关键词： embedding superscalar parallelization Consumers Programming

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