The proceedings contain 50 papers. The topics discussed include: concurrent memory subsystem and application optimization for ASIP design;automatic recognition of computational kernels for platform-dependent code opti...
ISBN:
(纸本)9781509030767
The proceedings contain 50 papers. The topics discussed include: concurrent memory subsystem and application optimization for ASIP design;automatic recognition of computational kernels for platform-dependent code optimizations;Bard: a unified framework for managing soft timing and power constraints;power models supporting energy-efficient co-design on ultra-low power embeddedsystems;real-time tasks and voltage/frequency controller collaboration on low power energy operational systems;a bypass first policy for energy-efficient last level caches;AccuRA: accurate alignment of short reads on scalable reconfigurable accelerators;simulator calibration for accelerator-rich architecture studies;exploring system performance using elastic traces: fast, accurate and portable;CoolSim: statistical techniques to replace cache warming with efficient, virtualized profiling;architecture exploration of a programmable neural network processor for embeddedsystems;design productivity of a high level synthesis compiler versus HDL;a configurable SIMD architecture with explicit datapath for intelligent learning;improving performance in VLIW soft-core processors through software-controlled ScratchPads;and NanoStreams: codesigned microservers for edge analytics in real time.
The proceedings contain 52 papers. The topics discussed include: rethinking memory system design for data-intensive computing;visual processing sparks a new class of processors;experiences in speeding up computer visi...
ISBN:
(纸本)9781467373111
The proceedings contain 52 papers. The topics discussed include: rethinking memory system design for data-intensive computing;visual processing sparks a new class of processors;experiences in speeding up computer vision applications on mobile computing platforms;parallelism extraction in embedded software for android devices? reconfigurable computing for future vision-capable devices;learning-based analytical cross-platform performance prediction;bridging the semantic gap between heterogeneous modeling formalisms and FMI;platform-aware dynamic data type refinement methodology for radix tree data structures;efficient dual-ISA support in a retargetable, asynchronous dynamic binary translator;tervel: a unification of descriptor-based techniques for non-blocking programming;and physical design aware system level synthesis of hardware.
The proceedings contain 48 papers. The topics discussed include: co-design of many-accelerator heterogeneous systems exploiting virtual platforms;robustness analysis of multiprocessor schedules;dynamic-vector executio...
ISBN:
(纸本)9781479937707
The proceedings contain 48 papers. The topics discussed include: co-design of many-accelerator heterogeneous systems exploiting virtual platforms;robustness analysis of multiprocessor schedules;dynamic-vector execution on a general purpose EDGE chip multiprocessor;combining application adaptivity and system-wide resource management on multi-core platforms;resource conscious prefetching for irregular applications in multicores;characterizing communication behavior of dataflow programs using trace analysis;on tokens and signals: bridging the semantic gap between data flow models and hardware implementations;and automated design flow for coarse-grained reconfigurable platforms: an RVC-CAL multi-standard decoder use-case.
An introduction is presented in which the editor discusses various reports within the issue on topics including video coding, embeddedsystems, and dynamic cache adaptation.
An introduction is presented in which the editor discusses various reports within the issue on topics including video coding, embeddedsystems, and dynamic cache adaptation.
The proceedings contain 41 papers. The topics discussed include: parallelizing general histogram application for CUDA architectures;abstraction of polychronous dataflow specifications into mode-automata;modeling pipel...
ISBN:
(纸本)9781479901036
The proceedings contain 41 papers. The topics discussed include: parallelizing general histogram application for CUDA architectures;abstraction of polychronous dataflow specifications into mode-automata;modeling pipelined application with synchronous data flow graphs;parallel implementation of real-time semi-global matching on embedded multi-core architectures;a process-based reconfigurable SystemC module for simulation speedup;lightweight resource estimation model to extend battery life in video playback;energy-aware-task-parallelism for efficient dynamic voltage, and frequency scaling, in CGRAs;an embedded hardware-efficient architecture for real-time cascade support vector machine classification;concurrent multi-level arrays: wait-free extensible hash maps;and fast transaction-level dynamic power consumption modeling in priority preemptive wormhole switching networks on chip.
Based on fundamental physics-based considerations, we introduce the Biaffine Temperature-Voltage power model (BiTV) for SoC systems, which takes the influence of dynamic voltage, frequency, and ambient temperature con...
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ISBN:
(纸本)9783031783760;9783031783777
Based on fundamental physics-based considerations, we introduce the Biaffine Temperature-Voltage power model (BiTV) for SoC systems, which takes the influence of dynamic voltage, frequency, and ambient temperature conditions into account. Using an ARM-Cortex-based AM572x system operating in a temperature-controlled oven, we provide experimental evidence of the validity of the BiTV power model over a significant range of ambient temperatures (25 to 55 degrees C), voltages (0.98 to 1.23 V) and frequencies (100 to 1,500 MHz). These experiments and the BiTV model provide quantitative elements to assess the impact of ambient temperature on systems' performance. Such insights could be of use to system designers and compiler writers, in particular when dealing with embeddedsystems operating in harsh conditions or under energy-critical constraints.
OpenGL SC 2 is Khronos' Graphics API for safety critical systems. However, unlike other Khronos' APIs, available OpenGL SC 2 drivers are only provided by vendors to their customers. This hinders the wide adopt...
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ISBN:
(纸本)9783031783791;9783031783807
OpenGL SC 2 is Khronos' Graphics API for safety critical systems. However, unlike other Khronos' APIs, available OpenGL SC 2 drivers are only provided by vendors to their customers. This hinders the wide adoption of OpenGL SC 2, which is limited to a niche market, since there are very limited available resources for it. In this work, we describe the design and implementation of an Open Source Installable Client Driver (ICD) and offline compiler on top of OpenGL ES 2.0. Thus, our solution enables the development of OpenGL SC 2.0.1 applications on any embedded system, as well as their deployment on selected safety critical platforms, which do not have an available OpenGL SC 2.0.1 driver yet.
Digital microfluidic biochips provide a controlled and miniaturized environment to carry out biochemical protocols in an automated fashion. Software-based simulators are essential tools that aid the design of such pro...
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ISBN:
(数字)9783031783807
ISBN:
(纸本)9783031783791;9783031783807
Digital microfluidic biochips provide a controlled and miniaturized environment to carry out biochemical protocols in an automated fashion. Software-based simulators are essential tools that aid the design of such protocols by enabling users to verify correct execution before targeting the physical biochip. To produce a simulation that is faithful to reality, the fluidic behavior of the droplets and their interaction with the driving electrodes must be taken into account. This paper presents a framework for simulating DMF biochips in a resource-constrained web-based environment. The framework is based on a novel droplet model that uses logic-based calculations to capture fluidic behavior. Thus, enabling to faithfully simulate the movement, merging, and splitting of arbitrary-shaped droplets with a low-computational footprint. The simulation framework also includes modular component models to capture the behavior of sensors and actuators, an event-driven simulation engine, and a graphical user interface. The framework is implemented as a client-side web application and runs in a browser. The evaluation carried out using artificial and real-life test cases shows that the framework can deliver real-time simulations with a high level of fidelity.
Efficient processing architectures for irregular data patterns require vector element addressing with flexible indices. Therefore, state-of-the-art SIMD vector extensions implement gather and scatter instructions for ...
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ISBN:
(纸本)9783031783760;9783031783777
Efficient processing architectures for irregular data patterns require vector element addressing with flexible indices. Therefore, state-of-the-art SIMD vector extensions implement gather and scatter instructions for indexed addressing of data in memory. In vertical vector processors, different data is processed sequentially in parallel lanes and can be exchanged via chaining. This paper proposes an extension of such chaining mechanisms in a vertical vector processor architecture (V2PRO) to flexibly chain not only data but also address offsets between vector lanes. The indirect addressing enables vector access patterns with irregular strides for both register file and memory. The extension has a low hardware overhead of +4.8 % lookup tables and +1.8% registers on a Xilinx Ultrascale+ FPGA. A runtime evaluation for two applications from computer vision, namely Deformable Convolutions and point cloud encoding with PointPillars, demonstrates speedups of at least an order of magnitude with the proposed extension.
Formal verification of embedded system software can profoundly influence both safety and security, and has the potential to alter the development process substantially. However, the complexity of formal verification, ...
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ISBN:
(纸本)9783031783760;9783031783777
Formal verification of embedded system software can profoundly influence both safety and security, and has the potential to alter the development process substantially. However, the complexity of formal verification, along with stringent time-to-market and resource constraints of embeddedsystems, has posed significant barriers to its adoption. Moreover, ensuring the accessibility of formal methods in the design and implementation of embeddedsystems remains a major challenge. In our paper, we evaluate formal methods and demonstrate the accessibility and benefits within a critical area of many industries: IEEE754 floating-point values are widely used and due to their fixed size, they can only approximate real numbers. For the most part, their behavior aligns with programmer expectations;however, certain corner cases exist in which they are susceptible to value cancellation, rounding errors, and deviations from standard mathematical rules. Such discrepancies can be problematic when calculated results diverge from software developer expectations, potentially leading to fatal errors. We propose SafeFloatZone which allows for the identification of safe domains for algorithms utilizing IEEE754 floating-point numbers. The approach is rooted in formal verification, leveraging modern, efficient Satisfiability Modulo Theories (SMT) solvers to deduce preconditions for functions, thereby providing stronger guarantees of correctness. In this work we demonstrate how SafeFloatZone can readily benefit embedded system developers and show that it is transferable to a variety of algorithms based on IEEE754 floating-point numbers.
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