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18th international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Ndour, Genevieve Jost, Tiago Trevisan Molnos, Anca Durand, Yves Tisserand, Arnaud Univ Grenoble Alpes CEA LETI Grenoble France Univ Rennes 1 CNRS INRIA IRISA Rennes France Univ Bretagne Sud CNRS Labs STICC UMR 6285 Lorient France

ISBN: (纸本)9781450364942

Approximate computing techniques have been proposed to decrease the energy consumption or improve the performance of computation. Several designs of approximate arithmetic operators are proposed in the literature, suggesting that the operators' energy can be reduced up to 46%. This paper puts existing work in perspective by studying the impact of these operators in a processor targeting the embedded systems. We augment a RISC-V processor with approximate addition and multiplication that support a variable bit-width in the range of 1 to 16 bits. We investigate the error-energy trade-off for a Sobel filter application. The results indicate that, for an acceptable output image degradation, 7.5% of the energy is saved. We conclude that the benefits of using approximate operators in embedded systems processors, have yet to be proved.

关键词： embedded systems approximate computing operators energy

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A comparative study of different FFT architectures for Software Defined Radio

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international conference on embedded computer systems - architectures, modeling and simulation

作者： Mittal, Shashank Khan, Md. Zafar Ali Srinivas, M. B. Int Inst Informat technol Ctr VLSI & Embedded Syst Technol Hyderabad 500032 Andhra Pradesh India

ISBN: (纸本)9783540736226

Fast Fourier Transform (FFT) is the most basic and essential operation performed in Software Defined Radio (SDR). Thus designing regular, reconfigurable, modular, low hardware and timing-complexity FFT computation block is very important. A single FFT block should be configurable for varying length FFT computation and also for computation of different transforms like Discrete cosine/sine transform (DCT/DST) etc. In this paper, the authors analyze area, timing complexity and noise to signal Ratio (NSR) of Bruun's FFT w.r.t. classical FFT from a SDR perspective. It is shown that architecture of Bruun's FFT is ideally suited for SDR and may be used in preference over classical FFT for most practical cases. A detailed comparison of Bruun's and classical FFT hardware architectures for same NSR is carried out and results of FPGA implementation are discussed.

关键词： computer architecture

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Memory architecture evaluation for video encoding on enhanced embedded processors

Memory architecture evaluation for video encoding on enhance...

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6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Iranpour, Ali Kuchcinski, Krzysztof Lund Univ Dept Comp Sci SE-22100 Lund Sweden

ISBN: (纸本)3540364102

In this paper we investigate the impact of different memory configurations on performance and energy consumption of the video encoding applications, MPEG-4 and H.264. The memory architecture is integrated with SIMD extended embedded processor, proposed in our previous work. We explore both dedicated memories and multilevel cache-architectures and perform exhaustive simulations. The simulations have been conducted using highly optimized proprietary video encoding code for mobile handheld devices. Our simulation results show that the performance improvement of dedicated memories on video encoding applications is not very significant. The multilevel cache-based architecture processes approximately 17 frames/s compared to 1922 frames/s for 512 KB dedicated on-chip zero-wait state memory. Thus it is difficult to justify using dedicated memory for this kind of embedded systems, when energy consumption and cost of implementation are also considered.

关键词： Image coding

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Hardware-Based Synchronization Framework for Heterogeneous RISC/Coprocessor architectures

Hardware-Based Synchronization Framework for Heterogeneous R...

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international conference on embedded computer systems -architectures, modeling and simulation

作者： Flatt, Holger Schmaedecke, Ingo Kaergel, Michael Blume, Holger Pirsch, Peter Leibniz Univ Hannover Inst Microelect Syst D-30167 Hannover Germany

ISBN: (纸本)9781424445011

This paper presents a synchronization framework for parallel computing heterogeneous processing elements, which are controlled by a RISC processor. The communication delay between RISC and processing elements is a key issue if the RISC is not closely attached to the processing elements. Recent synchronization approaches neglect communication delays or require low communication delays. This results in a low synchronization rate between RISC and PEs. In order to overcome this delay, a special hardware-based synchronization approach is proposed that reduces the communication overhead and increases the number of executable tasks per time unit. Further, it supports parallel execution of independent hardware tasks. The approach was evaluated for a modular coprocessor architecture containing several processing elements for image processing tasks. The coarse-grained parallel execution of independent tasks significantly improves the speed of an exemplary application for aerial image based vehicle detection on straight highways.

关键词： Synchronization

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Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems

Combining on-hardware prototyping and high-level simulation ...

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international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Meloni, Paolo Pomata, Sebastiano Raffo, Luigi Piscitelli, Roberta Pimentel, Andy D. Univ Cagliari Dept Elect & Elect Engn I-09124 Cagliari Italy Univ Amsterdam Comp Syst Architecture Grp Amsterdam Netherlands

ISBN: (纸本)9781467322973;9781467322966

Modern heterogeneous multi-processor embedded systems very often expose to the designer a large number of degrees of freedom, related to the application partitioning/mapping and to the component-and system-level architecture composition. The number is even larger when the designer targets systems based on configurable Application Specific Instruction-set Processors, due to the fine customizability of their internal architecture. This poses the need for effective and user-friendly design tools, capable to deal with the extremely wide system-level design space exposed by multi-processor architecture and, at the same time, with an extended variety of processing element architectural configurations, to be evaluated in detail and in reasonable times. As a possible solution, within the MADNESS project [1], an integrated toolset has been proposed, combining the benefits of novel fast FPGA-based prototyping techniques with those provided by high-level simulation. In the toolset, the resulting evaluation platform serves as an underlying layer for a Design Space search algorithm. The paper presents the individual tools included in the toolset and their interaction strategy. The approach is then evaluated with a design space exploration case study, taking as a target application a video compression kernel. The integrated toolset has been used to produce a Pareto front of evaluated system-level configurations.

关键词： DSE gene Designers Multiprocessor Processor architectures PROTOTYPE Video compression Building construction ARCHITECTURE customizability

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Optimal Mapping of Inferior Olive Neuron simulations on the Single-Chip Cloud computer 14

Optimal Mapping of Inferior Olive Neuron Simulations on the ...

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international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Rodopoulos, Dimitrios Chatzikonstantis, Giorgos Pantelopoulos, Andreas Soudris, Dimitrios De Zeeuw, Chris I. Strydis, Christos NTUA MICROprocessors & Digital Syst LAB Athens Greece Erasmus MC Dept Neurosci Rotterdam Netherlands

ISBN: (纸本)9781479937707

Biologically accurate neuron simulations are increasingly important in research related to brain activity. They are computationally intensive and feature data and task parallelism. In this paper, we present a case study for the mapping of a biologically accurate inferior-olive (InfOli), neural cell simulator on an many-core research platform. The Single-Chip Cloud computer (SCC) is an experimental processor created by Intel Labs. The target neurons provide a major input to the cerebellum and are involved in motor skills and space perception. We exploit task-and data-partitioning, scaling the simulation over more than 40,000 neurons. The voltage-and frequency-scaling capabilities of the chip are explored, achieving more than 20% energy savings with negligible performance degradation. Four platform configurations are evaluated and a mapping with balanced workload and constant voltage and frequency is formally derived as optimal.

关键词： Dynamic Frequency and Voltage Scaling Inferior Olive Neurons Pareto Optimal Single-Chip Cloud computer

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A State-Based modeling Approach for Fast Performance Evaluation of embedded System architectures

A State-Based Modeling Approach for Fast Performance Evaluat...

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22nd IEEE international Symposium on Rapid System Prototyping (RSP)

作者： Le Nours, Sebastien Barreteau, Anthony Pasquier, Olivier Univ Nantes IREENA EA1770 Polytech Nantes F-44000 Nantes France

ISBN: (纸本)9781457706608

models are means to assist system architects in the evaluation process of hardware/software architectures and then to cope with the still increasing complexity of embedded systems. Efficient methods are necessary to correctly model system architectures and to make possible early performance evaluation and fast exploration of the design space. In this paper, we present the use of a specific modeling approach to improve evaluation of non-functional properties of embedded systems. The contribution is about a computation method defined to improve modeling of properties used for assessment of architecture performances. This method favors creation of abstract transaction level models and leads to significantly reducing simulation time but still preserving accuracy of results. The benefits of the proposed approach for evaluation of performances of system architectures are highlighted through analysis of two specific case studies.

关键词： Analytical models Computational modeling computer architecture Context modeling embedded systems Load modeling Performance evaluation abstract transaction level models embedded system architectures embedded systems hardware architectures performance evalu

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Design space exploration of reliable networked embedded systems

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JOURNAL OF systems ARCHITECTURE 2007年第10期53卷 751-763页

作者： Streichert, Thilo Glass, Michael Haubelt, Christian Teich, Juergen Univ Erlangen Nurnberg Dept Comp Sci 12 D-91058 Erlangen Germany

In this paper, a new methodology is presented for topology optimization of networked embedded systems as they occur in automotive and avionic systems as well as wireless sensor networks. By introducing a model which is (1) suitable for heterogeneous networks with different communication bandwidths, (2) modeling of routing restrictions, and (3) flexible binding of tasks onto processors, current design issues of networked embedded systems can be investigated. On the basis of this model, the presented methodology firstly allocates the required resources which can be communication links as well as computational nodes and secondly binds the functionality onto the nodes and the data dependencies onto the links such that no routing restrictions will be violated or capacities on communication links will be exceeded. Due to the often error-prone communication in networks, we allow for routing each data dependency over multiple routes in the networks. With this strategy, our methodology is able to increase the reliability of the entire system. This reliability analysis is based on Binary Decision Diagrams (BDDs) and is integrated in our multi-objective design space exploration. By applying Evolutionary Algorithms, we are able to consider multiple objectives simultaneously during the optimization process and allow for a subsequent unbiased decision making. An experimental evaluation as well as a demonstration of a case study from the field of automotive electronics will show the applicability of the presented approach. (C) 2007 Elsevier B.V. All rights reserved.

关键词： topology optimization reliability design space exploration network design

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Trade-offs between voltage scaling and processor shutdown for low-energy embedded multiprocessors

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international conference on embedded computer systems - architectures, modeling and simulation

作者： de Langen, Pepijn Juurlink, Ben Delft Univ Technol Comp Engn Lab Mekelweg 4 NL-2628 CD Delft Netherlands

ISBN: (纸本)9783540736226

When peak performance is unnecessary, Dynamic Voltage Scaling (DVS) can be used to reduce the dynamic power consumption of embedded multiprocessors. In future technologies, however, static power consumption is expected to increase significantly. Then it will be more effective to limit the number of employed processors, and use a combination of DVS and processor shutdown. Scheduling heuristics are presented that determine the best trade-off between these three techniques: DVS, processor shutdown, and finding the optimal number of processors. Experimental results show that our approach reduces the total energy consumption by up to 25% for tight deadlines and by up to 57% for loose deadlines compared to DVS. We also compare the energy consumed by our scheduling algorithm to two lower bounds, and show that our best approach leaves little room for improvement.

关键词： Multiprocessing systems

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A New Generic HLS Approach for Heterogeneous Computing On the Feasibility of High-Level Synthesis in HSA-Compatible systems 18

A New Generic HLS Approach for Heterogeneous Computing On th...

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18th international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Holzinger, Philipp Reichenbach, Marc Fey, Dietmar Friedrich Alexander Univ Erlangen Nuremberg Chair Comp Architecture Dept Comp Sci Erlangen Germany

ISBN: (纸本)9781450364942

Recent advances like deep learning algorithms or virtual reality applications require an amount of computational power in increasingly smaller devices never seen before. Heterogeneous architectures are seen as a solution to this problem, since they provide a significantly better performance per watt. However, their comparatively difficult integration and programming are a major drawback of this solution. The Heterogeneous System Architecture (HSA) Foundation accepted this problem and published a set of specifications to provide a uniform solution for different architectures. This has been successfully applied to GPUs and DSPs, but is insufficiently researched for FPGAs. However, the usage of reconfigurable logic can further increase the efficiency of embedded systems, while the hurdle of integration can be lowered by high-level synthesis (HLS). Therefore, a combination of the HSA specifications with HLS seems worthwhile to increase the heterogeneity and ease the programmability of FPGAs. This paper provides a suitability analysis of the HSA Intermediate Language (HSAIL) for HLS with suggestions for further improvements to the specification as well as an associated proof of concept. The results show that it is indeed possible to build such a hybrid HLS flow based on the HSA standard, where parts of the process can be shared with other classes of accelerators like GPUs. This implies that progress in the GPU sector like the available source languages can faster carry over to FPGAs and improve the general accessibility.

关键词： Heterogeneous System architectures HSA Foundation High-Level Synthesis HLS Hardware Accelerator FPGA

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