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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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Low-Power Application-Specific FFT Processor for LTE Applications

Low-Power Application-Specific FFT Processor for LTE Applica...

引用

13th international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Patyk, Tomasz Guevorkian, David Pitkanen, Teemu Jaaskelainen, Pekka Takala, Jarmo Dolby Labs Wroclaw Poland Nokia Siemens Networks Espoo Finland Tampere Univ Technol FIN-33101 Tampere Finland

ISBN: (纸本)9781479901036

In this paper, we describe a processor architecture tailored to mixed-radix4/2/3 FFT algorithm. The proposed design supports all FFT sizes, namely 128-2048/1536, required by the LTE applications. The processor is based on the Transport Triggered Architecture processor architecture, which was customized with a set of function units, designed especially for the application at hand. The processor has been synthesized on an ASIC technology and both energy-efficiency and performance have been evaluated. The developed processor is programmable but shows energy-efficiency comparable to fixed-function ASIC implementations.

关键词： Fast Fourier Transform Long-Term Evolution Application-Specific Integrated Circuit Parallel architectures

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System architecture modeling of an UWB receiver for wireless sensor network

引用

international conference on embedded computer systems - architectures, modeling and simulation

作者： Lecointre, Aubin Dragomirescu, Daniela Plana, Robert Univ Toulouse 7 Av Colonel Roche F-31077 Toulouse 4 France

ISBN: (纸本)9783540736226

This paper presents a method for system architecture modeling of an IR-UWB (Impulse Radio Ultra WideBand) receiver for sensors networks applications. We expose the way for designing an FPGA (Field Programmable Gate Array) receiver starting from a previous study based on system modeling on Matlab. The proposed receiver architecture is first designed and validated on Matlab, before being implemented, thanks to VHDL language, on a FPGA. Our study shows the interest and the advantages of co-design Matlab-VHDL. We will propose here different IR-UWB receiver architecture depending on the modulation used. We will also introduce in this paper a data-rate and TH-code reconfigurable receiver. Using co-simulation Matlab-VHDL, we have compared three kind of IR-UWB receiver: TH-PPM, TH-OOK, TH-BPAM, with respect to BER/SNR criteria and in the specific context of wireless sensors networks, at high level (Matlab) and hardware level (FPGA-Xilinx).

关键词： systems analysis

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FPGA-based Evaluation Platform for Disaggregated Computing 17

FPGA-based Evaluation Platform for Disaggregated Computing

引用

17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Theodoropoulos, Dimitris Alachiotis, Nikolaos Pnevmatikatos, Dionisios Fdn Res & Technol Hellas FORTH Inst Comp Sci Comp Architecture & VLSI Syst Lab 100 Plastira AveVassilika Vouton Iraklion Greece

ISBN: (纸本)9781538634370

Disaggregated computing aims at overcoming the problem of fixed resource proportionality in existing infrastructures while advancing resource allocation to virtual machines, which is currently restricted by the physical boundaries of a server tray. Organizing resources into large homogeneous pools (e.g., compute, memory, accelerators, etc) enables the demand-driven, fine-grained allocation of resources, effectively leading to improved resource utilization and significant power savings. However, the success of this approach relies on how efficiently the underlying resources are utilized by the software application. To facilitate software development in disaggregated computing environments, we introduce a versatile multi-FPGA evaluation platform that can serve as an early exploration tool for the involved trade-offs and execution alternatives given the application at hand. To increase functionality of the proposed development/evaluation platform, we consider three types of building blocks, namely compute, memory, and accelerator ones, providing the developer with the option to instantiate and interconnect them in proportion to the application demands, thus facilitating both compute- and memory-intensive applications. We have implemented a fully fledged prototype platform, based on three interconnected Zynq boards, and rely on a thin user-level API to allocate compute and memory resources on remote blocks, transfer data, and deploy reconfigurable accelerators. As a case study, we employ one of the Seven Dwarfs of Symbolic Computation, the matrix multiply benchmark.

关键词： Software Hardware Resource management Data transfer computer architecture Field programmable gate arrays Task analysis Field programmable gate arrays task analysis data transmission Resource utilization computer Architecture computer software management of resources computer hardware Platform Physical boundaries Memory Memory

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From Scilab to Multicore embedded systems: Algorithms and Methodologies

From Scilab to Multicore Embedded Systems: Algorithms and Me...

引用

international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Goulas, George Alefragis, Panayiotis Voros, Nikolaos S. Valouxis, Christos Derrien, Steven Menard, Daniel Sentieys, Olivier Gogos, Christos Huebner, Michael Kavvadias, Nikolaos Dimitroulakos, Grigoris Masselos, Kostas Stripf, Timo Oey, Oliver Becker, Juergen Goehringer, Diana Rauwerda, Gerard Sunesen, Kim Kritharidis, Dimitrios Mitas, Nikolaos Technological Educational Institute of Mesolonghi Greece

ISBN: (纸本)9781467322973;9781467322966

While advances in processor architecture continues to increase hardware parallelism, parallel software creation is hard. There is an increasing need for tools and methodologies to narrow the entry gap for non-experts in parallel software development as well as to streamline the work for experts. This paper presents the methodology and algorithms for the creation of parallel software written in Scilab source code for multicore embedded processors in the context of the "Architecture oriented paraLlelization for high performance embedded Multicore systems using scilAb" (ALMA) EU FP7 project. The ALMA parallelization approach in a nutshell attempts to manage the complexity of the task by alternating focus between very localized and holistic view program optimization strategies.

关键词： Software design

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Multi-processor System-on-Chip Design Space Exploration based on Multi-level modeling Techniques

Multi-processor System-on-Chip Design Space Exploration base...

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international conference on embedded computer systems -architectures, modeling and simulation

作者： Mariani, Giovanni Palermo, Gianluca Silvano, Cristina Zaccaria, Vittorio Univ Lugano ALaRI Lugano Switzerland Politecn Milan Dipartimento Elettr & Informat Milan Italy

ISBN: (纸本)9781424445011

Multi-processor systems-on-chip are currently designed by using platform-based synthesis techniques. In this approach, a wide range of platform parameters are tuned to find the best trade-offs in terms of the selected system figures of merit (such as energy, delay and area). This optimization phase is called Design Space Exploration (DSE) and it generally consists of a Multi-Objective Optimization (MOO) problem. The design space of a Multi-processor architecture is too large to be evaluated comprehensively. So far, several heuristic techniques have been proposed to address the MOO problem, but they are characterized by low efficiency to identify the Pareto set. In this paper we propose a methodology for heuristic platform based design based on evolutionary algorithms and multi-level simulation techniques. In particular, we extend the NSGA-II with an approximate neural network meta-model for multiprocessor architectures in order to replace expensive platform simulations with fast meta-model evaluation. The model accuracy and efficiency is improved by exploiting high-level platform simulation techniques. High-level simulation allows us to reduce the overall complexity of the neural network and improving its prediction power. Experimental results show that the proposed techniques is able to reduce the number of simulations needed for the optimization without decreasing the quality of the obtained Pareto set. Results are compared with state of the art techniques to demonstrate that optimization time due to simulation can be sped up by adopting multi-level simulation techniques.(1)

关键词： Heuristic methods

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Exploration of distributed shared memory architectures for NoC-based multiprocessors

Exploration of distributed shared memory architectures for N...

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6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Monchiero, Matteo Palermo, Gianluca Silvano, Cristina Villa, Oreste Politecn Milan Dipartimento Elettron & Informaz I-20133 Milan Italy

ISBN: (纸本)1424401550

Multiprocessor system-on-chip (MP-SoC) platforms represent an emerging trend for embedded multimedia applications. To enable MP-SoC platforms, scalable communication-centric interconnect fabrics, such as networks-on-chip (NoC), have been recently proposed. The shared memory represents one of the key elements in designing MP-SoCs, since its function is to provide data exchange and synchronization support. In this paper, a distributed shared memory architecture has been explored, that is suitable for low-power on-chip multiprocessors based on NoC. In particular, the paper focuses on the energy/delay exploration of on-chip physically distributed and logically shared memory address space for MP-SoCs based on a parameterizable NoC. The data allocation on the physically distributed shared memory space is dynamically managed by an on-chip Hardware Memory Management Unit. Experimental results show the impact of different NoC topologies and distributed shared memory configurations for a selected set of parallel benchmark applications from the power/performance perspective.

关键词： Network-on-chip

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modeling NoC architectures by means of deterministic and stochastic Petri nets

Modeling NoC architectures by means of deterministic and sto...

引用

5th international Workshop on embedded computer systems - architectures, modeling, and simulation

作者： Blume, H von Sydow, T Becker, D Noll, TG RWTH Aachen Univ Chair Elect Engn & Comp Syst D-52062 Aachen Germany

ISBN: (纸本)354026969X

The design of appropriate communication architectures for complex systems-on-Chip (SoC) is a challenging task. One promising alternative to solve these problems are Networks-on-Chip (NoCs). Recently, the application of deterministic and stochastic Petri-Nets (DSPNs) to model on-chip communication has been proven to be an attractive method to evaluate and explore different communication aspects. In this contribution the modeling of basic NoC communication scenarios featuring different processor cores, network topologies and communication schemes is presented. In order to provide a test bed for the verification of modeling results a state-of-the-art FPGA-platform has been utilized. This platform allows to instantiate a soft-core processor network which can be adapted in terms of communication network topologies and communication schemes. It will be shown that DSPN modeling yields good prediction results at low modeling effort. Different DSPN modeling aspects in terms of accuracy and computational effort are discussed.

关键词： computer architecture

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Racetrack Memory-based Encoder/Decoder for Low-Power Interconnect architectures 16

Racetrack Memory-based Encoder/Decoder for Low-Power Interco...

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international conference on embedded computer systems - architectures, modeling and simulation (SAMOS)

作者： Deb, Suntan Ni, Leibin Yu, Hao Chattopadhyay, Anupam Nanyang Technol Univ Sch Comp Sci & Engn Singapore Singapore Nanyang Technol Univ Sch Elect & Elect Engn Singapore Singapore

ISBN: (纸本)9781509030767

Spin-based memory devices offer multiple benefits, like, zero standby power, fast operation speed and high write endurance. Besides for storage applications, Spin Torque Transfer (STT)-based Magnetic Tunnel Junctions (MTJs) and Racetrack Memories (RMs) are also being investigated for logic operations, especially in the context of in-memory computing and neuromorphic architectures. In this paper, we propose spin-based design of encoder/decoder which can be used to reduce the power consumption of interconnect architectures in digital systems. Encoding schemes provide a useful way to reduce the power consumption in interconnects and buses. Realizing these schemes require the use of encoders and decoders. Our proposed design can be reconfigured to implement different encoding schemes. Also, the same design can be reconfigured to function either as encoder or as decoder. Our simulations show a 49.65% reduction in dynamic power consumption for 6-bit proposed reconfigurable design when compared with CMOS-only implementation. Compared to the CMOS implementations, the RM-based non-reconfigurable designs show improvements upto 1.8X and 17.34X in leakage and dynamic power respectively.

关键词： Electric power utilization

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Instruction Scheduling for VLIW Processors Under Variation Scenario

Instruction Scheduling for VLIW Processors Under Variation S...

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international conference on embedded computer systems -architectures, modeling and simulation

作者： Mujadiya, Nayan V. Int Inst Informat Technol Hyderabad Ctr VLSI & Embedded Syst Technol Hyderabad 500032 Andhra Pradesh India

ISBN: (纸本)9781424445011

Process variations in components like adders, multipliers, etc., of different Integer Functional Units (IFUs) in VLIW (Very Long Instruction Word) processors may cause these units to operate at various speeds, resulting in non-uniform latency IFUs. Worst-case techniques to deal with the non-uniform latency IFUs may incur significant performance and/or leakage energy loss. In this work, we propose two process variation-aware compiletime techniques to handle non-uniform latency IFUs. In the first technique, namely 'turn-off', we turn off all the process variation affected high latency IFUs. In the second technique, namely 'on-demand turn-on', we use some of the process variation affected high latency IFUs by turning them on whenever there is a requirement. Our experimental results show that with these techniques, the non-uniform latency IFU can be tackled without much performance penalty. The proposed techniques also achieve significant reduction in leakage energy consumption because of turning off of some of the IFUs.

关键词： Energy dissipation

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GPU Implementation of an Anisotropic Huber-L¹ Dense Optical Flow Algorithm Using OpenCL 15

GPU Implementation of an Anisotropic Huber-<i>L</i><SUP>1</S...

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international conference on embedded computer systems architectures modeling and simulation

作者： Buyukaydin, Duygu Akgun, Toygar ASELSAN Transportat Secur Energy & Automat Syst UGES Busi Ankara Turkey

ISBN: (纸本)9781467373111

Optical flow estimation aims at inferring a dense pixel-wise correspondence field between two images or video frames. It is commonly used in video processing and computer vision applications, including motion-compensated frame processing, extracting temporal features, computing stereo disparity, understanding scene context/dynamics and understanding behavior. Dense optical flow estimation is a computationally complex problem. Fortunately, a wide range of optical flow estimation algorithms are embarrassingly parallel and can efficiently be accelerated on GPUs. In this work we discuss a massively multi-threaded GPU implementation of the anisotropic Huber-L-1 optical flow estimation algorithm using OpenCL framework, which achieves per frame execution time speed-up factors up to almost 300x. Overall algorithm flow, GPU specific implementation details and performance results are presented.

关键词： Optic Flow Traffic estimation GRAPPER PICK UP Graphics Processing Unit Understanding behavior images Dense Videotapes Frame Anisotropy computer vision

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