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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

共 2831 条记录，以下是221-230 订阅

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Access-Aware DRAM Failure-Rate Estimation under Relaxed Refresh Operations 17

Access-Aware DRAM Failure-Rate Estimation under Relaxed Refr...

引用

17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Tovletoglou, Konstantinos Nikolopoulos, Dimitrios S. Karakonstantis, Georgios Queens Univ Belfast Elect Elect Engn & Comp Sci Belfast North Ireland

ISBN: (纸本)9781538634370

In recent years, there has been a growing interest on relaxing the pessimistic DRAM refresh rate due to the incurred power and throughput loss. Undeniably, a critical factor in determining the refresh rate relaxation that can be achieved lies on the degree of the DRAM error-rate deterioration that is incurred and on the amount of estimated errors that can be handled by system mitigation schemes which are mainly being evaluated in simulators. To estimate the DRAM faults under relaxed refresh, the majority of the existing works rely on estimated DRAM failure probability models using only the spatial distribution of the DRAM retention time across the memory cells. We observe that such failure models have neglected the intricate dependence on the memory accesses, which inherently refresh the accessed rows. In this paper, we propose that the intervals between consecutive accesses must also be considered during DRAM simulation. We show that the estimation of the distribution of accesses poses a lot of challenges mainly due to the time consuming full system simulations that are required. To address such challenges, this paper presents one of the first efforts to model the access time-dependent DRAM retention time by developing a fast simulation infrastructure based on binary instrumentation. The basic idea behind the proposed approach lies on the quantification of the time elapsed between consecutive memory accesses on the same row and its relation to the DRAM failure probability, which is then being used for a more accurate fault injection. The introduced overheads of the instrumentation functions are measured during native execution allowing accurate corrections of the time elapsed between consecutive accesses. The efficacy of our framework is being evaluated using various artificial benchmarks. Results show that our scheme helps to limit the misprediction of estimated errors of current error-injection models.

关键词： memory tracing fault injection DRAM memory retention time simulation binary instrumentation

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Black Box ESL Power Estimation for Loosely-Timed TLM Models 16

Black Box ESL Power Estimation for Loosely-Timed TLM Models

引用

international conference on embedded computer systems - architectures, modeling and simulation (SAMOS)

作者： Onnebrink, Gereon Leupers, Rainer Ascheid, Gerd Schuermans, Stefan Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst Aachen Germany Silexica Software Solut GmbH Aachen Germany

ISBN: (纸本)9781509030767

Design space exploration (DSE) at system level needs to cover all parameters and has to find the best trade-off between performance and power of modern heterogeneous multi- and many-processor SoCs (MPSoC). Modelling virtual platforms with SystemC TLM offers fast HW and SW co-design using the loosely-timed (LT) coding style. However, simulations at this high abstraction level lack the capability of providing power estimates in case no insight into the models of the virtual platform is possible. This paper extends a well-proven black box power estimation methodology. The proposed method is capable of estimating the power with high accuracy using fast LT modelling. Two case studies reveal average estimation errors of just 5.1% and 3.5% for the ARM Cortex-A9 on the PandaBoard and the Blackfin 609 DSP on the FinBoard, respectively.

关键词： System-on-chip

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CARROT - A tool for fast and accurate soft error rate estimation

CARROT - A tool for fast and accurate soft error rate estima...

引用

6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Bountas, Dimitrios Stamoulis, Georgios I. Univ Thessaly Dept Comp & Commun Engn Volos 38221 Greece

ISBN: (纸本)3540364102

We present a soft error rate (SER) analysis methodology within a simulation and design environment that covers a broad spectrum of design problems and parameters. Our approach includes modeling of the particle hit at the transistor level, fast Monte-Carlo type simulation to obtain the latching probability of a particle hit on all nodes of the circuit, embedded timing analysis to obtain the latching window, and fine-grained accounting of the electrical masking effects to account for both the effects of scaling and of pulse duration versus the period of the system clock to get an estimate of the maximum SER of the circuit. This approach has been implemented in CARROT and placed under a broad design environment to assess design tradeoffs with SER as a parameter.

关键词： SER combinational circuits simulation

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Learning-based Analytical Cross-Platform Performance Prediction 15

Learning-based Analytical Cross-Platform Performance Predict...

引用

international conference on embedded computer systems architectures modeling and simulation

作者： Zheng, Xinnian Ravikumar, Pradeep John, Lizy K. Gerstlauer, Andreas Univ Texas Austin Austin TX 78712 USA

ISBN: (纸本)9781467373111

As modern processors are becoming increasingly complex, fast and accurate performance prediction is crucial during the early phases of hardware and software co-development. To accurately and efficiently predict the performance of a given software workload is, however, a challenging problem. Traditional cycle-accurate simulation is often too slow, while analytical models are not sufficiently accurate or still require target-specific execution statistics that may be slow or difficult to obtain. In this paper, we propose a novel learning-based approach for synthesizing analytical models that can accurately predict the performance of a workload on a target platform from various performance statistics obtained directly on a host platform using built-in hardware counters. Our learning approach relies on a one-time training phase using a cycle-accurate reference of the chosen target processor. We train our models on over 15,000 program instances from the ACM-ICPC programming contest database, and demonstrate the prediction accuracy on standard benchmark suites. Result show that our approach achieves on average more than 90% accuracy at 160x the speed compared to a cycle-accurate reference simulation.

关键词： performance prediction ANALYSIS MODELS Workload standardized benchmark computer hardware PROCESSOR

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On Brain-inspired Hybrid Topologies for Nano-architectures - A Rent's Rule Approach

On Brain-inspired Hybrid Topologies for Nano-architectures -...

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international conference on embedded computer systems - architectures, modeling and simulation

作者： Beiu, Valeriu Madappuram, Basheer A. M. McGinnity, Martin United Arab Emirates Univ Coll Informat Technol Ctr Neural Inspired Nano Architectures Al Ain U Arab Emirates Univ Ulster Magee Sch Intelligent Syst Coleraine BT52 1SA Londonderry North Ireland

ISBN: (纸本)9781424419852

This paper will start by comparing brain's connectivity (based on different analyses of neurological data) versus well-known network topologies (originally used in massively parallel super-computers), in view of the latest interpretation of Rent's rule. These will reveal that the brain is in very good agreement with Rent's rule average growth rate. With respect to classical network topologies, the crossbar (only for quite small sizes) and the cube connected cycles (for a wider range) look like promising contenders (for the brain), while in fact any network topology falls short of properly mimicking brain's connectivity. That is why, we will go on exploring hybrid (hierarchical) combination of two network topologies, allowing us to identify those (hybrid network topologies) which could closely emulate brain's connectivity (as well as the particular ranges where this is happening).

关键词： Network topology

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Removal of unnecessary context switches from the systemc simulation kernel for fast VP simulation

Removal of unnecessary context switches from the systemc sim...

引用

2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Lu, Kun Müller-Gritschneder, Daniel Schlichtmann, Ulf Institute for Electronic Design Automation Technische Universität München Munich Germany

ISBN: (纸本)9781457708008

Virtual prototypes are widely employed in today's development of embedded hardware and software. To model and simulate the VPs, SystemC has been adopted as a standard language tool. With SystemC, hardware modules and software codes can be modeled as processes. To model concurrency, one process can be suspended and then the SystemC scheduler selects the next process to resume. This is also known as context switching. Context switching can consume a large portion of simulation time and decrease the simulation performance heavily. In this paper, a method is proposed to avoid unnecessary context switches. It achieves this by taking concurrency into account to determine the necessity of a context switch. The case study shows that, by applying the method, performance could be increased significantly without any loss in simulation accuracy. © 2011 IEEE.

关键词： computer software

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Out-Of-Order Execution of Synchronous Data-Flow Networks

Out-Of-Order Execution of Synchronous Data-Flow Networks

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international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Baudisch, Daniel Brandt, Jens Schneider, Klaus Univ Kaiserslautern Dept Comp Sci Embedded Syst Grp D-67663 Kaiserslautern Germany

ISBN: (纸本)9781467322973;9781467322966

Data flow process networks (DPNs) have been introduced as a convenient model of computation for distributed and asynchronous systems since each process node can work independently of the other nodes, i.e. without the need of a global coordination. Synchronous and cyclo-static data flow process networks even allow to derive at compile-time efficient static schedules that allow one to run these systems with an efficient use of available resources, e. g. in embedded systems. Single process nodes of DPNs are stream-based computing devices that transform input streams to uniquely defined corresponding output streams such that single values of the output streams are computed as soon as sufficient input values are available. In this sense, they are related to the execution of an instruction stream by a conventional microprocessor. In this paper, we show how out-of-order execution that has been introduced for the efficient use of multiple functional units in microprocessors can also be used for the implementation of DPNs on multiprocessors. This way, the implementation of DPNs on multiprocessors allows one to optimize the throughput of single process nodes, and as shown by our experiments, also of the entire DPN.

关键词： NAD Legal Executions instruction flow Multiprocessor macroprocessor output stream data flow streams rivers Ganglia

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An Efficient Design Space Exploration Methodology for Multiprocessor SoC architectures based on Response Surface Methods

An Efficient Design Space Exploration Methodology for Multip...

引用

international conference on embedded computer systems - architectures, modeling and simulation

作者： Palermo, Gianluca Silvano, Cristina Zaccaria, Vittorio Politecn Milan Dipartimento Elettron & Informaz I-20133 Milan Italy

ISBN: (纸本)9781424419852

Multi-Processor System on-Chip (MPSoC) architectures are currently designed by using a platform-based approach. In this approach, a wide range of platform parameters must be tuned to find the best trade-offs in terms of the selected figures of merit (such as energy, delay and area). This optimization phase is called Design Space Exploration (DSE) and it generally consists of a Multi-Objective Optimization (MOO) problem. The design space for an MPSoC architecture Is too large to be evaluated comprehensively. So far, several heuristic techniques have been proposed to address the MOO problem for MPSoC, but they are characterized by low efficiency to identify the Pareto front. In this paper, an efficient DSE methodology is proposed leveraging traditional Design of Experiments (DoE) and Response Surface modeling (RSM) techniques. In particular, the DoE phase generates an initial plan of experiments used to create a coarse view or the target design space;a set of RSM techniques are then used to reline the exploration. This process is iteratively repeated until the target criterion (e.g. number of simulations) is satisfied, A set of experimental results are reported to trade-off accuracy and efficiency of the proposed techniques with actual workloads(1).

关键词： Iterative methods

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An analysis of dynamics of CA3b in Hippocampus 14

An analysis of dynamics of CA3b in Hippocampus

引用

international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Keshavarz-Hedayati, B. Dimopoulos, N. J. Babul, A. Univ Victoria Dept Elect & Comp Engn Victoria BC V8W 2Y2 Canada Univ Victoria Dept Phys & Astron Victoria BC V8W 2Y2 Canada

ISBN: (纸本)9781479937707

In this paper we will present a computational model of area CA3b in Hippocampus and through simulations show that this system is capable of sustaining a rhythm without any external input using only a small portion of its population. The model proposed here was devised using the biological data available on CA3. Our simulations have shown that the rhythmic emergent behaviour is sustainable and that we can alter its characteristics (i.e. spectrum) by altering the overall physical characteristics of the network such as the overall size of the structure itself or the extent of the connectivity field.

关键词： Hippocampus external input Biological data simulating dynamics CA3 gene Computational modeling overall sizes Spectra Physical characteristics Rhythms

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Framework for Parameter Analysis of FPGA-based Image Processing architectures 15

Framework for Parameter Analysis of FPGA-based Image Process...

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international conference on embedded computer systems architectures modeling and simulation

作者： Reichenbach, Marc Pfundt, Benjamin Fey, Dietmar Univ Erlangen Nurnberg Comp Architecture Martensstr 3 D-91058 Erlangen Germany

ISBN: (纸本)9781467373111

Image processing algorithms which only work on a local neighbourhood are nearly used in every image processing application. Very often several iterations are performed on a fixed neighbourhood which leads to the description of stencil codes. A promising approach in embedded systems is to use the massively parallel computation power of an FPGA for this kind of algorithms. This not only speeds up processing time, if the FPGA is directly placed inside the image acquisition unit forming a smart camera, but also reduces or even eliminates the PC based hardware which saves space and power. However, most designers begin from scratch when they have to implement stencil computations into smart cameras. This leads to a not fully utilized FPGA because the most efficient usage of the given resources is only secondary alongside functional correctness. Therefore, we are presenting in this paper a framework for stencil code applications which immediately delivers the best architecture regarding prominent resource criteria. An analytical model is used to find an optimized parameter set (degree of parallelism, usage of buffers, etc.) for a highly flexible FPGA implementation. A graphical tool allows to further evaluate the effects of certain parameters. Our results show, that we are able to create an optimized hardware architecture for this application domain.

关键词： stencil computation parallel processing analytical model optimization full buffering

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