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Multidisciplinary Engineering and Applied Science (ICMEAS), international conference on

作者： Edosa Osa Eguagie Evbuomwan Emmanuel. E. Ajari Faculty of Engineering University of Benin Benin City Nigeria Embedded Firmware Engineering SHYFT Power Solutions Lagos Nigeria

ISBN: (纸本)9781665434942

An Autonomous Underwater Vehicle (AUV) is an underwater robot that can operate in six degrees of freedom (6DOF) thereby carrying out preplanned missions via its propulsion and navigation systems which are controlled by an onboard computer. This paper describes the design of an Autonomous Underwater Vehicle, EDYSYS 1. The AUV was first modeled in SolidWorks and thereafter navigation capabilities were tested in a simulation environment using A* algorithm and Robot Operating System (ROS) platform in Unity 3-D game engine. The design for the mechanical, electronics, control and communication subsystems are described as well as operation states.

关键词： Underwater structures Autonomous underwater vehicles Solid modeling Visualization Navigation Computational modeling Operating systems

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A Novel modeling Method of NAND Device 1

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2nd international conference on Advanced Intelligent systems for Sustainable Development, AI2SD 2019

作者： Baghdadi, Hajar Rhofir, Karim Lamhamdi, Mohamed ENSA Khouribga Morocco FST Settat Morocco

ISBN: (数字)9783030366711

ISBN: (纸本)9783030366704

Flash memory has gained tremendous popularity in recent years. A variant of flash, referred to as NAND flash, is widely used in consumer electronics products, such as cell-phones and music players while NAND flash based Solid-State Disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even datacenters. computer architects have recently begun exploring the use NAND flash, from SSD organizations to disk caches and even new flash-based server architectures. In order to study this design space, architects require simulation tools that can provide detailed insights into the behavior of flash memory. This article presents electrical and mathematical models of a NAND device and propose a novel method to resolve the system. Results show that, thanks to the modeling approaches used, the NAND devices are optimized. © Springer Nature Switzerland AG 2020.

关键词： NAND circuits

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Self-Awareness for Autonomous systems

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PROCEEDINGS OF THE IEEE 2020年第7期108卷 971-975页

作者： Dutt, Nikil Regazzoni, Carlo S. Rinner, Bernhard Yao, Xin Nikil Dutt (Fellow IEEE) received the Ph.D. degree from the University of Illinois at Urbana–Champaign Champaign IL USA in 1989.""He is currently a Distinguished Professor of computer science (CS) cognitive sciences and electrical engineering and computer sciences (EECS) with the University of California at Irvine Irvine CA USA. He is a coauthor of seven books. His research interests include embedded systems electronic design automation (EDA) computer architecture distributed systems healthcare Internet of Things (IoT) and brain-inspired architectures and computing.""Dr. Dutt is a Fellow of ACM. He was a recipient of the IFIP Silver Core Award. He has received numerous best paper awards. He serves as the Steering Committee Chair of the IEEE/ACM Embedded Systems Week (ESWEEK). He is also on the steering organizing and program committees of several premier EDA and embedded system design conferences and workshops. He has served on the Editorial Boards for the IEEE Transactions on Very Large Scale Integration (VLSI) Systems and the ACM Transactions on Embedded Computing Systems and also previously served as the Editor-in-Chief (EiC) for the ACM Transactions on Design Automation of Electronic Systems. He served on the Advisory Boards of the IEEE Embedded Systems Letters the ACM Special Interest Group on Embedded Systems the ACM Special Interest Group on Design Automationt and the ACM Transactions on Embedded Computing Systems. Carlo S. Regazzoni (Senior Member IEEE) received the M.S. and Ph.D. degrees in electronic and telecommunications engineering from the University of Genoa Genoa Italy in 1987 and 1992 respectively.""He is currently a Full Professor of cognitive telecommunications systems with the Department of Electrical Electronics and Telecommunication Engineering and Naval Architecture (DITEN) University of Genoa and a Co-Ordinator of the Joint Doctorate on Interactive and Cognitive Environments (JDICE) international Ph.D. course started initially as EU Erasmus Mundus Project and

Autonomous systems are able to make decisions and potentially take actions without direct human intervention, which requires some knowledge about the system and its environment as well as goal-oriented reasoning. In computer systems, one can derive such behavior from the concept of a rational agent with autonomy (“control over its own actions”), reactivity (“react to events from the environment”), proactivity (“act on its own initiative”), and sociality (“interact with other agents”) as fundamental properties \n[1]\n. Autonomous systems will undoubtedly pervade into our everyday lives, and we will find them in a variety of domains and applications including robotics, transportation, health care, communications, and entertainment to name a few. \nThe articles in this month’s special issue cover concepts and fundamentals, architectures and techniques, and applications and case studies in the exciting area of self-awareness in autonomous systems.

关键词： Special issues and sections Autonomous systems Self-aware Robot sensing systems Computational modeling

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Alternate Coupling for Targeted Supply Chain Attacks 15

Alternate Coupling for Targeted Supply Chain Attacks

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15th international conference on Cyber Warfare and Security (ICCWS)

作者： Rohret, David M. Jimenez, Abiud Gen Dynam Informat Technol San Antonio TX 78218 USA Dynetics Inc Huntsville AL 35805 USA

ISBN: (纸本)9781912764532

The authors demonstrate that power-conditioning circuitry on a system's mainboard can be affected using specific power levels, frequencies, and modulation, for an alternative coupling effect to create repeatable results. This effect in-turn triggers embedded code to compromise or exploit targeted systems. Pulse Width Modulation (PWM) circuitry, as part of the power conditioning circuitry, manages power to resources so resource blocks receive sufficient power during heavy usage (i.e. memory during modeling and simulation). To accomplish this task, the PWM maintains a continuous power reading to maintain power consumption efficiency, ensuring an over-voltage condition does not arise. In the event a surge or other external event occurs, the hosts' system bios will react to a surge condition by shutting down or rebooting. Following the reboot or a user-initiated restart, embedded code runs prior to the volatile memory erasure sequence to capture data stored in reserved memory and exfiltrates data using covert communications. computers used for testing were loaded with a payload designed to run on reboot, acquire volatile memory in a file, and starts a network service allowing remote retrieval of the file. For Phase 1 experimentation, an initial state was enabled on each computer to simulate a working environment following each test run, providing researchers the ability to acquire the data in residual memory resulting from an alternative coupling attack. The teams current research has three objectives;to identify if current memory modules in use (DDR3 and DDR4) are susceptible to similar effects identified in early testing, identify covert effects and power requirements using alternative coupling against specific Integrated Circuits (ICs), and covert effects by creating a repeatable 8-bit data stream using alternative coupling.

关键词： Alternative coupling covert communications supply chain attack embedded exploits

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PreSyNC: Hardware realization of the Presynaptic Region of a Biologically Extensive Neuronal Circuitry

PreSyNC: Hardware realization of the Presynaptic Region of a...

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international conference on VLSI Design

作者： Rounak Chatterjee Souradeep Chowdhury Soham Mondal Arnab Raha Janet Paluh Amitava Mukherjee Jadavpur University Kolkata India Memory Solutions Samsung Electronics Co. Ltd. Bangalore India Advanced Architecture Research Intel Edge. AI Intel Corporation Santa Clara USA Colleges of Nanoscale Science and Engineering Nanobioscience SUNY Polytechnic Institute Albany New York USA Adamas University Kolkata India

Spiking Neural Networks (SNN) have gained relevance in recent times, due to their ability to mimic the biological nature to communicate and process sparse asynchronous binary signals in a massively parallel fashion. SNN based neuromorphic hardware exhibits highly desired favourable properties such as low power consumption, fast inference, and event-driven information processing. A recognized challenge of standard SNN neuron models is their limited capabilities in biological applications, such as applying neural networks to study network responses arising from variations pertaining to damage, external influence or disruptions in channel transfer dynamics. This paper presents Pre-Synaptic Neuronal Circuit (PreSyNC), a high performance hardware realization of an input-specific presynaptic region of a generic neuron, without abstraction of primary intra-neuronal parameters. PreSyNC is configured to operate on three precision modes: IEEE 754 single precision, double precision and the recently developed universal number posit number system. The developed hardware design is compared to current standards of SNN neuron models as well as biological models in terms of flexibility, resource efficiency and damage modelling capability. Error margins as low as 0.9 % were obtained and suggest the capability of our hardware in handling applications involving large scale neuron networks. These architectures are synthesized on 45 nm process technology where they all operate at a minimum frequency of approximately 1GHz. The three precision modes are compared based on power, accuracy, and sensitivity handling and are expected to benefit implantation oriented applications such as neural prosthesis and Human-computer Interaction (HCI). The posit-based implementation outperforms the rest of the operating modes in terms of RMS error, while having 26.3 % less area and 25.2 % less power consumption compared to double precision implementation. These new architectures can be expanded in the fut

关键词： Human computer interaction Adaptation models Power demand Neuromorphics Biological system modeling Neurons Hardware

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SHARQ: Software-Defined Hardware-Managed Queues for Tile-Based Manycore architectures 19th

SHARQ: Software-Defined Hardware-Managed Queues for Tile-Bas...

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19th international conference on embedded computer systems: architectures, modeling, and simulation (SAMOS)

作者： Rheindt, Sven Maier, Sebastian Schmaus, Florian Wild, Thomas Schroeder-Preikschat, Wolfgang Herkersdorf, Andreas Tech Univ Munich TUM Arcisstr 21 D-80333 Munich Germany Friedrich Alexander Univ Erlangen Nurnberg FAU Schlosspl 4 D-91054 Erlangen Germany

ISBN: (纸本)9783030275624;9783030275617

The recent trend towards tile-based manycore architectures has helped to tackle the memory wall by physically distributing memories and processing nodes. Distributed operating systems and applications allow to exploit the increased scalability of such architectures, but still face the data-to-task locality challenge. As inter-tile communication, thread synchronization and data transport often impose significant software overhead on such architectures, many applications would benefit from a more efficient and powerful communication primitive with minimal software involvement. We propose software-defined hardware-managed queues for distributed computing architectures that enable efficient inter-tile communication by leveraging application-specific queues with arbitrarily sized elements. To ensure (remote) processing of queued elements, SHARQ introduces the concept of an optional handler task, which is scheduled by hardware on demand. Queue and memory management, intra- and inter-tile data transfer, and handler task invocation are entirely handled by hardware. Only the dynamic queue creation at runtime is performed in software. As an example use-case, we integrated SHARQ into the MPI library. The evaluation with the MPI-based NAS benchmarks shows a reduction in execution time by up to 48% for the communication intense IS kernel in a 4 x 4 tile design on an FPGA platform with a total of 80 LEON3 cores.

关键词： Distributed architectures Hardware accelerator Inter-tile communication Hardware/software codesign MPMC queue NoC

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Evaluation of Electric Vehicle Hosting Capacity in Campus Microgrid Using Monte Carlo simulation

Evaluation of Electric Vehicle Hosting Capacity in Campus Mi...

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international conference on Electrical Machines and systems (ICEMS)

作者： Tae-Han Kim Dam Kim Seung-Il Moon Electrical and Computer Engineering Seoul National University Seoul South Korea Electrical Electronics & Communication Engineering Education Chungnam National University Daejeon South Korea

The electric vehicle and electric vehicle charger market is rapidly growing due to increased interest in carbon free. When a lot of electric vehicles and chargers are penetrated into the distribution network, various problems such as voltage drop may occur. Therefore, it is essential to accurately determine the hosting capacity of electric vehicles from the point of view of system operation. Electric vehicles have a variety of uncertainties, including arrival and departure times, state of charge and selection of charging station. To evaluate the hosting capacity of electric vehicles, these uncertainties must be taken into account. In this paper, load modeling was performed considering the uncertainty of electric vehicle, and the hosting capacity of electric vehicle was evaluated using monte carlo simulation. In addition, load modeling was performed using the actual power consumption data of buildings in Seoul National University. The network was modeled using the parameters of the actually embedded cable. Based on the modeled data, the hosting capacity was evaluated by assuming an electric vehicle based on the actual vehicle access data.

关键词： Uncertainty Monte Carlo methods Power demand Power cables systems operation Voltage Microgrids

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RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM 19th

RRAMSpec: A Design Space Exploration Framework for High Dens...

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19th international conference on embedded computer systems: architectures, modeling, and simulation (SAMOS)

作者： Mathew, Deepak M. Chinazzo, Andre Lucas Weis, Christian Jung, Matthias Giraud, Bastien Vivet, Pascal Levisse, Alexandre Wehn, Norbert Tech Univ Kaiserslautern Kaiserslautern Germany Fraunhofer Inst Expt Software Engn IESE Kaiserslautern Germany Univ Grenoble Alpes CEA LETI MINATEC Campus Grenoble France Ecole Polytech Fed Lausanne Embedded Syst Lab ESL Lausanne Switzerland

ISBN: (纸本)9783030275624;9783030275617

Resistive RAM (RRAM) is a promising emerging Non-Volatile Memory candidate due to its scalability and CMOS compatibility, which enables the fabrication of high density RRAM crossbar arrays in Back-End-Of-Line CMOS processes. Fast and accurate architectural models of RRAM crossbar devices are required to perform system level design space explorations of new Storage Class Memory (SCM) architectures using RRAM e.g. Non-Volatile-DIMM-P (NVDIMM-P). The major challenge in architectural modeling is the trade-off between accuracy and computing intensity. In this paper we present RRAMSpec, an architecture design space exploration framework, which enables fast exploration of various architectural trade-offs in designing high density RRAM devices, at accuracy levels close to circuit level simulators. The framework estimates silicon area, timings, and energy for RRAM devices. It outperforms state-of-the-art RRAM modeling tools by conducting architectural explorations at very high accuracy levels within few seconds of execution time. Our evaluations show various trade-offs in designing RRAM crossbar arrays with respect to array sizes, write time and write energy. Finally we present the influence of technology scaling on different RRAM design trade-offs.

关键词： RRAM ReRAM Crossbar NVM

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Modelling of vertical and ferroelectric junctionless technology for efficient 3D neural network compute cube dedicated to embedded artificial intelligence

Modelling of vertical and ferroelectric junctionless technol...

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international Electron Devices Meeting (IEDM)

作者： C. Maneux C. Mukherjee M. Deng M. Dubourg L. Reveil G. Bordea A. Lecestre G. Larrieu J. Trommer E.T. Breyer S. Slesazeck T. Mikolajick O. Baumgartner M. Karner D. Pirker Z. Stanojevic David Atienza A. Levisse G. Ansaloni A. Poittevin A. Bosio D. Deleruyelle C. Marchand I. O'Connor IMS University of Bordeaux UMR CNRS 5218 Bordeaux INP Talence France LAAS-CNRS UPR 8001 CNRS Université de Toulouse Toulouse France NaMLab gGmbH Dresden Germany Global TCAD Solutions GmbH Vienna Austria EPFL Lausanne Switzerland INL University of Lyon CNRS UMR 5270 Ecole Centrale de Lyon Ecully France

ISBN: (纸本)9781665425735

This paper presents the set of simulation means used to develop the concept of N 2 C 2 (neural network compute cube) based on a vertical transistor technology platform. On the basis of state-of-the-art junctionless nanowire transistors (JLNT), TCAD simulation, compact modeling and EM simulation are leveraged through a Design-Technology Co-Optimization (DTCO) to achieve innovative 3D circuit architectures. Further, System-Technology Co-Optimization (STCO) implications on 3D NN system architecture are explored.

关键词： Solid modeling Three-dimensional displays Computational modeling systems architecture computer architecture Artificial neural networks Transistors

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modeling and simulation of offshore wind farm installation with multi-leveled cgspn approach 30

Modeling and simulation of offshore wind farm installation w...

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30th international Ocean and Polar Engineering conference, ISOPE 2020

作者： Peng, Shengrui Szczerbicka, Helena Becker, Matthias L3S Research Center Leibniz University Hanover HanoverLower Saxony Germany Human-Computer-Interaction Group Leibniz University Hanover HanoverLower Saxony Germany

ISBN: (纸本)9781880653845

This work presents a multi-leveled model based on Colored Generalized Stochastic Petri nets (CGSPN) approach for offshore wind energy installation. The offshore logistics, which describes the organization of offshore operations, is embedded at the root level. The offshore operations, e.g., loading and sailing, are implemented at the secondary level using sub-models. The large scale of the wind turbine components and the ever-changing offshore weather conditions make the scheduling difficult. The aim is to support the project operators and managers in making decisions with the knowledge of the system behavior obtained through stochastic simulation, in which historical weather data measured on the German North Sea from 1958 to 2007 is used. The numerical results show the influence of decision variables, e.g. initial inventory, on a designed offshore wind farm with a size of 80 wind turbines. © 2020 by the international Society of Offshore and Polar Engineers (ISOPE).

关键词： Stochastic systems

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