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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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Reciprocal public sensing for integrated RFID-Sensor Networks

Reciprocal public sensing for integrated RFID-Sensor Network...

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international Wireless Communications and Mobile Computing conference, IWCMC

作者： Fadi M. Al-Turjman Ashraf E. Al-Fagih Waleed M. Alsalih Hossam S. Hassanein School of Computing Queen's University Kingston ONT Canada Information & Computer Science Department King Fahd University of Petroleum and Minerals Dhahran Saudi Arabia Department of Computer Science King Saud University Riyadh Saudi Arabia

Public sensing is an application in which sensory systems embedded in smart devices, vehicles, residential and public spaces form a collective cloud of data sources from which multi-owned access points realize end-users' service requests. This conception can be further extended under the umbrella of integrated RFID-Sensor Networks (RSNs) to include RFID systems. Such a configuration is heterogeneous by nature and faces many challenges in terms of data delivery and resource management. In this paper, we represent a Reciprocal Public Sensing (RPS) scheme for integrated RSN architectures. Our scheme incorporates heuristic solutions for static sensors and mobile data collectors, in addition to a reciprocal agreement for data exchange over the tiers of the proposed architecture adhering to the social welfare of the network as a whole. We provide simulation results showing how RPS outperforms other data delivery schemes in terms of minimizing delay, packet loss, and energy consumption, in addition to prolonging the overall network lifetime.

关键词： Delays Radiofrequency identification Routing Relays Wireless sensor networks Mobile communication

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Demo abstract — Hexacopters for everyone: Online access to advanced robotics platforms for your research

Demo abstract — Hexacopters for everyone: Online access to ...

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IEEE/ACM international conference on Cyber-Physical systems (ICCPS)

作者： Peiyi Chen Sebastian Fischmeister Thomas Reidemeister Yassir Rizwan Steven Waslander Department of Elect. and Computer Engineering University of Waterloo Canada Department of Mechanical and Mechatronics Engineering University of Waterloo Canada

We will present our approach to remote experimentation. The system provides access to a well-maintained, high-fidelity hardware-in-the-loop simulation of a flight-validated hexacopter with an autopilot. The whole system has already received the Special Flight Operations Certificate (SFOC) and was used during several missions such as sensor deployment on icebergs, terrain mapping, and structural integrity checks. The system is easily accessible to remote users, and in active use for research and teaching. Users will be able to connect through a remote connection and gain access to the system. Several scenarios are available which mimic different flight conditions and flight paths. The platform supports research from the operating system up to arbitrary application software and thus enables case studies on software and system design, modeling, programming, validation, and verification, as well as robotic operations, mission planning, and simultaneous localization and mapping.

关键词： Educational institutions Abstracts Mechatronics embedded systems Communities Robot sensing systems

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Approximating Memory-bound Applications on Mobile GPUs

Approximating Memory-bound Applications on Mobile GPUs

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international conference on High Performance Computing & simulation (HPCS)

作者： Daniel Maier Nadjib Mammeri Biagio Cosenza Ben Juurlink Technische Universität Berlin Germany

ISBN: (数字)9781728144849

ISBN: (纸本)9781728144856

Approximate computing techniques are often used to improve the performance of applications that can tolerate some amount of impurity in the calculations or data. In the context of embedded and mobile systems, a broad number of applications have exploited approximation techniques to improve performance and overcome the limited capabilities of the hardware. On such systems, even small performance improvements can be sufficient to meet scheduled requirements such as hard real-time deadlines. We study the approximation of memory-bound applications on mobile GPUs using kernel perforation, an approximation technique that exploits the availability of fast GPU local memory to provide high performance with more accurate results. Using this approximation technique, we approximated six applications and evaluated them on two mobile GPU architectures with very different memory layouts: a Qualcomm Adreno 506 and an ARM Mali T860 MP2. Results show that, even when the local memory is not mapped to dedicated fast memory in hardware, kernel perforation is still capable of 1.25× speedup because of improved memory layout and caching effects. Mobile GPUs with local memory show a speedup of up to 1.38×.

关键词： Kernel Graphics processing units Instruction sets computer architecture Hardware Image reconstruction Resilience

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CMT-bone: A Mini-App for Compressible Multiphase Turbulence simulation Software

CMT-bone: A Mini-App for Compressible Multiphase Turbulence ...

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IEEE international conference on Cluster Computing

作者： Nalini Kumar Mrugesh Sringarpure Tania Banerjee Jason Hackl S. Balachandar Herman Lam Alan George Sanjay Ranka Department of Electrical and Computer Engineering Department of Mechanical and Aerospace Engineering Department of Computer Information Science and Engineering University of Florida Gainesville FL

Designed with the goal of mimicking key features of real HPC workloads, mini-apps have become an important tool for co-design. An investigation of mini-app behavior can provide system designers with insight into the impact of architectures, programming models, and tools on application performance. Mini-apps can also serve as a platform for fast algorithm design space exploration, allowing the application developers to evaluate their design choices before significantly redesigning the application codes. Consequently, it is prudent to develop a mini-app alongside the full blown application it is intended to represent. In this paper, we present CMT-bone a mini-app for the compressible multiphase turbulence (CMT) application, CMT-nek, being developed to extend the physics of the CESAR Nek5000 application code. CMT-bone consists of the most computationally intensive kernels of CMT-nek and the communication operations involved in nearest-neighbor updates and vector reductions. The mini-app represents CMT-nek in its most mature state and going forward it will be developed in parallel with the CMT-nek application to keep pace with key new performance impacting changes. We describe these kernels and discuss the role that CMT-bone has played in enabling interdisciplinary collaboration by allowing application developers to work with computer scientists on performance optimization on current architectures and performance analysis on notional future systems.

关键词： computer architecture Computational modeling Kernel Mathematical model computers Optimization

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Multicube Explorer: An Open Source Framework for Design Space Exploration of Chip Multi-Processors

Multicube Explorer: An Open Source Framework for Design Spac...

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23th international conference on Architecture of Computing systems 2010

作者： V. Zaccaria G. Palermo F. Castro C. Silvano G. Mariani Dipartimento di Elettronica e Informazione - Politecnico di Milano Italy ALaRI - University of Lugano Switzerland

Given the increasing complexity of Chip Multi-Processors (CMPs), a wide range of architecture parameters must be explored at design time to find the best trade-off in terms of multiple competing objectives (such as energy, delay, bandwidth, area, etc.) The design space of the target architecture is huge because of it should consider all possible combinations of each parameter (number of processors, processor issue width, L1 and L2 cache sizes, etc.). In this complex scenario, the multi-objective exploration of the huge design space of next generation CMPs cannot be anymore based on intuition and past experience of the design architects. An Automatic Design Space Exploration methodology is needed to support systematically the exploration and the quantitative comparison of the design alternatives in terms of multiple competing objectives (Pareto analysis). An overall design space exploration framework is needed to combine all optimizations into a global search space with a common interface to the simulation and evaluation tools. Our work focuses on the definition of an automatic multi-objective Design Space Exploration (DSE) framework for tuning Chip Multi-Processor architectures by evaluating a set of metrics (such as energy and delay) for the next generation embedded computing platforms. Multicube Explorer is an interactive open-source framework to enable the designer to automatically explore a design space of configurations for a parameterized architecture for which an executable model (use case simulator) exists. Multicube Explorer is an advanced multi-objective optimization framework which is entirely command-line/script driven and can be re-targeted to any configurable platform by writing a suitable XML design space definition file and providing a configurable simulator.

关键词： Space exploration computer architecture Optimization Program processors Computational modeling Measurement US Department of Energy

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Bipolar ReRAM Based non-volatile flip-flops for low-power architectures

Bipolar ReRAM Based non-volatile flip-flops for low-power ar...

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Annual IEEE Northeast Workshop on Circuits and systems (NEWCAS)

作者： Santhosh Onkaraiah Marina Reyboz Fabien Clermidy Jean-Michel Portal Marc Bocquet Chritophe Muller Hraziia Costin Anghel Amara Amara Cea-leti Minatec Grenoble France IM2NP UMR CNRS 6242 Aix Marseille Université Marseilles France ISEP Paris France

Resistive Random Access Memories (ReRAMs) fabricated in the back-end-of-line are a promising breakthrough for including permanent retention mechanisms in embedded systems. This low-cost solution opens the way to advanced power management schemes. In this paper, we propose novel design architecture of a non-volatile flip-flop based on Bipolar ReRAMs (Bi-RNVFF). Compared to state-of-the-art Data-Retention flip-flop (with Balloon latch), the proposed design is 25% smaller due to 6T structure compared to the 8T structure of Data-Retention flip-flop. Moreover, being non-volatile, the proposed architecture exhibits a zero leakage compared to a Data-Retention Flip-Flop, which consumes ~3.2μW in sleep mode (leakage) for a 10K Flip-Flop design implemented in 22nm FDSOI technology. Our simulation results show that Bi-RNVFF is a true alternative for future “Power-on, Power-off” application adding Non-Volatility without significant burdening of the existing architectures.

关键词： Nonvolatile memory Flip-flops computer architecture Latches Transistors Switches Delay

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MPI+ULT: Overlapping Communication and Computation with User-Level Threads

MPI+ULT: Overlapping Communication and Computation with User...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Huiwei Lu Sangmin Seo Pavan Balaji Mathematics and Computer Science Division Argonne National Laboratory Argonne IL USA

As the core density of future processors keeps increasing, MPI+Threads is becoming a promising programming model for large scale SMP clusters. Generally speaking, hybrid MPI+Threads runtime can largely improve intra-node parallelism and data sharing on shared-memory architectures. However, it does not help much on inter-node communication due to the inefficient integration of existing communication and threading libraries. More specifically, existing MPI+Threads runtime systems use coarse-grained locks to protect their thread safety, which leads to heavy lock contention and limit the scalability of the runtime. While kernel threads are efficient for intra-node parallelism, we found that they are too heavy for computation/communication overlap in an MPI+Threads runtime system. In this paper we propose a new way for asynchronous MPI communication with user-level threads (MPI+ULT). By enabling ULT context switching inside MPI, MPI communication in one ULT can overlap with computation or communication in other ULTs. MPI+ULT can be used for communication hiding in various scenarios, including MPI point-to-point, collective and one-sided calls. We use MPI+ULT in two applications, a high-performance conjugate gradient benchmark and a genome assembly application, to show how MPI+ULT can help effectively hide communication and reduce runtime overhead. Experiments show that our method helps improve the performance of these applications significantly.

关键词： Instruction sets Runtime Kernel Switches Context Computational modeling Message systems

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Accelerating GPGPU architecture simulation 13

Accelerating GPGPU architecture simulation

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Proceedings of the ACM SIGMETRICS/international conference on Measurement and modeling of computer systems

作者： Zhibin Yu Lieven Eeckhout Nilanjan Goswami Tao Li Lizy John Hai Jin Chengzhong Xu Shenzhen Institute of Advanced Technology Chinese Academy of Sciences Shenzhen China ELIS Department Ghent University Ghent Belgium Intelligent Design of Efficient Architectures Lab University of Florida Gainesville USA Department of Electrical and Computer Engineering University of Texas at Austin Austin USA Service Computing Technologies and System Lab/Cluster and Grid Computing Lab HUST Wuhan China Department of Electrical and Computer Engineering Wayne State University Detroit USA

ISBN: (纸本)9781450319003

Recently, graphics processing units (GPUs) have opened up new opportunities for speeding up general-purpose parallel applications due to their massive computational power and up to hundreds of thousands of threads enabled by programming models such as CUDA. However, due to the serial nature of existing micro-architecture simulators, these massively parallel architectures and workloads need to be simulated sequentially. As a result, simulating GPGPU architectures with typical benchmarks and input data sets is extremely time-consuming. This paper addresses the GPGPU architecture simulation challenge by generating miniature, yet representative GPGPU kernels. We first summarize the static characteristics of an existing GPGPU kernel in a profile, and analyze its dynamic behavior using the novel concept of the divergence flow statistics graph (DFSG). We subsequently use a GPGPU kernel synthesizing framework to generate a miniature proxy of the original kernel, which can reduce simulation time significantly. The key idea is to reduce the number of simulated instructions by decreasing per-thread iteration counts of loops. Our experimental results show that our approach can accelerate GPGPU architecture simulation by a factor of 88X on average and up to 589X with an average IPC relative error of 5.6%.

关键词： micro-architecture simulation performance general purpose graphics processing unit (GPGPU)

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simulation of High-Performance Memory Allocators

Simulation of High-Performance Memory Allocators

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Euromicro Symposium on Digital System Design

作者： Jose L. Risco-Martín J. Manuel Colmenar David Atienza J. Ignacio Hidalgo Dept. of Computer Architecture and Automation Complutense University of Madrid Madrid Spain C.E.S. Felipe II Complutense University of Madrid Aranjuez Spain Embedded Systems Laboratory (ESL) EPFL Lausanne Switzerland

Current general-purpose memory allocators do not provide sufficient speed or flexibility for modern high-performance applications. To optimize metrics like performance, memory usage and energy consumption, software engineers often write custom allocators from scratch, which is a difficult and error-prone process. In this paper, we present a flexible and efficient simulator to study Dynamic Memory Managers (DMMs), a composition of one or more memory allocators. This novel approach allows programmers to simulate custom and general DMMs, which can be composed without incurring any additional runtime overhead or additional programming cost. We show that this infrastructure simplifies DMM construction, mainly because the target application does not need to be compiled every time a new DMM must be evaluated. Within a search procedure, the system designer can choose the "best" allocator by simulation for a particular target application. In our evaluation, we show that our scheme will deliver better performance, less memory usage and less energy consumption than single memory allocators.

关键词： Memory management Resource management Energy consumption Dynamic scheduling Software Computational modeling Algorithm design and analysis

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Towards scalable computational models of emotions for autonomous agents

Towards scalable computational models of emotions for autono...

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IEEE international conference on Cognitive Informatics

作者： Xavier González-Olvera Luis-Felipe Rodríguez Department of Computer Science and Design Instituto Tecnológico de Sonora México

ISBN: (纸本)9781509038473

Computational models of emotions (CMEs) are software systems designed to synthesize the mechanisms of the human emotion process. They are included in cognitive agent architectures to endow Autonomous Agents (AAs) with abilities for the evaluation of emotional stimuli, the simulation and expression of emotional feelings, and the development of emotionally driven responses. Although the literature reports several developments of CMEs, there is still a wide range of challenges that remain unaddressed regarding their development process. A key challenge is the development of scalable CMEs whose architecture is capable of implementing novel findings about human emotions. In this paper, we discuss the challenge of scalable CMEs and present a case study that demonstrates how the step by step application of a methodology that takes advantage of psychological and biological findings leads to the design of scalable CMEs. The results of this paper aim at promoting the development of AAs capable of meeting the complex requirements of current applications.

关键词： Computational modeling computer architecture Brain Mood Autonomous agents

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