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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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Real-time benchmark set synthesis based on pWCET estimation and bounded hyper-periods

Real-time benchmark set synthesis based on pWCET estimation ...

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international conference on Circuits, System and simulation (ICCSS)

作者： Ashraf Suyyagh Zeljko Zilic Department of Electrical and Computer Engineering McGill University Montreal QC Canada

ISBN: (纸本)9781538603932

In evaluating performance, schedulability, and energy efficiency metrics for real-time systems, numerous algorithms have been proposed to construct synthetic tasksets for simulation. The resulting taskset characteristics should ideally reflect real workloads while the algorithms generating these tasksets should be efficient. Any experimentation using these tasksets will highly depend on their properties. Current approaches construct the sets by choosing taskset periods and utilisation from statistical distributions and compute the task worst case execution times accordingly. Tasks are generated through timed loops or matrix operations up to the specified task WCET. At times, the taskset hyper-period is bounded to minimise simulation interval through selected assignment of task periods. However, tasks which burn processor cycles through loops and matrix operations do not always reflect realistic task loads. In this paper, we propose a methodology for generating realistic tasksets based on available embedded benchmarks. We extend on previous work and propose new algorithms: CPA-AU/DU (Compute-Propagate-Adjust Ascending/Descending Utilisation) which efficiently pair taskset WCETs with selected discrete periods. Our tasksets have bounded and feasible simulation interval and meet desired total utilisation with minimum digression errors. We also show that our algorithms run in polynomial time.

关键词： Computational modeling Estimation Real-time systems Benchmark testing Hardware Timing Probabilistic logic

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ERSCHED: An Efficient and Reliable Scheduler for Workflows in Multi-Edge systems

ERSCHED: An Efficient and Reliable Scheduler for Workflows i...

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Intelligent Technology and embedded systems (ICITES), international conference on

作者： Linhui Wang Liying Li Yue Zeng Peijin Cong Junlong Zhou School of CSE Nanjing University of Science and Technology Nanjing China National Mobile Communications Research Laboratory Southeast University Nanjing China

ISBN: (数字)9798331506292

ISBN: (纸本)9798331506308

With the rise of edge computing, many users are turning to hosting and running workflow applications in multi-edge environments. This approach can effectively address issues such as resource limitations, low reliability, and high costs that are often encountered in single-edge environments. However, the heterogeneity of resources in multi-edge environments and the differences among edge service providers (in terms of technical architectures, service types, pricing models, etc.) make scheduling tasks in a multi-edge system quite complex. As a result, effectively utilizing multi-edge resources to efficiently and reliably schedule and execute workflows has become a crucial challenge in multi-edge environments. This paper concentrates on the multi-objective workflow scheduling optimization problem when facing reliability constraints in multi-edge environments. We design an efficient and reliable scheduler, namely ERSCHED, for executing workflows in multi-edge systems, with the goal of optimizing makespan and cost simultaneously under reliability constraints. We implement extensive experiments on both real-world and synthetic workflows to validate the efficacy of our scheduler ERSCHED. simulation results show that ERSCHED can derive better makespan-cost trade-off fronts with significantly higher HyperVolume than similar peer methods. The average improvement of HyperVolume realized by ERSCHED is 48.7%.

关键词： Schedules Costs Scheduling algorithms simulation computer architecture Pricing Reliability engineering Turning Service-oriented architecture Sorting

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Integrating Communication Cost into the Utility Accrual Model for the Resource Allocation in Distributed Real-Time systems

Integrating Communication Cost into the Utility Accrual Mode...

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IEEE international conference on embedded and Real-Time Computing systems and Applications (RTCSA)

作者： Xinfa Hu Joseph Y.-T. Leung Department of Computer Science New Jersey Institute of Technology Newark NJ USA

ISBN: (纸本)9780769533490

In distributed real-time systems, both computation and communication are critical factors. The timeliness of activities relies on both the computation and the communication involved in them. Moreover, the timeliness of computation relies on that of communication, and vice versa. This property requires that both computation and communication be integrated into the resource allocation model and that the model be able to capture the interplay between them. Unfortunately, the utility/benefit/value accrual models employed in current distributed real-time systems are constructed solely on computation. They are inadequate for capturing the interplay between computation and communication. This paper extends previous research on utility-based model by proposing a new utility accrual model, which integrates both computation and communication. Most importantly, the interplay between computation and communication is fully characterized in the model. Under the new model, resource managers are guided towards maximizing system-wide utility by exploring the interplay between computation and communication instead of traditional meeting the timing constraint on computation and the deadline of communication separately. To validate the effectiveness of this model, a resource allocation algorithm called CAUASA is developed under it. The performance of CAUASA is compared to that of another resource allocation algorithm that is developed according to existing utility accrual models. simulation results reveal that CAUASA is far superior to its counterpart. Therefore, the new utility accrual model provides a more effective framework for the resource allocation in distributed real-time systems.

关键词： Computational modeling Real time systems Resource management Processor scheduling Timing Scheduling algorithm Finishing

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Large Surface Area Electronic Textiles for Ubiquitous Computing: A System Approach

Large Surface Area Electronic Textiles for Ubiquitous Comput...

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international conference on Mobile and Ubiquitous systems: Networking and Services (MobiQuitous)

作者： David Graumann Giuseppe Raffa Meghan Quirk Braden Sawyer Justin Chong Mark Jones Tom Martin Intel Corporation USA Department of ECE Virginia Polytechnic Institute and State University USA ARCES University of Bologna Italy

Electronic textile research often centers on the concept of introducing electronics to apparel such as shirts jackets, gloves, and health vests. Another less researched concept incorporates electronics into large textile surfaces such as carpets and upholstery. In this paper we explore methods and challenges of building a large surface area electronic textile floor for cooperative mobile device interaction. We systematically construct both a 100 ft by 50 ft textile simulation and a 3 ft by 8 ft working prototype using readily available materials. We introduce the broadly applicable embedded workload of human gait tracking as a means to defining the requirements for the textile physicals, networked computing node, and distributed execution environment subsystems. Through this effort we begin to establish a working model for combining inexpensive electronic textiles with a scalable execution environment that supports mobile device to floor interactions.

关键词： Textiles Ubiquitous computing Floors Buildings Computational modeling Virtual prototyping Humans computer networks Distributed computing embedded computing

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Image coding/reconstruction and matching using a parallel distributed Hebbian architecture

Image coding/reconstruction and matching using a parallel di...

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international Joint conference on Neural Networks (IJCNN)

作者： K.P. Lam Department of Systems Engineering & Engineering Management Chinese University of Hong Kong New Territories Hong Kong China

A high-gain, post-annealing, generalized Hebbian algorithm is proposed and observed to have chaotic learning behavior. It lends itself readily to a highly efficient parallel distributed architecture for principal components computation. The work is extended to a convergence accelerator that uses the chaotic pattern learned during the first few epochs for an iterative weight-change procedure. Applications of using the parallel architecture for image encoding, reconstruction, and matching are described. Successful simulation results in yielding good quality reconstructed images and photo/sketch matching are reported.

关键词： Image coding Image reconstruction Chaos Iterative algorithms computer architecture Concurrent computing Distributed computing Convergence Parallel architectures Computational modeling

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Towards Web Platform for Cloud-Based Virtual Commissioning of IEC 61499 Distributed Automation systems

Towards Web Platform for Cloud-Based Virtual Commissioning o...

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international conference on Emerging Technologies and Factory Automation (ETFA)

作者： Tuojian Lyu Tung Nguyen Roman Rumiantsev Mikhail Kolesnikov Hansani Perera Udayanto Dwi Atmojo Valeriy Vyatkin Department of Electrical Engineering and Automation Aalto University Espoo Finland Department of Computer Science Computer and Space Engineering Luleå Tekniska Universitet Sweden

ISBN: (数字)9798350361230

ISBN: (纸本)9798350361247

In this paper, we propose a cloud-based virtual commissioning Web platform for IEC 61499 compliant distributed automation systems that support Create-Read-Update-Delete operations for SoftPLC containers from various versions and provide a remote engineering workstation with an embedded web Integrated Development Environment (IDE), Human Machine Interface (HMI), and 3D simulation models. A water tank use case demonstrates the platform's flexibility, enabling control software testing entirely via a Web browser without local installations.

关键词： Water Software testing Cloud computing Solid modeling Three-dimensional displays Human-machine systems Storage management Workstations IEC Standards Manufacturing automation

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Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors

Performance comparison of single-precision SPICE Model-Evalu...

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international conference on Field Programmable Logic and Applications

作者： Nachiket Kapre Andre DeHon Computer Science California Institute of Technology Pasadena CA USA Electrical and Systems Engineering University of Pennsylvania Philadelphia PA USA

Automated code generation and performance tuning techniques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor organizations for data-parallel, floating-point computation in SPICE model-evaluation. Our Verilog AMS compiler produces code for parallel evaluation of non-linear circuit models suitable for use in SPICE simulations where the same model is evaluated several times for all the devices in the circuit. Our compiler uses architecture specific parallelization strategies (OpenMP for multi-core, PThreads for Cell, CUDA for GPU, statically scheduled VLIW for FPGA) when producing code for these different architectures. We automatically explore different implementation configurations (e.g. unroll factor, vector length) using our performance-tuner to identify the best possible configuration for each architecture. We demonstrate speedups of 3- 182times for a Xilinx Virtex5 LX 330T, 1.3-33times for an IBM Cell, and 3-131times for an NVIDIA 9600 GT GPU over a 3 GHz Intel Xeon 5160 implementation for a variety of single-precision device models.

关键词： SPICE Field programmable gate arrays Multicore processing computer architecture Computational modeling Circuit optimization Concurrent computing Hardware design languages Circuit simulation Scheduling

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modeling and Performance Analysis of Beyond 3G Integrated Wireless Networks

Modeling and Performance Analysis of Beyond 3G Integrated Wi...

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IEEE international conference on Communications (ICC)

作者： Ahmed H. Zahran Ben Liang Aladdin Saleh Department of Electrical and Computer Engineering University of Toronto Canada Wireless Technology Bell Canada Limited Canada

Next-generation wireless networking is evolving towards a multi-service heterogeneous paradigm that converges different pervasive access technologies and provides a large set of novel revenue generating applications. Hence, system complexity increases due to its embedded heterogeneity, which can not be accounted by the existing modeling and performance evaluation techniques. Consequently, the development of new modeling approaches becomes as a crucial requirement for proper system design and performance evaluation. This paper presents a novel mobility model for a two-tier integrated wireless system using a new modeling approach that accommodates the aforementioned complexity. Additionally, a novel session model is developed as an adapted version of the proposed mobility model. These models use phase-type distributions that are known to approximate any generic probability laws. Using the proposed session model, a novel generic analytical framework is developed to obtain several salient performance metrics such as network utilization times and handoff rates. simulation and analysis results prove the proposed model validity and demonstrate the accuracy of the novel modeling approach when compared with traditional modeling techniques.

关键词： Performance analysis Wireless networks Wireless LAN Cathode ray tubes Land mobile radio cellular systems Next generation networking Measurement Analytical models Quality of service Application software

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Diagnosis of sensor networks

Diagnosis of sensor networks

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IEEE international conference on Communications (ICC)

作者： C. Jaikaeo C. Srisathapornphat C.-C. Shen Computer and Information Sciences University of Delaware Newark DE USA

As sensor nodes are embedded into physical environments and becoming integral parts of our daily lives, sensor networks will become the important nerve systems that monitor and actuate our physical environments. We define the process of monitoring the status of a sensor network and figuring out the problematic sensor nodes sensor network diagnosis. However, the high sensor node-to-manager ratio makes it extremely difficult to pay special attention to any individual node. In addition, the response implosion problem, which occurs when a high volume of incoming replies triggered by diagnosis queries cause the central diagnosing node to become a bottleneck, is one major obstacle to be overcome. We describe approaches to addressing the response implosion problem in sensor network diagnosis. We also present simulation experiments on the performance of these approaches, and discuss presentation schemes for diagnostic results.

关键词： Sensor phenomena and characterization Sensor systems computerized monitoring Computational modeling Wireless communication computer network management Biomedical monitoring Image sensors Humans Biomedical imaging

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Mutation Analysis and Model Checking Guided Test Generation for SoC Run-Time Monitors

Mutation Analysis and Model Checking Guided Test Generation ...

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international conference on VLSI Design

作者： Suriya Srinivasan Ranga Vemuri Electrical and Computer Engineering Department University of Cincinnati Cincinnati OH USA

Security verification and validation both before and after fabrication emerged as an important concern in the design of systems-on-chip (SoC) architectures. Assertion-based formal methods are widely for pre-fabrication verification of SoC designs. Assertions denoting the SoC's security policies are formally verified to check if the design satisfies these specifications. In addition, several researchers have proposed to migrate these assertions into silicon as run-time monitors to facilitate continuous run-time security monitoring. However, due to limited observability, post-silicon validation of these run-time monitors requires input sequences that are specifically targeted to testing these monitors. In this paper, we present a methodology to produce a variety of tests for assertion-based run-time monitors. Given temporal logic assertions which denote security properties of an SoC design, the methodology consists of the following steps: (1) introduce mutations into the SoC design model to cause assertion failures, (2) use model checking to produce counterexample traces, (3) generate alternative and longer counterexamples for a mutant, with the help of novel algorithms to enhance the test suite, (4) extract test programs from the counterexamples and winnow repetitive test cases, (5) investigate the code coverage of the design with the help of these multiple tests. This methodology can be used to generate a large number of tests for each security monitor, enhancing the design's code coverage. We demonstrate the methodology for a large OpenRISC-1200 based SoC design. We show the effectiveness of the generated test programs via simulation and FPGA-based emulation.

关键词： Fabrication Codes Model checking Very large scale integration Silicon Security Test pattern generators

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