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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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Real-time scheduling of CPU-bound and I/O-bound processes

Real-time scheduling of CPU-bound and I/O-bound processes

引用

IEEE international conference on embedded and Real-Time Computing systems and Applications (RTCSA)

作者： Jun Wu Tei-Wei Kuo Department of Computer Science and Information Engineering National Chung Cheng University Chiayi Taiwan

The real-time resource allocation problem has been an active research topic in recent decades. Although the real-time resource allocation problem has been analyzed for different architectural assumptions, various simplified assumptions on resource synchronization are made for real-time process scheduling. Little work has been done in scheduling processes which may requests services from other independent subsystems. This paper explores real-time scheduling of processes which may share non-preemptible resources on the same processor and, at the same time, request services from other independent subsystems. In particular we consider the scheduling of real-time processes which may stop to wait for disk I/O without releasing any locked semaphores. We propose to revise the definition of priority ceiling and propose a resource synchronization mechanism to meet the deadline requirements of real-time CPU-bound and I/O-bound processes. The capability of the proposed methodology is verified by a series of simulation experiments on different workloads of CPU-bound and I/O-bound processes, for which we have some encouraging experimental results.

关键词： Processor scheduling Optimal scheduling Resource management Scheduling algorithm Timing Real time systems Protocols computer science Councils Computational modeling

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Synthesis of DSP soft real-time multiprocessor systems-on-silicon

Synthesis of DSP soft real-time multiprocessor systems-on-si...

引用

international conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： D. Kirovski M. Potkonjak Computer Science Department University of California Los Angeles CA USA

The convergence of applications (Internet and embedded applications) and technology (reuse and very high integration level) trends resulted in a strong need for design of soft real-time DSP systems-on-silicon. We developed a new hierarchical modular approach for synthesis of area efficient soft real-time DSP systems-on-silicon. This synthesis strategy employs a number of optimization intensive scheduling, performance monitoring, and allocation steps. The backbone of the optimization approach is a novel online scheduling algorithm which uses meta-algorithmic techniques for on-the-fly heuristic selection and parameter tuning. Resource allocation refers to a predetermined lower-bound system performance, to perform a branch-and-bound resource allocation search for an area-efficient multiprocessor configuration where each processor has local instruction and data cache. In order to bridge the gap between the profiling, modeling, and synthesis tools of the two traditionally independent synthesis domains (architecture and CAD), we develop a new synthesis and evaluation platform which integrates the existing modeling, profiling, and simulation tools with the new developed system-level synthesis tools. The effectiveness of the approach is demonstrated on the industrial strength MediaBench benchmark suite.

关键词： Digital signal processing Real time systems Multiprocessing systems Resource management Internet Job shop scheduling Monitoring Spine Scheduling algorithm System performance

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Describing software architectures by system structure and properties 22

Describing software architectures by system structure and pr...

引用

22nd Annual international computer Software and Applications conference

作者： Eixelsberger, W Gall, H ABB Corp Res ITC Dept N-1361 Billingstad Norway

ISBN: (纸本)0818685859

To support architecture-based development, different modeling notations and languages, so-called architecture description languages (ADLs) have been designed. To be of help in the development process, software architectures must be described in a complete and consistent manner but without being overloaded with information provided to the system stakeholders. Current architecture description languages provide information about software architectures in a domain independent way. This may lead to inappropriate and incomplete descriptions of software architectures. In this paper, we introduce a flexible and extensible language called Architecture Structure Description Language (ASDL) developed for describing structural aspects of software architectures and their properties. We thereby focus on the domain of embedded real-rime systems that have to meet certain timing and safety constraints. The language was developed in an architecture recovery, process of a real-world Train Control System (TCS) and has been used to describe and reason about TCS's architecture.

关键词： software architecture re-engineering architecture recovery architectural properties

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ACM SIGPLAN Workshop on Languages, Compilers, and Tools for embedded systems, LCTES 1998

ACM SIGPLAN Workshop on Languages, Compilers, and Tools for ...

引用

4th ACM SIGPLAN Workshop on Languages, Compilers, and Tools for embedded systems, LCTES 1998

ISBN: (纸本)354065075X

The proceedings contain 21 papers. The special focus in this conference is on Languages, Compilers, and Tools for embedded systems. The topics include: Integrating path and timing analysis using instruction-level simulation techniques;on predicting data cache behavior for real-time systems;automatic accurate time-bound analysis for high-level languages;extending RT-linux to support flexible hard real-time systems with optional components;limited preemptible scheduling to embrace cache memory in real-time systems;a uniform reliable multicast protocol with guaranteed response times;a tool to assist in fine-tuning and debugging embedded real-time systems;debugging distributed implementations of modal process systems;turboj, a java bytecode-to-native compiler;cache-sensitive pre-runtime scheduling;priority assignment for embedded reactive real-time systems;mapping an embedded hard real-time systems SDL specification to an analyzable task network;efficient user-level I/O in the ARX real-time operating system;machine descriptions to build tools for embedded systems;non-local instruction scheduling with limited code growth;an efficient data partitioning method for limited memory embedded systems;a design environment for counterflow pipeline synthesis;end-to-end optimization in heterogeneous distributed real-time systems;using UML for modeling complex real-time systems and evaluating ASIC, DSP, and RISC architectures for embedded applications.

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Parallel architectures and Compilation Techniques - conference Proceedings, PACT

Parallel Architectures and Compilation Techniques - Conferen...

引用

1998 international conference on Parallel architectures and Compilation Techniques, PACT 1998

ISBN: (纸本)0818685913

The proceedings contain 50 papers. The topics discussed include: integrating loop and data transformations for global optimization;optical versus electronic bus for address-transactions in future SMP architectures;Origin 2000 design enhancements for communication intensive applications;design study of shared memory in VLIW video signal processors;exploiting fine- and coarse-grain parallelism in embedded programs;eliminating bottlenecks on parallel systems using adaptive objects;Athapascan-1: on-line building data flow graph in a parallel language;code generation in the polytope model;capturing the effects of code improving transformations;fast, accurate and flexible data locality analysis;superscalar execution with direct data forwarding;a fast interrupt handling scheme for VLIW processors;efficacy and performance impact of value prediction;a fast algorithm for scheduling time-constrained instructions on processors with ILP;exploiting method-level parallelism in single-threaded java programs;improving static branch prediction in a compiler;static methods in hybrid branch prediction;Madeleine: an efficient and portable communication interface for RPC-based multithreaded environments;breaking the barriers: two models for MPI programming;performance of message-passing systems using a zero-copy communication protocol;dynamic hammock predication for non-predicated instruction set architectures;and an direct-execution framework for fast and accurate simulation of superscalar processors.

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Efficient modeling of memory arrays in symbolic ternary simulation 4th

Efficient modeling of memory arrays in symbolic ternary simu...

引用

4th international conference on Tools and Algorithms for the Construction and Analysis of systems, TACAS 1998, Held as Part of the Joint European conferences on Theory and Practice of Software, ETAPS 1998

作者： Velev, Miroslav N. Bryant, Randal E. Department of Electrical and Computer Engineering United States School of Computer Science Carnegie Mellon University PittsburghPA15213 United States

ISBN: (纸本)3540643567

This paper enables symbolic ternary simulation of systems with large embedded memories. Each memory array is replaced with a behavioral model, where the number of symbolic variables used to characterize the initial state of the memory is proportional to the number of distinct symbolic memory locations accessed. The behavioral model provides a conservative approximation of the replaced memory array, while allowing the address and control inputs of the memory to accept symbolic ternary values. Memory state is represented by a list of entries encoding the sequence of updates of symbolic addresses with symbolic data. The list interacts with the rest of the circuit by means of a software interface developed as part of the symbolic simulation engine. This memory model was incorporated into our verification tool based on Symbolic Trajectory Evaluation. Experimental results show that the new model significantly outperforms the transistor level memory model when verifying a simple pipelined data path. © Springer-Verlag Berlin Heidelberg 1998.

关键词： computer software

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4th international conference on Intelligent Tutoring systems, ITS 1998

4th International Conference on Intelligent Tutoring Systems...

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4th international conference on Intelligent Tutoring systems, ITS 1998

ISBN: (纸本)3540647708

The proceedings contain 98 papers. The special focus in this conference is on architectures for ITS, Design and Interface Issues. The topics include: Instructional applications of ACT;teaching expertise and learning environments;the evolution of intelligent tutoring systems research;my knowledge of knowledge;cognitive tools to support discovery learning;using a learning agent with a student model;model-based explanations in simulation-based training;towards an intelligent tutoring system for situation awareness training in complex, dynamic environments;embedded training for complex information systems;macro-definitions, a basic component for interoperability between ILEs at the knowledge level;modelling the knowledge-based components of a learning environment within the task/method paradigm;striving for better learning efficiency in stat lady;habitable 3D learning environments for situated learning;motivation diagnosis in intelligent tutoring systems;some reasons why learning science is hard;a bottom-up approach to multimedia teachware;the authoring assistant;explanatory mechanisms for intelligent tutoring systems;uncorking the bottleneck in knowledge elicitation and organization;component-based construction of a science learning space;promoting effective peer interaction in an intelligent collaborative learning system;using induction to generate feedback in simulation based discovery learning environments;an interactive graphical tool for efficient cooperative task acquisition based on monaco-T model;initial requirements of a lessons learned centred corporate memory;an ITS for dutch punctuation and cognitive task analysis in service of intelligent tutoring system design.

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10 Workshops Held in Conjunction with the 12th international Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, IPPS/SPDP 1998

引用

10 Workshops held in conjunction with 12th international Parallel Symposium and 9th Symposium on Parallel and Distributed Processing, IPPS/SPDP 1998

ISBN: (纸本)3540643591

The proceedings contain 118 papers. The special focus in this conference is on Parallel and Distributed Processing. The topics include: Dynamic reconfiguration of a PMMLA for high-throughput applications;a parallel algorithm for minimum cost path computation on polymorphic processor array;a performance modeling and analysis environment for reconfigurable computers;an integrated partitioning and synthesis system for dynamically reconfigurabte multi-FPGA architectures;temporal partioning for partially-reconfigurable-field-programmable gate;a java development and runtime environment for reconfigurable computing;synthesizing reconfigurable sequential machines using tabular models;evaluation of a low-power reconfigurable DSP architecture;a reconfigurable hardware-monitor for communication analysis in distributed real-time systems;a mathematical benefit analysis of context switching reconfigurable computing;a configurable computing approach towards real-time target tracking;hardware reconfigurable neural networks;a simulator for the reconfigurable mesh architecture;processor architectures for circuit emulation;an empirical comparison of runtime systems for conservative parallel simulation;synchronizing operations on multiple objects;migration and rollback transparency for arbitrary distributed applications in workstation clusters;a topology based approach to coordinated multicast operations;a parallel evolutionary algorithm for the vehicle routing problem with heterogeneous fleet;artificial neural networks on reconfigurable meshes;a molecular quasi-random model of computations applied to evaluate collective intelligence;replicated shared object model for edge detection with spiral architecture and scheduling tasks of a parallel program in two-processor systems with use of cellular automata.

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Cycle-based simulation on loosely-coupled systems

Cycle-based simulation on loosely-coupled systems

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Annual IEEE international conference and Exhibit ASIC

作者： D. Dohler K. Hering W.G. Spruth S/390 Development IBM Germany Laboratory Boblingen Germany Department of Computer Science University of Leipzig Leipzig Germany

Logic simulation is a crucial verification task in processor design. Aiming at significant acceleration of system simulation we have parallelized IBM's cycle-based simulator TEXSIM. The resulting parallelTEXSIM has already been employed successfully in simulating S/390 architectures on IBM SP systems. Here we present parallelTEXSIM together with its model partitioning environment.

关键词： Circuit simulation Context modeling Computational modeling Logic design Process design Analytical models Timing Clocks Associate members computer science

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Describing software architectures by system structure and properties

Describing software architectures by system structure and pr...

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IEEE Annual international computer Software and Applications conference (COMPSAC)

作者： W. Eixelsberger H. Gall ITC Department ABB Corporate Research Center Norway Distributed Systems Group Technical University of of Vienna Vienna Austria

To support architecture based development, different modeling notations and languages, so called architecture description languages (ADLs), have been designed. To be of help in the development process, software architectures must be described in a complete and consistent manner but without being overloaded with information provided to the system stakeholders. Current architecture description languages provide information about software architectures in a domain independent way. This may lead to inappropriate and incomplete descriptions of software architectures. We introduce a flexible and extensible language called Architecture Structure Description Language (ASDL) developed for describing structural aspects of software architectures and their properties. We thereby focus on the domain of embedded real time systems that have to meet certain timing and safety constraints. The language was developed in an architecture recovery process of a real world Train Control System (TCS) and has been used to describe and reason about TCS's architecture.

关键词： Software systems computer architecture Software architecture Variable speed drives Architecture description languages Real time systems Timing Identity-based encryption Safety Maintenance

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