The proceedings contain 118 papers. The special focus in this conference is on Parallel and Distributed Processing. The topics include: Dynamic reconfiguration of a PMMLA for high-throughput applications;a parallel al...
ISBN:
(纸本)3540643591
The proceedings contain 118 papers. The special focus in this conference is on Parallel and Distributed Processing. The topics include: Dynamic reconfiguration of a PMMLA for high-throughput applications;a parallel algorithm for minimum cost path computation on polymorphic processor array;a performance modeling and analysis environment for reconfigurable computers;an integrated partitioning and synthesis system for dynamically reconfigurabte multi-FPGA architectures;temporal partioning for partially-reconfigurable-field-programmable gate;a java development and runtime environment for reconfigurable computing;synthesizing reconfigurable sequential machines using tabular models;evaluation of a low-power reconfigurable DSP architecture;a reconfigurable hardware-monitor for communication analysis in distributed real-time systems;a mathematical benefit analysis of context switching reconfigurable computing;a configurable computing approach towards real-time target tracking;hardware reconfigurable neural networks;a simulator for the reconfigurable mesh architecture;processor architectures for circuit emulation;an empirical comparison of runtime systems for conservative parallel simulation;synchronizing operations on multiple objects;migration and rollback transparency for arbitrary distributed applications in workstation clusters;a topology based approach to coordinated multicast operations;a parallel evolutionary algorithm for the vehicle routing problem with heterogeneous fleet;artificial neural networks on reconfigurable meshes;a molecular quasi-random model of computations applied to evaluate collective intelligence;replicated shared object model for edge detection with spiral architecture and scheduling tasks of a parallel program in two-processor systems with use of cellular automata.
Logic simulation is a crucial verification task in processor design. Aiming at significant acceleration of system simulation we have parallelized IBM's cycle-based simulator TEXSIM. The resulting parallelTEXSIM ha...
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Logic simulation is a crucial verification task in processor design. Aiming at significant acceleration of system simulation we have parallelized IBM's cycle-based simulator TEXSIM. The resulting parallelTEXSIM has already been employed successfully in simulating S/390 architectures on IBM SP systems. Here we present parallelTEXSIM together with its model partitioning environment.
To support architecture based development, different modeling notations and languages, so called architecture description languages (ADLs), have been designed. To be of help in the development process, software archit...
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To support architecture based development, different modeling notations and languages, so called architecture description languages (ADLs), have been designed. To be of help in the development process, software architectures must be described in a complete and consistent manner but without being overloaded with information provided to the system stakeholders. Current architecture description languages provide information about software architectures in a domain independent way. This may lead to inappropriate and incomplete descriptions of software architectures. We introduce a flexible and extensible language called Architecture Structure Description Language (ASDL) developed for describing structural aspects of software architectures and their properties. We thereby focus on the domain of embedded real time systems that have to meet certain timing and safety constraints. The language was developed in an architecture recovery process of a real world Train Control System (TCS) and has been used to describe and reason about TCS's architecture.
The purpose of the paper is to describe a new semi-automated design space exploration method based on genetic programming. A new control/dataflow specification method is proposed as well as appropriate models for hard...
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The purpose of the paper is to describe a new semi-automated design space exploration method based on genetic programming. A new control/dataflow specification method is proposed as well as appropriate models for hardware parts and algorithms. With this method we are able to test many different hardware architectures and algorithms against cost, speed, computation time and other constraints within a very short time. The remaining manual work is to exploit the model parameters of the components of the architecture and the algorithm. In contrast to other approaches our method is suited for embedded and distributed systems. The method, models and application are explained in detail by means of a comprehensive case study.
Multiprocessor system evaluation has traditionally been based on direct-execution based Execution-Driven simulations (EDS). In such environments, the processor component of the system is not fully modeled. With wide i...
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Multiprocessor system evaluation has traditionally been based on direct-execution based Execution-Driven simulations (EDS). In such environments, the processor component of the system is not fully modeled. With wide issue superscalar processors being the norm in today's multiprocessor nodes, there is an urgent need for modeling the processor accurately. However, using direct execution to model a superscalar processor has been considered an open problem. Hence, current approaches model the processor by interpreting the application executable. Unfortunately, this approach can be slow. In this paper, we propose a novel direct-execution framework that allows accurate simulation of wide-issue superscalar processors without the need for code interpretation. This is achieved with the aid of an Interface Window between the front-end and the architectural simulator, that buffers the necessary information. This eliminates the need for full-fledged instruction emulation. Overall, this approach enables detailed yet fast EDS of superscalar processors. Finally, we evaluate the framework and show good performance for uni- and multiprocessor configurations.
Trace-driven simulation is common technique to accurately estimate the performance of computersystems. Accuracy of the estimated performance greatly depends on the traces as well as the system model itself. The trace...
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Trace-driven simulation is common technique to accurately estimate the performance of computersystems. Accuracy of the estimated performance greatly depends on the traces as well as the system model itself. The trace based performance evaluation, however, suffers from the high cost of trace generation and execution. This has, provided the necessary impetus towards the development of accurate trace sampling methodologies. In this paper, we have presented a new methodology for generating and validating representative reduced traces. Experimental results show effectiveness and usefulness of the proposed technique.
We describe the UPFAST system that automatically generates a cycle level simulator, an assembler and a disassembler from a microarchitecture specification written in a domain specific language called the Architecture ...
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We describe the UPFAST system that automatically generates a cycle level simulator, an assembler and a disassembler from a microarchitecture specification written in a domain specific language called the Architecture Description Language (ADL). Using the UPFAST system, it is easy to retarget a simulator for an existing architecture to a modified architecture since one has to simply modify the input specification and the new simulator is generated automatically. UPFAST also allows porting of simulators to different platforms with minimal effort. We have been able to develop three simulators ranging from simple pipelined processors to complicated out-of-order issue processors over a short period of three months. While the specifications of the architectures varied from 5000 to 6000 lines of ADL code, the sizes of automatically generated software varied from 20000 to 300000 lines of C++ code. The automatically generated simulators are less than 2 times slower than hand coded simulators for similar architectures.
The SAVANT, QUEST II, and HEPE research programs at the University of Cincinnati include the development and distribution of VHDL analysis and simulation capabilities. These capabilities are being freely distributed f...
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The SAVANT, QUEST II, and HEPE research programs at the University of Cincinnati include the development and distribution of VHDL analysis and simulation capabilities. These capabilities are being freely distributed for non-commercial use. The SAVANT project is underway specifically to develop a VHDL analyzer with a well-documented, extensible intermediate form; the main objective is to smooth the integration of VHDL technology into university and industrial research programs. The SAVANT project is funded through the Air Force SBIR program and is a joint activity between the University of Cincinnati and MTL systems, Inc. The QUEST II program is investigating parallel algorithms and architectures for simulation, behavioral synthesis, and ATPG. The HEPE program is investigating (in part) novel strategies for relaxing causal orders in the parallel simulation of active networks. As part of the QUEST II/HEPE simulation activities, a VHDL simulation kernel is being developed that will operate with the SAVANT intermediate form for sequential or parallel execution of VHDL models (a C++ code generator from the SAVANT intermediate is being jointly developed by the SAVANT and QUEST II programs). All of the software from the QUEST and HEPE simulation programs is freely available for use (commercial or otherwise).
Supercomputers have greatly influenced the studies of biological cells and cellular networks. Electrophysiological properties of the cells are now known in great detail. Therefore, computer models are constructed to s...
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Supercomputers have greatly influenced the studies of biological cells and cellular networks. Electrophysiological properties of the cells are now known in great detail. Therefore, computer models are constructed to simulate the electrical activity of single heart cells and networks of coupled heart cells. These simulations are used to mimic the rhythms of the heart, including arrhythmias such as ventricular fibrillation (VF). computersimulations require very large scale computational resources, with parallel or vector architectures offering distinct benefits in terms of the ease of coding the algorithms and in terms of computational performance. Three models, one implemented on a personal computer, the second on a Connection Machine and the third on a Cray C90, are reported. The computersimulations reveal the mechanism of generation of VF-like rhythms in the form of wavelets and spiral waves and suggest novel strategies for terminating these arrhythmias.
A new approach for the modeling and control of automated manufacturing systems is presented. This formulation lends itself to a hybrid model that allows fast and direct design of the system configuration embedded with...
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A new approach for the modeling and control of automated manufacturing systems is presented. This formulation lends itself to a hybrid model that allows fast and direct design of the system configuration embedded with its optimal control policy. A discrete-time linear stochastic state variable model is formally derived from first and second order fluid approximation obtained by splitting the process into two hierarchical layers. This hybrid representation yields a complete dynamical description of the system and offers average values and variances of both performance measures and of their gradients with respect to the most significant design parameters.
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