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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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3-D memory organization and performance analysis for multi-processor network-on-chip architecture

3-D memory organization and performance analysis for multi-p...

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IEEE international conference on 3D System Integration, 3DIC

作者： Awet Yemane Weldezion Zhonghai Lu Roshan Weerasekera Hannu Tenhunen School of Information and Communication Technologies Department of Electronics Computer and Software Systems KTH Royal Institute of Technology Kista Sweden Centre of Microsystems Engineering Department of Engineering Lancaster University Lancaster UK

Several forms of processor memory organizations have been in use to optimally access off-chip memory systems mainly the hard disk drives (HDD). Recent trends show that the solid state drives (SSD) such as flash memories replacing HDDs and multi-processor memory system realized in a single 3-D structure with network-on-chip (NOC) architecture as a communication medium. This paper discusses high level memory organization and architectural modeling and simulation based on 3D NOC. A comparative analysis among several models including Dance-hall, Sandwich, Terminal, Per-layer and mixed architectures is done. simulations in cycle accurate 3-D NOC VHDL model are done to evaluate the performance each architecture in uniform and local traffic patterns.

关键词： Performance analysis Network-on-a-chip

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Efficient exploration of on-chip bus architectures and memory allocation 04

Efficient exploration of on-chip bus architectures and memor...

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international conference on Hardware/Software Codesign and System Synthesis (CODES)

作者： Sungchan Kim Chaeseok Im Soonhoi Ha School of Electrical Engineering and Computer Science Seoul National University Seoul South Korea

ISBN: (纸本)9781581139372

Separation between computation and communication in system design allows the system designer to explore the communication architecture independently of component selection and mapping. We present an iterative two-step exploration methodology for bus-based on-chip communication architecture and memory allocation, assuming that memory traces from the processing elements are given from the mapping stage. The proposed method uses a static performance estimation technique to reduce the large design space drastically and quickly, and applies a trace-driven simulation technique to the reduced set of design candidates for accurate performance estimation. Since local memory traffic as well as shared memory traffic are involved in bus contention, memory allocation is considered as an important axis of the design space in our technique. The viability and efficiency of the proposed methodology are validated by two real-life examples, 4-channel digital video recorder (DVR) and an equalizer for OFDM DVB-T receiver.

关键词： Memory architecture computer architecture System-on-a-chip Space exploration Traffic control Design methodology Permission computer science Iterative methods Video sharing

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Presenting systems concepts in Physiology and Pharmacology with simulation applets in Java

Presenting systems concepts in Physiology and Pharmacology w...

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Annual international conference of the IEEE Engineering in Medicine and Biology Society (EMBC)

作者： J.M. Kootsey G. McAuley Hua Liu Department of Physiology and Pharmacology Loma Linda University Loma Linda CA USA

Java simulation applets solving equations for system models have been constructed for teaching system behavior in Pharmacology and Physiology. The applets are intended to be included in Web pages with text and other illustrations for use in the classroom or in self-study lessons. Students can experiment with the system by changing selected model parameters with sliders, immediately observing the resulting changes in system behavior. Several applet presentations are constructed for a model, each presentation designed for a different learning objective by displaying a subset of output variables and making a subset of parameters available for adjustment. Presentations may include control buttons, a graph for output display, sliders to adjust parameters, a legend table comparing parameter settings for multiple experiments, and an animation of the model linked to the calculations. The applet design is highly modular to facilitate replication with different models. Two architectures were tested and compared: 1) a single applet containing all the functions listed above embedded as a single unit in the Web page and 2) a cluster of individual applets of different functional types (control buttons, graph, sliders, etc.) distributed over the Web page and linked by a control object having no visible interface.

关键词： Physiology Java Education Computational modeling Web pages Mathematical model Differential equations Animation Service oriented architecture Packaging

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Extension processing in a parallel and distributed environment

Extension processing in a parallel and distributed environme...

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IEEE international conference on systems, Man and Cybernetics

作者： Liang-Teh Lee Ching-Ren Wei Department of Computer Science and Engineering Tatung Institute of Technology Taipei Taiwan

Extension set theory is developed for deriving solutions and transformations in problems, especially for contradictory problems, in an intelligent system. A matter element (ME) which contains three tuples, the name N, the characteristic c and the value /spl nu/, is defined to represent an object in the extension set theory. By means of continuous substitution and estimating the correlation between MEs found in the database, a problem is solved or transformed to an equivalent problem which is easier understood and solved. Due to the huge computing power consumed in the process of transforming and comparing MEs and estimating the correlation between the MEs found. Powerful and more effective schemes and architectures are required. We propose a parallel and distributed environment for extension processing. The kernel of the system is an architecture based on dataflow execution with a technique of parallel prefix computation, which is the model of a predefined macro actor to perform the extension process. The extension processing or continuous performing is spawned simultaneously when the associated MEs are returned from the database: the returned MEs are processed in a parallel and distributed manner. Therefore, a higher performance and throughput can be achieved. The evaluation of the scheme is developed and tasted according to the requirement of the extension process. From the simulation results, the proposed scheme and associated architecture can provide an effective environment for transformation of MEs.

关键词： Set theory computer architecture computer science Kernel Concurrent computing Power system modeling Distributed databases Throughput Testing Magnetic flux leakage

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Future electronic power distribution systems a contemplative view

Future electronic power distribution systems a contemplative...

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international conference on Optimization of Electrical and Electronic Equipment, OPTIM

作者： Dushan Boroyevich Igor Cvetković Dong Dong Rolando Burgos Fei Wang Fred Lee Center for Power Electronics Systems (CPES) The Bradley Department of Electrical and Computer Engineering Virginia Polytechnic Institute and State University Blacksburg VA USA

Although it has long been argued that electronic power converters can help improve system controllability, reliability, size, and efficiency, their penetration in power systems is still quite low. The often-cited barriers of higher cost and lower reliability of the power converters are quite high if power electronics is used as direct, one-to-one, replacement for the existing electromechanical equipment. However, if the whole power distribution system were designed as a system of controllable converters, the overall system cost and reliability could actually improve, as is currently the case at low power levels within computer and telecom equipment. Starting from the example of a computer power system, the paper contemplates possible future ac and dc electronic power distribution system architectures, especially in the presence of renewable energy sources. The proposed nanogrid-microgrid-...-grid structure achieves hierarchical dynamic decoupling of generation, distribution, and consumption by using bidirectional converters as energy control centers. This is illustrated by the description and simulation of static and dynamic operation of a dc nanogrid in a hypothetical future sustainable home. Several ideas for modeling, analysis, and system-level design of such systems, including power flow control, protection, stability, and subsystem interactions, are presented.

关键词： Power distribution Power system reliability Costs Distributed computing Telecommunication computing Power system dynamics Controllability Power electronics Control systems Telecommunication control

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Using Digital Twin Data for the Attribute-Based Usage Control of Value-Added Networks

Using Digital Twin Data for the Attribute-Based Usage Contro...

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international conference on Software Defined systems (SDS)

作者： Alexander Kern Reiner Anderl Department of Computer Integrated Systems (DiK) Technical University of Darmstadt Darmstadt Germany

ISBN: (数字)9781728172194

ISBN: (纸本)9781728172200

The great progress in the field of digitization and networking of the industry brings many advantages as well as new challenges. On the one hand, it enables new business models that hold great economic growth potential. On the other hand, it leads to an increased heterogeneity of the resulting value- added networks. This poses a striking problem when it comes to the interconnection of industrial devices and the establishment of new business models. Since the disadvantages can quickly outweigh the advantages, activities in this area proceed still very cautiously. A solution is offered by highly dynamic attribute-based usage control architectures at network-level, which monitor the entire communication in the value-added networks. Previous approaches, however, either have the disadvantage that they can only use communication metadata as attributes, or are highly specialized and tailored to the respective systems of the individual network nodes. In addition, they are usually pure access control systems instead of usage control systems. In this paper, the authors propose a novel attribute-based usage control model (ABUC) that allows simulation models in form of digital twins of the respective network components to be used in order to predict their behavior and thus control network traffic according to predicted usage. The ABUC model is then implemented in a use case and validated with several performance tests.

关键词： Access control computer architecture Biological system modeling Software Business Control systems

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Finite Element Modelling and Analysis of Axial Active Magnetic Bearing

Finite Element Modelling and Analysis of Axial Active Magnet...

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IEEE international conference on Industrial and Information systems

作者： Sudipta Saha M. Nabi Department of Electrical Engineering Indian Institute of Technology Delhi New Delhi India

ISBN: (纸本)9781538684931

Active Magnetic Bearing uses electromagnetic force, generated by current carrying coils to levitate the rotor freely. The application of active magnetic bearing embedded devices like Maglev Train, Fly wheel based energy storage system, Micro precision devices, Blood pump etc. are increasing in industries because of rapid progress happened in the electronics sector and controller structure. Finite Element is a method which allows numerical modelling and analysis of this kind of systems. In this paper, a 2D computer simulation of an axial active magnetic bearing system has been carried out using finite element software COMSOL. The changes in flux density and force are plotted.

关键词： Magnetic levitation Rotors Finite element analysis Magnetomechanical effects Computational modeling Geometry Coils

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embedded processor for array of hydrophone sensors to construct real time images for AUV using FPGA

Embedded processor for array of hydrophone sensors to constr...

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IEEE international conference on Signal and Image Processing Applications (ICSIPA)

作者： Muataz H. Salih Mohd. Rizal Arshad Underwater Robotics Research Group School of Electrical and Electronic Engineering Universiti Sains Islam Malaysia Penang Malaysia

Implementation of embedded systems-on-chip on modern field programmable gate arrays (FPGAs) chip is doable due to its large density. Architecture of multilevel computing focusing on its embedded processor is suggested in our project. The architecture design of embedded processor presents the challenges and opportunities that stem from the task coarse granularity and the large number of input and output for each task. Thus, we have designed a new architecture called embedded Concurrent Computing (ECC). The entire embedded processor architecture is implemented on the FPGA chip using VHDL. We have synthesized and evaluated the embedded system based on an Altera environment by using a DE2 board. The performances of a realistic application show scalable speedups comparable to that of the simulation. Furthermore, the results show the accuracy of Extended Kalman Filter (EKF) rather than the Kalman Filter (KF) in identifying the landmarks and target in underwater environment, and the usefulness of the multiple filtering techniques when the nonlinearities are too large due to linearization errors. We believe that implementation has been achieved in providing low complexity in terms of FPGA resource usage and frequency. In addition, the design methodology allows the embedded processor to be scalable as the entire system grows.

关键词： Sensor arrays Sonar equipment Image sensors Field programmable gate arrays computer architecture embedded computing Process design Concurrent computing embedded system Computational modeling

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A new fault-tolerant scheduling technique for real-time multiprocessor systems

A new fault-tolerant scheduling technique for real-time mult...

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IEEE international conference on embedded and Real-Time Computing systems and Applications (RTCSA)

作者： T. Tsuchiya Y. Kakuda T. Kikuno Department of Information and Computer Sciences Faculty of Engineering Science Osaka University Toyonaka Osaka Japan

In multiprocessors used for implementing real-time applications, it is strongly required to ensure that tasks' deadlines are met in spite of faults. In this paper, we discuss fault-tolerant task scheduling techniques in real-time multiprocessor systems where aperiodic tasks arrive dynamically. For fault-tolerance, multiple copies of each task have to be scheduled on distinct processors in such systems. The authors propose a new technique for efficiently scheduling copies of tasks having small laxity. Then, we integrate our technique with previous work and develop a new scheduling algorithm, removing the assumption on task laxity. simulation results show the effectiveness of our technique.

关键词： Fault tolerant systems Real time systems Multiprocessing systems Processor scheduling Scheduling algorithm Fault tolerance Fault detection Application software Dynamic scheduling Computational modeling

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Real-time benchmark set synthesis based on pWCET estimation and bounded hyper-periods

Real-time benchmark set synthesis based on pWCET estimation ...

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international conference on Circuits, System and simulation (ICCSS)

作者： Ashraf Suyyagh Zeljko Zilic Department of Electrical and Computer Engineering McGill University Montreal QC Canada

ISBN: (纸本)9781538603932

In evaluating performance, schedulability, and energy efficiency metrics for real-time systems, numerous algorithms have been proposed to construct synthetic tasksets for simulation. The resulting taskset characteristics should ideally reflect real workloads while the algorithms generating these tasksets should be efficient. Any experimentation using these tasksets will highly depend on their properties. Current approaches construct the sets by choosing taskset periods and utilisation from statistical distributions and compute the task worst case execution times accordingly. Tasks are generated through timed loops or matrix operations up to the specified task WCET. At times, the taskset hyper-period is bounded to minimise simulation interval through selected assignment of task periods. However, tasks which burn processor cycles through loops and matrix operations do not always reflect realistic task loads. In this paper, we propose a methodology for generating realistic tasksets based on available embedded benchmarks. We extend on previous work and propose new algorithms: CPA-AU/DU (Compute-Propagate-Adjust Ascending/Descending Utilisation) which efficiently pair taskset WCETs with selected discrete periods. Our tasksets have bounded and feasible simulation interval and meet desired total utilisation with minimum digression errors. We also show that our algorithms run in polynomial time.

关键词： Computational modeling Estimation Real-time systems Benchmark testing Hardware Timing Probabilistic logic

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