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GSPN subnet aggregation algorithms for modeling distributed applications in parallel architectures

GSPN subnet aggregation algorithms for modeling distributed ...

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IEEE international conference on systems, Man and Cybernetics

作者： P.A. Bressan L.C. Trevelin ãDepartment of Computer Science Federal University of São Carlos Sao Paulo Brazil

This paper presents algorithms for the mean response time of generalized stochastic Petri nets (GSPN) models based on a methodology for performance modeling and prediction of real time distributed applications running in parallel architectures. For architectures with monoprogrammable processors, the mean response time is obtained by successive aggregation without the use of state space, which prevents state explosion. For multiprogrammable processor architectures, reductions in immediate transitions are applied. The methodology described herein aims to help the designer to predict application execution times early in their developmental phase.

关键词： Parallel architectures Delay Application software Stochastic processes State-space methods Petri nets Predictive models Throughput Explosions Algorithm design and analysis

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6th international conference on Evolutionary Programming, EP 1997

6th International Conference on Evolutionary Programming, EP...

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6th international conference on Evolutionary Programming, EP 1997

ISBN: (纸本)9783540627883

The proceedings contain 37 papers. The special focus in this conference is on Evolutionary Methods for modeling, Training and Alternative Frameworks for the Computational Study of Evolutionary Social systems. The topics include: Complexity formalisms, order and disorder in the structure of art;the application of evolutionary computation to selected problems in molecular biology;parallel evolutionary programming for constructing artificial neural networks;scaling behavior of the evolution strategy when evolving neuronal control architectures for autonomous agents;an object oriented simulation platform applied to markets and organizations;an agent-based computational model for the evolution of trade networks;performance-enhanced genetic programming;comparing subtree crossover with macromutation;composing 16th-century counterpoint with genetic programming and symbiosis;design of a high-gain operational amplifier and other circuits by means of genetic programming;modeling speculators with genetic programming;fast evolution strategies;airspace congestion smoothing by stochastic optimization;evolutionary optimization based on lagrangian with constraint scaling;solving static and dynamic fuzzy constraint networks using evolutionary hill-climbing;applying family competition to evolution strategies for constrained optimization;supporting polyploidy in genetic algorithms using dominance vectors;an individually variable mutation-rate strategy for genetic algorithms;inductive learning of mutation step-size in evolutionary parameter optimization;a note on the escape probabilities for two alternative methods of selection under gaussian mutation;raising theoretical questions about the utility of genetic algorithms;some geometric and algebraic results on crossover and an analysis of evolutionary algorithms based on neighborhood and step sizes.

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international Symposium on High Performance Computing, ISHPC 1997

International Symposium on High Performance Computing, ISHPC...

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international Symposium on High Performance Computing, ISHPC 1997

ISBN: (纸本)3540637664

The proceedings contain 37 papers. The special focus in this conference is on High Performance Computing. The topics include: The generation of optimized codes using nonzero structure analysis;on the importance of an end-to-end view of memory consistency in future computer sysmtems;high performance distributed object systems;instruction cache prefetching using multilevel branch prediction;high performance wireless computing;high-performance computing and applications in image processing and computer vision;evaluation of multithreaded processors and thread-switch policies;a building block for high performance computers;data dependence path reduction with tunneling load instructions;performance estimation of embedded software with pipeline and cache hazard modeling;an implementation and evaluation of a distributed shared-memory system on workstation clusters using fast serial links;designing and optimizing 3-connectivity communication networks using a distributed genetic algorithm;adaptive routing on the recursive diagonal torus;an algorithm for automatic detection of loop indices for communication overlapping;hybrid approach for non-strict dataflow program on commodity machine;scenario-based hypersequential programming;parallelization of space plasma particle simulation;implementing iterative solvers for irregular sparse matrix problems in high performance fortran;cost estimation of coherence protocols of software managed cache on distributed shared memory system;a portable distributed shared memory system on the cluster environment;a method for runtime recognition of collective communication on distributed-memory multiprocessors;efficiency of parallel machine for large-scale simulation in computational physics and a parallelization method for neural networks with weak connection design.

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A simulator construction methodology for the Shiva multiprocessor system

A simulator construction methodology for the Shiva multiproc...

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IEEE international conference on Algorithms and architectures for Parallel Processing (ICAP)

作者： S. Slomka K.F. Sterzl V. Lakshmi Narasimhan The Speech Research Laboratory Signal Processing Research Center Queensland University of Technology Brisbane QLD Australia The PA SE Research Laboratory Department of Electrical and Computer Engineering University of Queensland Saint Lucia QLD Australia Information Management Group ITD DSTO Salisbury SA Australia

This paper describes a simulator for the Shiva multiprocessor system and the simulator construction methodology (SCM) used in its creation. The SCM, based on the active functional unit (AFU) construct, is a modern SCM which is flexible, accurate, fast, easy to use, capable of dynamic reconfigurability at run-time, and most of all simple and capable of quick simulator construction. The AFU SCM is capable of all these things through the use of object-oriented software techniques. The Shiva simulator constructed using the AFU SCM is program-driven and capable of micro and macro architectural simulation.

关键词： Multiprocessing systems Computational modeling Object oriented modeling Signal generators Laboratories computer simulation Discrete event simulation Speech processing Signal processing Information management

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Reliability simulation of fault-tolerant software and systems

Reliability simulation of fault-tolerant software and system...

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Pacific Rim international Symposium on Fault Tolerant systems

作者： S.S. Gokhale M.R. Lyu K.S. Trivedi Department of Electrical and Computer Engineering Center for Advanced Computer & Communication Duke University Durham NC USA Bell Laboratories Lucent Technologies Inc. Murray Hill NJ USA

Fault tolerance is a survival attribute of complex computer systems and software in their ability to deliver continuous service to their users in the presence of faults. Formulating an analytic model for dependability and performance evaluation of hardware/software fault tolerant architectures can be quite cumbersome. Also, in practice, isolating the effect of various parameters on a system, while holding the others constant requires exploring a variety of scenarios. It is economically infeasible to build several such systems. simulation offers an attractive mechanism for dependability evaluation and the study of the influence of various parameters on the failure behavior of the system. In this paper, we develop algorithms to simulate the failure behavior of three commonly used fault tolerant architectures, viz., Distributed Recovery Block (DRB), N-Version Programming (NVP) and N-Self Checking Programming (NSCP). We demonstrate the ability of the approach to simulate complex failure scenarios with various dependencies using some illustrative numerical examples.

关键词： Fault tolerant systems Software systems Hardware Fault tolerance computer architecture Computational modeling Liver Performance analysis embedded software Software maintenance

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Predicting FDDI computer network performance using a calibrated software simulation model

Predicting FDDI computer network performance using a calibra...

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IEEE international conference on Performance, Computing and Communications (IPCCC)

作者： S. Dempsey W.J. Reilly M. Teter L. Weinberg Lockheed Martin Government Electronic Systems Moorestown NJ USA

This report discusses two related activities. The first is the development of a software simulation that predicts the performance of a computer network under different loading conditions. The second is the validation of that simulation. The simulation model is configured to match a laboratory computer network, and each is subjected to similar traffic. The goal of these activities is to establish the credibility of the simulation, which will be used to predict message latency performance, host-to-host, in more complex tactical system architectures planned for Navy use on AEGIS class ships.

关键词： Predictive models FDDI computer networks Software performance Computational modeling computer simulation Laboratories Telecommunication traffic Traffic control Delay

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Object oriented parallel architecture simulator

Object oriented parallel architecture simulator

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international conference on High Performance Computing in the Asia-Pacific Region

作者： Sang Gue Oh Cheol Min Hwang A. Choudhary School of Computer and Information Science Syracuse University USA Electrical and Computer Engineering Northwestern University USA

We introduce a general purpose object oriented simulation environment which enables the study of different architectural configurations for servers. The simulation environment has been built on the top of AWESIME which provides a process oriented discrete event simulation environment. On the top of AWESIME, the simulator provides the base class definitions for major components required to build large scale high-performance computer systems, and a more advanced model of any particular component can be derived from these base classes and easily replaced with the old one. This feature enables rapid evaluation of alternatives in simulating different architectures. In addition this design allows studying a component of interest in various degrees of detail while keeping the other components at a coarse-level for a faster simulation time.

关键词： Parallel architectures Object oriented modeling Computational modeling Discrete event simulation computer simulation Libraries Information science Large-scale systems Scalability Communications technology

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An approach for quantitative analysis of application-specific dataflow architectures

An approach for quantitative analysis of application-specifi...

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international conference on Application Specific systems (ASAP), architectures and Processors

作者： B. Kienhuis E. Deprettere K. Vissers P. Van Der Wolf Philips Research Laboratories Eindhoven Netherlands Delft University of Technnology Delft Netherlands

In this paper we present an approach for quantitative analysis of application-specific dataflow architectures. The approach allows the designer to rate design alternatives in a quantitative way and therefore supports him in the design process to find better performing architectures. The context of our work is video signal processing algorithms which are mapped onto weakly-programmable, coarse-grain dataflow architectures. The algorithms are represented as Kahn graphs with the functionality of the nodes being coarse-grain functions. We have implemented an architecture simulation environment that permits the definition of dataflow architectures as a composition of architecture elements, such as functional units, buffer elements and communication structures. The abstract, clock-cycle accurate simulator has been built using a multi-threading package and employs object oriented principles. This results in a configurable and efficient simulator. Algorithms can subsequently be executed on the architecture model producing quantitative information for selected performance metrics. Results are presented for the simulation of a realistic application on several dataflow architecture alternatives, showing that many different architectures can be simulated in modest time on a modern workstation.

关键词： Data analysis Signal processing algorithms computer architecture Communication system control Process design Streaming media Computational modeling Algorithm design and analysis Laboratories Video signal processing

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Rapid prototyping of parallel and distributed systems by means of high-level Petri nets

Rapid prototyping of parallel and distributed systems by mea...

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IEEE international conference on systems, Man and Cybernetics

作者： B. Mikolajczak A. Cabeza J.T. Rumbut Computer and Information Science Department University of Massachusetts Dartmouth Dartmouth MA USA Architecture and Computer System Division Naval Undersea Warfare Center Newport RI USA

The control flow of parallel or distributed application can be specified by means of high-level Petri nets. One of the aims of rapid prototyping is to provide a validation of the specification; another is to produce a real application code which can be used in the final implementation. We restrict our considerations in this paper to the first goal only. When high-level Petri nets are involved, such as colored Petri nets, then colored linear invariants contribute to map automatically a set of processes on a specific parallel architecture. The purpose of this paper is to present the state of the art of the prototyping methodology and to illustrate it with a suitable example.

关键词： Prototypes Petri nets Power system modeling Application software Information science computer architecture Concurrent computing Distributed computing Military computing Parallel architectures

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Formal methods at the systems level

Formal methods at the systems level

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IEEE international conference on systems, Man and Cybernetics

作者： P. Alexander P. Baraona Department of Electrical & Computer Engineering and Computer Science University of Cincinnati Cincinnati OH USA

This paper presents an attempt at using formal methods as engineering mathematics. We present a Larch interface language for VHDL, called VSPEC, that provides a mechanism for specifying and analyzing systems level requirements. Further, this language supports abstractions and concepts familiar to traditional digital hardware designers. Using VSPEC, it is possible to specify and verify both functional requirements and constraints. Components are specifying using the traditional axiomatic style extended to include performance constraints and activation conditions. Additionally, using VHDL's structural specification features, it is possible to specify and verify abstract architectures formally. The paper opens by describing general characteristics of VSPEC including single component representation and architecture representation. Design rationale are presented to show how VSPEC provides familiar abstractions to the system designer. Finally, annotated examples are presented to demonstrate the language and its expected uses.

关键词： Process design Specification languages Computational modeling Handicapped aids computer science Mathematical model Software systems Mathematics Hardware Digital systems

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