Image processing algorithms which only work on a local neighbourhood are nearly used in every image processing application. Very often several iterations are performed on a fixed neighbourhood which leads to the descr...
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ISBN:
(纸本)9781467373111
Image processing algorithms which only work on a local neighbourhood are nearly used in every image processing application. Very often several iterations are performed on a fixed neighbourhood which leads to the description of stencil codes. A promising approach in embeddedsystems is to use the massively parallel computation power of an FPGA for this kind of algorithms. This not only speeds up processing time, if the FPGA is directly placed inside the image acquisition unit forming a smart camera, but also reduces or even eliminates the PC based hardware which saves space and power. However, most designers begin from scratch when they have to implement stencil computations into smart cameras. This leads to a not fully utilized FPGA because the most efficient usage of the given resources is only secondary alongside functional correctness. Therefore, we are presenting in this paper a framework for stencil code applications which immediately delivers the best architecture regarding prominent resource criteria. An analytical model is used to find an optimized parameter set (degree of parallelism, usage of buffers, etc.) for a highly flexible FPGA implementation. A graphical tool allows to further evaluate the effects of certain parameters. Our results show, that we are able to create an optimized hardware architecture for this application domain.
Current tools for embedded system design have limited support for modelling the interaction of the system with its physical environment. Furthermore, the natural representation of (streaming, real-time) applications w...
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Soft real-time systems are often analysed using hard realtime techniques, which are not suitable to take into account the deadline misses rate allowed in such systems. Therefore, the resulting system is over-dimension...
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ISBN:
(纸本)3540364102
Soft real-time systems are often analysed using hard realtime techniques, which are not suitable to take into account the deadline misses rate allowed in such systems. Therefore, the resulting system is over-dimensioned, thus expensive. To appropriately dimension soft real-time systems, adequate models, capturing their varying runtime behaviour, are needed. By using the concepts of a mathematically defined language, we provide a modelling approach based on patterns that are able to express the variations appearing in the system timing behaviour. Based on these modelling patterns, models can be easily created and are amenable to average case performance evaluation. By the means of a case study, we show the type of results that can be obtained from such an evaluation and how these results are used to dimension the system.
With increasingly complex applications and architectures, the task of determining Pareto-optimal implementations at the system level becomes a challenge even for state-of-the-art Design Space Exploration (DSE) methodo...
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ISBN:
(数字)9783030609399
ISBN:
(纸本)9783030609399;9783030609382
With increasingly complex applications and architectures, the task of determining Pareto-optimal implementations at the system level becomes a challenge even for state-of-the-art Design Space Exploration (DSE) methodologies. In this field, nature-inspired techniques such as Evolutionary Algorithms (EAs) are frequently employed, since they are well-suited to the multi-objective and hard-constrained nature of the DSE optimization problem. On the other hand, meta-heuristic approaches are problem-agnostic and are often observed to converge relatively quickly. Furthermore, this type of optimization lacks explainability, i.e. the way in which the optimization algorithm arrives at improved solutions as well as the individual contributions of design decisions to the resulting quality of a solution are not at all clear - and are consequently not utilized during DSE as of yet. To remedy this, we propose the integration of automated data-mining techniques into state-of-the-art DSE flows. Data mining is, thereby, used for (a) the automatic extraction and generation of previously untapped information from the optimization process to be (b) incorporated into the DSE to enhance optimization quality. We present a variety of ways to extract and include relevant knowledge during DSE, as well as (c) several possibilities to gain insight into the interdependence between decision variables and optimization objectives. Experimental results for benchmark systems for large-scale many-cores to networked embeddedsystems demonstrate the potential of the proposed techniques to improve the quality of the optimized implementations at no DSE-time overhead.
In today's design of embeddedsystems the software part is increasingly important. Over the last years we have observed a shift from hardware to software added value. With the rise of multi- and many-core platform...
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3D stacking and integration can provide significant system advantages. Following a brief technology review, this abstract explores application drivers, design and CAD for 3D ICs. The main 3D exploitation explored in d...
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This paper presents a new co-simulation framework supporting system level power estimation. The goal of this work is to support precise power estimation in the early design stage. The proposed co-simulation provides a...
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ISBN:
(纸本)9783540736226
This paper presents a new co-simulation framework supporting system level power estimation. The goal of this work is to support precise power estimation in the early design stage. The proposed co-simulation provides a guideline to reduce the power dissipation for a SoC design. This approach resulted in energy saving of 61% for redesigned medium access control processors while code size increased by 14%. The accuracy of the power estimation obtained from the proposed framework was around 94.9%. The contribution of the proposed framework was a straightforward method to merge system level power estimation techniques into the system level design environment.
This paper describes an object-oriented model and a reuse-oriented methodology for the co-design of embeddedcomputersystems. Our approach is based on a hierarchy of classes which describes all possible specification...
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This paper describes an object-oriented model and a reuse-oriented methodology for the co-design of embeddedcomputersystems. Our approach is based on a hierarchy of classes which describes all possible specifications of systems of a certain domain, the behavior of hard- and software-components, and the target-architectures. The content of this knowledge base (re-usable, formalized descriptions) is determined by the analysis of known systems. We present solutions for a specification methodology, the modeling of heterogeneous systems by task graphs, and the mapping process from specified requirements down to hard- or software components in a target architecture. This approach is illustrated by functions of the domain of robot controls.
Increased power densities result to higher on-chip temperatures, which in turn creates numerous problems tightly firmed to reliability issues. This problem is expected to become even more severe for deep-submicron tec...
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