Using a signal transition approach to design computation systems has many advantages. The authors illustrate the design of a dataflow processor using the signal transition framework proposed by I.E. Sutherland (1989)....
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Using a signal transition approach to design computation systems has many advantages. The authors illustrate the design of a dataflow processor using the signal transition framework proposed by I.E. Sutherland (1989). Dataflow computers differ from most other parallel architectures. They are based on the concept of data-driven computation instead of the program store computation model. Since the data-driven computation model provides the execution of instructions asynchronously, it is natural to implement a dataflow processor using self-timed circuits. The authors present the design of a static dataflow processor implemented using self-timed circuits. They use VHDL to model part of the design to aid the simulation and verification process.< >
Existing approaches to integrating neural and symbolic processing are divided into the following four categories: developing specialized, structured, localist networks for symbolic processing; performing symbolic proc...
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Existing approaches to integrating neural and symbolic processing are divided into the following four categories: developing specialized, structured, localist networks for symbolic processing; performing symbolic processing in distributed neural networks (in a holistic way); combining separate symbolic and neural network modules; and using neural networks as basic elements in symbolic architectures (the embedded approach). Research issues that need to be addressed in order to advance this field as well as to better understand the nature of intelligence and cognition are outlined.< >
computer-aided design tools for high-speed QAM (quadrature amplitude modulation) modems are being developed to allow system level simulation and IC design to be integrated in the same environment. Digital architecture...
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computer-aided design tools for high-speed QAM (quadrature amplitude modulation) modems are being developed to allow system level simulation and IC design to be integrated in the same environment. Digital architectures for the modulation and demodulation filters are being exploited to develop functional compilers that allow the IC to be customized to system specifications while automating the architecture generation and layout generation. For example, programs have been developed to synthesize the required Nyquist filters from system specifications, generate the architecture using simulations to determine internal and I/O (input/output) wordlengths, and directly generate the layout using previously published optimization strategies to minimize the area and achieve baud rates as high as 50 MBd for 256-level QAM.< >
To control and monitor pumping wells in water works, drainage systems in mines and building pits, and industrial and agricultural contaminations, it is necessary to know the processes in the soil and groundwater zone,...
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To control and monitor pumping wells in water works, drainage systems in mines and building pits, and industrial and agricultural contaminations, it is necessary to know the processes in the soil and groundwater zone, which involve physical or chemical, and biological processes. It is possible to describe these processes with mathematical models, using the heat conductivity-equation and the convection-diffusion equation. The simulation and visualisation of the processes is necessary and helpful in making decisions for operating the system. The use of parallel computerarchitectures, supercomputer/vector processors as well as transputer networks is more effective then the use of serial computers. The computation time, number and speed of iterations, solution stability and discretisation error are improved using these systems.< >
A CAD tool for architecture-level design and analysis of data converters covering a wide range of conversion specifications is described. Building block and functional models are included for performance verification ...
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A CAD tool for architecture-level design and analysis of data converters covering a wide range of conversion specifications is described. Building block and functional models are included for performance verification and, for all synthesized data converter architectures, macromodels are generated with embedded statistical information concerning the nonlinearity characteristics. Such macromodels yield rather fast functional simulated results whose accuracy is similar with the accuracy of the results obtained through much slower and time consuming general purpose simulators.< >
The proceedings contain 23 papers. The topics discussed include: ProSet - a language for prototyping with sets;visualizing optimization algorithms via rapid prototyping of graphical user interfaces;a system level synt...
ISBN:
(纸本)0818635207
The proceedings contain 23 papers. The topics discussed include: ProSet - a language for prototyping with sets;visualizing optimization algorithms via rapid prototyping of graphical user interfaces;a system level synthesis framework for computerarchitectures;rapid prototyping through communicating Petri nets;rapid prototyping using object-oriented modeling and testbed simulation for complex real-time systems;higher-level statecharts for prototyping architectural dynamics;integrating operational specification and performance modeling;a novel VHDL-based computer architecture design methodology;an axiomatic approach of software functionality measure;BBDS - a design tool for architectural evaluation and rapid prototyping of performance critical digital systems;adaptation and modification of NassiShneiderman charts to represent descartes specifications visually;and requirements specification for a realtime embedded expert system for rapid prototyping.
DProto is a computer-aided software engineering (CASE) system for rapidly prototyping concurrent applications. The environment supports codesign and analysis of high-level software and hardware architectures early in ...
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The proceedings contain 56 papers. The special focus in this conference is on computer Aided systems Theory. The topics include: Linear and algorithmic formulation of co-operative computation in neural nets;algebraic ...
ISBN:
(纸本)9783540553540
The proceedings contain 56 papers. The special focus in this conference is on computer Aided systems Theory. The topics include: Linear and algorithmic formulation of co-operative computation in neural nets;algebraic system modelling and implementation;geometric theory of nonlinear dynamical networks;towards a computer aided design of linear control systems;use of modern computer tools for numerical experiments in matrix theory;the concept of the system as a key to system-engineering in the information technology domain;general systems theory requirements for the engineering of complex models;object identification and retrieval in a CAST library;navigation in systems problem solving;systems theory in modelling chromatic retinal visual processing;a transformation of the problems of minimal satisfaction of constraints;an environment for intelligent autonomous system design and simulation;systemsmodeling and process control;incorporating heuristic rules in a multifaceted system;towards formalism of deep model descriptions of dynamic systems;a new approach to the design of concurrent control architectures;on the complexity of system-level diagnosis algorithms;computer aided vision (CAV) a CAST method bank for artificial vision systems;a CAST system for visual fault detection research;CAST tools for automatic FMS-dynamics models synthesis;a high level interactive design environment for complex systems;the signal description language siba;experience in the development of advanced modelling environments;linking *** to practical applications;complete transforms and their incidence in artificial perception systems theory;neural structures to compute homothetic invariances for artificial perception systems.
The design and implementation of a database computer architecture performance evaluation system (DACPES) are presented. DACPES is a simulation tool which can be configured to evaluate a class of parallel database comp...
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The design and implementation of a database computer architecture performance evaluation system (DACPES) are presented. DACPES is a simulation tool which can be configured to evaluate a class of parallel database computers (DBCs), which have shared-nothing architectures, use data flow query processing strategies, and support object-oriented databases. DACPES can be used to simulate concurrent multiple query processing in a parallel DBC under varying conditions. The functions and design issues for each of the modules of DACPES are discussed and a case study of the evaluation of an object flow computer using DACPES is presented.< >
The analysis of complex neural network models via analytical techniques is often quite difficult due to the large numbers of components involved, and the nonlinearities associated with these components. For this reaso...
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The analysis of complex neural network models via analytical techniques is often quite difficult due to the large numbers of components involved, and the nonlinearities associated with these components. For this reason, simulation is seen as an important tool in neural network research. A framework for simulating neural networks as discrete event nonlinear dynamical systems is presented. This includes neural network models whose components are described by continuous-time differential equations, or by discrete-time difference equations. The design and construction of a concurrent object-oriented discrete event simulation environment for neural networks is considered. The use of an object-oriented language provides the data abstraction facilities necessary to support modification and extension of the simulation system at a high level of abstraction. The ability to specify concurrent processing supports execution on parallel architectures. The use of this system is demonstrated by simulating a specific neural network model (ART1) on a general-purpose parallel computer (bus based shared memory system).< >
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