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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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A soft aperiodic task scheduling algorithm in dynamic-priority systems

A soft aperiodic task scheduling algorithm in dynamic-priori...

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IEEE international conference on embedded and Real-Time Computing systems and Applications (RTCSA)

作者： Sungyoung Lee Hyungill Kim Jongwon Lee Department of Computer Engineering Kyung Hee University Seoul South Korea Software Research Laboratory Korea Telecom Seoul South Korea

ISBN: (纸本)0818671068

In this paper, we present a joint scheduling of hard deadline periodic and soft deadline aperiodic tasks in dynamic-priority systems. The proposed algorithm has extended the fixed-critical task indicating (CTI) algorithm developed by the authors previously (1995). The dynamic-CTI algorithm is operated in such a way that dynamic-priority assignment strategy for a given periodic task set and the information on a deadlinewise preassignment table, called dynamic-CTI table, are mixed dynamically according to the aperiodic tasks' arrivals at runtime. The algorithm has a predictability and a less computational complexity in calculating the slacks since it uses the dynamic-CTI table. Our simulation study shows that the dynamic-CTI scheduling has better performance than the fixed-CTI algorithm which is even better than the slack stealing algorithms, especially under a heavy, transient overload.

关键词： Scheduling algorithm Processor scheduling Dynamic scheduling Runtime Computational complexity Delay Heuristic algorithms Computational modeling Telecommunication computing Prediction algorithms

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An algorithm with constant execution time for dynamic storage allocation

An algorithm with constant execution time for dynamic storag...

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IEEE international conference on embedded and Real-Time Computing systems and Applications (RTCSA)

作者： T. Ogasawara Advanced Compiler Group IBM Japan Limited Yamato Kanagawa Japan

The predictability of the computation time of program modules is very important for estimating an accurate worst-case execution time (WCET) of a task in real-time systems. Dynamic storage allocation (DSA) is a common programming technique. Although many DSA algorithms have been developed, they focus on the average execution time rather than the WCET, making it is very difficult to calculate their WCET accurately. In this paper, we propose a new algorithm called Half-Fit whose WCET can be calculated accurately. The algorithm finds a free block without searching on a free list or tree, allowing extra unusable memory called incomplete memory use. In a simulation following a queueing model of M/G//spl infin/, Half-Fit has the advantage over the binary buddy system of more efficient storage utilization. The binary buddy system is a conventional algorithm whose WCET can be calculated.

关键词： Real time systems High level languages Dynamic programming Laboratories Processor scheduling Programming profession Computational modeling Scheduling algorithm computer architecture Upper bound

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Performance estimation of multistreamed, superscalar processors

Performance estimation of multistreamed, superscalar process...

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Annual Hawaii international conference on System Sciences (HICSS)

作者： W. Yamamoto M.J. Serrano A.R. Talcott R.C. Wood M. Nemirosky Department of Electrical and Computer Engineering University of California Santa Barbara CA USA University of California Santa Barbara Santa Barbara CA US Dept. of Electr. & Comput. Eng. California Univ. Santa Barbara CA USA

Multistreamed processors can significantly improve processor throughput by allowing interleaved execution of instructions from multiple instruction streams. We present an analytical modeling technique to evaluate the effect of dynamically interleaving additional instruction streams within superscalar architectures. Using this technique, estimates of the instructions executed per cycle (IPC) for a processor architecture are quickly calculated given simple descriptions of the workload and hardware characteristics. To validate this technique, estimates of the SPEC89 benchmark suite obtained from the model are compared to results from a hardware simulator. Our results show that the technique produces accurate estimates with an average deviation of /spl sim/4% from the simulation results. Finally, we demonstrate that as the number of functional units increases, multistreaming is an effective technique to exploit these additional resources.< >

关键词： Hardware Analytical models Parallel processing Throughput Processor scheduling Interleaved codes computer architecture Dispatching Control systems System performance

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Translation Validation of Code Generation from the SIGNAL Data-Flow Language to Verilog

Translation Validation of Code Generation from the SIGNAL Da...

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international conference on Semantics, Knowledge and Grid (SKG)

作者： Hafiz Muhammad Amjad Kai Hu Jianwei Niu Noor Khan Loïc Besnard Jean-Pierre Talpin School of Computer Science & Engineering Beihang University Beijing China IRISA Rennes France INRIA Campus de Beaulieu Rennes France

ISBN: (数字)9781728158235

ISBN: (纸本)9781728158242

The SIGNAL is a high-level synchronous data-flow language for the design and implementation of safety-critical embedded systems. It provides a unified framework for specification, modeling, formal analysis, and automatic code generation for different general-purpose languages like Java, C, and C++. However, fully implemented and verified open source tool for code generation from SIGNAL to Hardware Description Language (HDL) is not available. This paper describes the formal verification of the generated Verilog code from the SIGNAL language. Proving the correctness of generated code is very important when it is for safety-critical embedded systems. We use the translation validation technique for verifying the correctness of the generated code. In this approach, the Polychrony Toolset builds the models of source SIGNALprograms with its associated model checker SIGALI. The open source tool Yosys generates models for target Verilog programs in the SMT-LIB standard format. We transform the model generated by Yosys to the model accepted by the SIGALI model checker. Finally, we use the SIGALI model checker to validate the translation by symbolic simulation between both source and target program models. The target program may have fewer behaviors than the source program therefore if the model of the target program implies the model of the source program, it means the target program preserves the semantics of the source program, and the translation is correct.

关键词： Hardware design languages Mathematical model Clocks Semantics Tools embedded systems Encoding

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An Energy-Efficient Multi-bit Current-based Analog Compute-In-Memory Architecture and design Methodology

An Energy-Efficient Multi-bit Current-based Analog Compute-I...

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international conference on VLSI Design

作者： Dinesh Kushwaha Ashish Joshi Neha Gupta Aditya Sharma Sandeep Miryala Rajiv V. Joshi S. Dasgupta Anand Bulusu Department of Electronics and Communication Engineering Indian Institute of Technology Roorkee Roorkee Uttarakhand India Intel Technology India Pvt. Ltd. Bangalore Karnataka India Brookhaven National Laboratory Upton USA Thomas J. Watson Research Center Yorktown Heights NY USA

An energy-efficient and multi-bit (4b) current-based analog compute in-memory (CIM) architecture is proposed in this paper. In current-based analog CIM schemes, multiplication and-accumulate (MAC) operation is performed on bitline, and resultant output is equivalent to bitline voltage drop $(\Delta \mathbf{V}_{\text{RBL}})$ . However, dependence of $\Delta \mathbf{V}_{\text{RBL}}$ on process, voltage and temperature (PVT) variations and analog non-idealities (ANIs), reduces the signal-to-noise ratio (SNR) of MAC and degrade the computation accuracy of MAC in analog CIM architecture. An analytical model of $\Delta \mathbf{V}_{\text{RBL}}$ to predict the computation accuracy of MAC in current-based analog CIM architecture through a single SPICE simulation is presented in this paper. The proposed model determines the dynamic range of analog input voltage $(\boldsymbol{V}_{a})$ on the bitline for linear MAC operation for a given technology node. This model also provides a design methodology to predict computation accuracy of MAC and optimize design parameters for current-based analog CIM architecture with the modelling error of 1.1% in SPICE simulations. The implementation of the proposed CIM architecture and model validation are done using a standard 65nm CMOS technology. The proposed architecture achieves $13\times$ energy-efficiency and $2.5\times$ reduction in latency for 4-b multiplication and accumulation (MAC) operation than state-of-the-art. The proposed CIM architecture achieves $13\times$ improvement in Figure of Merit (FoM).

关键词： Semiconductor device modeling Computational modeling Design methodology computer architecture Voltage Predictive models SPICE

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Query Processing and Optimization of Parallel Database System in Multi Processor Environments

Query Processing and Optimization of Parallel Database Syste...

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Asia international conference on modeling & simulation

作者： Sukheja Deepak Singh Umesh Kumar Mishra Durgesh Pandya Bhupendra K. PITM Indore INDIA ICS Vikram University Ujjain India SAIT Indore INDIA ICS Vikaram University Ujjain India

In present scenario parallel database systems are being applicable in a broad range of systems, right from database applications (OLTP) server to decision support systems (OLAP) server. These developments involve database processing and querying over parallel systems. A means to the success of parallel database systems, particularly in decision-support applications (Data warehousing), is parallel query optimization. Given a SQL query, parallel query optimization has the goal of finding a parallel plan that delivers the query result in minimal time. Various useful and competent, optimizing solutions to be implemented For the parallel databases. Parallel DBS attempt to develop recently in order to make highperformance and high-availability database servers at a much lower price for multiprocessor computer architectures than mainframe computers. The objective of this paper is define a novel approach on how to achieve parallelism for relational database multithreaded query execution use to maximum resource utilization of CPU and memory. This technique offer a solution to the problem of minimizing the response time of input queries against parallel databases.

关键词： Query processing computer architecture Optimization Parallel processing Distributed databases

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Model-Based Design Streamlines for STM32 Motor Control embedded Software System*

Model-Based Design Streamlines for STM32 Motor Control Embed...

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international conference on Control, Decision and Information Technologies (CoDIT)

作者： Loubna BELHAMEL Arturo BUSCARINO Antonio CUCUCCIO Luigi FORTUNA Gaetano RASCONA University of Catania Catania Italy CNR-IASI Italian National Research Council-Institute for Systems Analysis and Computer Science A.Ruberti Rome Italy STMicroelectronics Catania Italy

ISBN: (数字)9781728159539

ISBN: (纸本)9781728159546

This paper presents a Model-Based Design (MBD) methodology as a promising approach for the rapid and se-cure development of embedded System applications, including those involving digital controllers. Based on existing hardware and software application-oriented tools by STMicroelectronics, a new modeling technique has been implemented to move from a traditional design workflow to an MBD one by using Mathworks ® software platform. For a practical application of the proposed approach, a case study is reported to design a Permanent Magnet Synchronous Motor (PMSM) drive based on the STM32 MCU family. The main contribution of this paper is to make focus on concretely building a unique model architecture of a complex software/hardware system able to implement all the major aspects of MBD methodology such as executable requirements, Normal and Processor-In-the-Loop (PIL) simulation modes, continuous test and verification, automatic code generation. To achieve this purpose, a new Simulink ® blockset dedicated to the STM32 Motor Control ecosystem was developed. It includes Simulink blocks for maths, algorithms, and IPs, electronic circuitries, MCU peripherals, speed sensors. Simulink ® embedded Coder tool has been used to automatically generate code for a specific STM32 MCU tar-get to overcome the time consuming and error-prone problems of the handwritten coding.

关键词： Motor drives Software packages Mathematical model Hardware Libraries Integrated circuit modeling Tools

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Advances in Mango Leaf Disease Detection Using Deep Neural Networks

Advances in Mango Leaf Disease Detection Using Deep Neural N...

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modeling, simulation & Intelligent Computing (MoSICom), international conference on

作者： Amit Kumar Bairwa Anirudh Singh Satyam Kumar Department of AIML School of CSE Manipal University Jaipur Jaipur India

ISBN: (数字)9798331533311

ISBN: (纸本)9798331533328

In the pursuit of addressing the persistent challenges in agriculture, particularly in the realm of mango cultivation, this research paper marks the culmination of deep learning and computer vision. Focused on the imperative task of mango leaf disease detection, our study introduces innovative advancements, leveraging deep learning models. Our approach embraces a diverse ensemble of deep learning architectures, namely DenseNet121, EfficientNetB2, MobileNetV2, ResNet50, VGG16, and VGG19. Each model is meticulously trained and evaluated on an extensive dataset containing images of healthy and diseased mango leaves. The objective is to develop a robust system capable of accurate and efficient mango leaf disease identification. The results obtained from our experiments are encapsulated in a comprehensive analytics table, showcasing the performance metrics of each model. Notably, ResNet50 exhibits unparalleled accuracy at $\mathbf{9 9. 1 2 \%}$, with impressive precision, recall, and F1-score values. Our research extends beyond model evaluations, delving into the intricate nuances of each algorithm’s contributions. This critical examination serves to guide practitioners and researchers in selecting the most suitable model for their specific agricultural applications. As a testament to the practicality and real-world applicability of our research, we present a robust discussion on the implications of deploying these models in precision agriculture systems. The significance lies not only in the remarkable accuracy achieved but also in the potential for timely intervention and mitigation of economic losses associated with crop damage. It contributes to a profound understanding of the application of deep learning models in the agricultural domain.

关键词： Deep learning Precision agriculture Measurement Accuracy Biological system modeling Computational modeling Prevention and mitigation Object recognition Diseases Residual neural networks

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Optimization Techniques for Dimensionally Truncated Sparse Grids on Heterogeneous systems

Optimization Techniques for Dimensionally Truncated Sparse G...

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Euromicro conference on Parallel, Distributed and Network-Based Processing

作者： Andrei Deftu Alin Murarasu Technische Universität München Germany

Given the existing heterogeneous processor landscape dominated by CPUs and GPUs, topics such as programming productivity and performance portability have become increasingly important. In this context, an important question refers to how can we develop optimization strategies that cover both CPUs and GPUs. We answer this for fastsg, a library that provides functionality for handling efficiently high-dimensional functions. As it can be employed for compressing and decompressing large-scale simulation data, it finds itself at the core of a computational steering application which serves us as test case. We describe our experience with implementing fastsg's time critical routines for Intel CPUs and Nvidia Fermi GPUs. We show the differences and especially the similarities between our optimization strategies for the two architectures. With regard to our test case for which achieving high speedups is a "must'" for real-time visualization, we report a speedup of up to 6.2x times compared to the state-of-the-art implementation of the sparse grid technique for GPUs.

关键词： Optimization Instruction sets Graphics processing units computer architecture Vectors Programming Computational modeling

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Model driven design of heterogeneous synchronous embedded systems

Model driven design of heterogeneous synchronous embedded sy...

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IEEE international conference on Automated Software Engineering (ASE)

作者： Huafeng Zhang Yu Jiang Han Liu Hehua Zhang Ming Gu Jiaguang Sun TNLIST Tsinghua University Beijing China Department of Computer Science University of lllinois at Urbana-Champaign lllinois USA

ISBN: (纸本)9781509055715

Synchronous embedded systems are becoming more and more complicated and are usually implemented with integrated hardware/software solutions. This implementation manner brings new challenges to the traditional model-driven design environments such as SCADE and STATEMATE, that supports pure hardware or software design. In this paper, we propose a co-design tool Tsmart-Edola to facilitate the system developers, and automatically generate the executable VHDL code and C code from the formal verified SyncBlock computation model. SyncBlock is a lightweight high-level system specification model with well defined syntax, simulation and formal semantics. Based on which, the graphical model editor, graphical simulator, verification translator, and code generator are implemented and seamlessly integrated into the Tsmart-Edola. For evaluation, we apply Tsmart-Edola to the design of a real-world train controller based on the international standard IEC 61375. Several critical ambiguousness or bugs in the standard are detected during formal verification of the constructed system model. Furthermore, the generated VHDL code and C code of Tsmart-Edola outperform that of the state-of-the-art tools in terms of synthesized gate array resource consumption and binary code size. The abstract demo video address is : https://***/D9ROyJmKZ4s The tool, user manual and examples can be downloaded: http://***/Tsmart-Edola/.

关键词： Computational modeling Hardware Ports (computers) Software Generators Graphical models Semantics

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