The application of PROTOB, an object-oriented CASE system based on high-level Petri nets, to rapid prototyping of distributed systems is presented. PROTOB consists of several tools supporting specification, modeling a...
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The application of PROTOB, an object-oriented CASE system based on high-level Petri nets, to rapid prototyping of distributed systems is presented. PROTOB consists of several tools supporting specification, modeling and prototyping activities within the framework of the operational software life-cycle paradigm. As its major application area it addresses distributed systems, such as real-time embeddedsystems, communication protocols and manufacturing control systems. The PROTOB methodology and its support environment can be used in software development of distributed discrete-event dynamic systems at three different levels. The functionality of the system can be formally defined and also analyzed quantitatively by building a PROT net based model, which is actually a simulation model. The model becomes more detailed and the timing of the transitions is real, being managed by the host operating system. The PROTOB objects emulating the physical environment are are replaced by a suitable interface which has the task of transforming signals coming from the plant into tokens to be introduced into the PROTOB model and, likewise, of converting tokens coming from the PROTOB model into appropriate commands issued to the plant.< >
The basic structure of a dynamic data-flow architecture based on the argument-fetching data-flow principle is outlined. In particular, the authors present a scheme to exploit fine-grain parallelism in function invocat...
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The basic structure of a dynamic data-flow architecture based on the argument-fetching data-flow principle is outlined. In particular, the authors present a scheme to exploit fine-grain parallelism in function invocation based on the argument-fetching principle. They extend the static architecture by associating a frame of consecutive memory space for each parallel function invocation, called a function overlay, and identify each invocation instance with the base address of its overlay. The scheme gains efficiency by making effective use of the power provided by the argument-fetching data-flow principle: the separation of the instruction scheduling mechanism and the instruction execution. To handle function applications and memory management, the proposed architecture will have a memory overlay manager that is separate from the pipelined execution unit. To verify the design, a set of standard benchmark programs was mapped onto the new architecture and executed on an experimental general-purpose data-flow architecture simulation testbed.< >
Hypercycles, a class of multidimensional graphs that are generalizations of the n-cube are presented. These graphs are obtained by allowing each dimension to incorporate more than two elements and a cyclic interconnec...
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Hypercycles, a class of multidimensional graphs that are generalizations of the n-cube are presented. These graphs are obtained by allowing each dimension to incorporate more than two elements and a cyclic interconnection strategy. Hypercycles offer simple routing and the ability, given a fixed degree, to choose among a number of different size graphs. These graphs can be used in the design of interconnection networks for distributed systems tailored specifically to the topology of a particular application. A back track-to-the-origin-and-retry routing, whereby paths that block at intermediate nodes are abandoned and a new attempt is made, is presented. Intermediate nodes are chosen at random at each point from among those that form the shortest paths from a source to a destination. simulation results that establish the performance of a variety of configurations are presented. An initial attempt at constructing a hypercycle-based router is discussed.< >
The performance of the Astronautics ZS-1, a decoupled access/execute (DAE) processor, is examined. The CPU is composed of two subsystems: an access processor, which handles address generation and fixed-point operation...
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The performance of the Astronautics ZS-1, a decoupled access/execute (DAE) processor, is examined. The CPU is composed of two subsystems: an access processor, which handles address generation and fixed-point operations; and an execute processor, which handles floating-point operations. These two systems communicate through a network of queues and operate in a fairly decoupled manner. This architecture exhibits a form of fine-grain parallelism, called slip, that improves performance. Some performance bounds for the ZS-1 are developed. A simple count of resource usage is sufficient to establish a good upper bound on performance for most vector loops. A dependence graph is used to form another bound that is particularly useful for nonvector loops. This two-bound model accounts for compiler characteristics, such as loop unrolling, and for hardware characteristics, such as memory latency. This model is applied to the first 12 Livermore loops and compared to simulation results for a variety of memory systems. This comparison indicates how well the ZS-1 tolerates increased memory latency as a function of slip and provides insights regarding application codes, architectures, and compiler capabilities.< >
A reference guide is provided for the tool selection process, particularly when applied to computer architecture simulation. Network II.5, Simscript II.5, and ModSim II each provide the capability for assessing comput...
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A reference guide is provided for the tool selection process, particularly when applied to computer architecture simulation. Network II.5, Simscript II.5, and ModSim II each provide the capability for assessing computerarchitectures although the underlying methodology behind each tool varies. Network II.5 is specifically designed for computer network simulation while Simscript II.5 and ModSim II are general-purpose simulation languages, with ModSim II supporting object-oriented programming. As a result, each has its own unique set of strengths and limitations that directly influence each model's ability to support modeling goals. The selection of a tool for a particular modeling effort is highly dependent upon these goals.
A reference guide is provided for the tool selection process, particularly when applied to computer architecture simulation. Network II.5, Simscript II.5, and ModSim II each provide the capability for assessing comput...
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A reference guide is provided for the tool selection process, particularly when applied to computer architecture simulation. Network II.5, Simscript II.5, and ModSim II each provide the capability for assessing computerarchitectures although the underlying methodology behind each tool varies. Network II.5 is specifically designed for computer network simulation while Simscript II.5 and ModSim II are general-purpose simulation languages, with ModSim II supporting object-oriented programming. As a result, each has its own unique set of strengths and limitations that directly influence each model's ability to support modeling goals. The selection of a tool for a particular modeling effort is highly dependent upon these goals.< >
An approach to object-oriented description of reconfigurable parallel architectures based on an extended communicating sequential processes (CSP) model of communication is presented. A workbench called OODRA (object-o...
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An approach to object-oriented description of reconfigurable parallel architectures based on an extended communicating sequential processes (CSP) model of communication is presented. A workbench called OODRA (object-oriented design of reconfigurable architectures), has been designed and implemented, based on this approach which is suitable for the development of highly concurrent, special-purpose, reconfigurable architectures. Intended uses of OODRA include parallel algorithm/architecture functional simulation and reconfiguration algorithm simulation, with an interactive graphical interface for parallel architecture design. Visual programming and parameterized architecture family approaches to design are supported.< >
A feasibility study that has identified computer-aided engineering (CAE) features and a methodology approach that will support BIT (built-in-test) verification through fault simulation are described. With an example, ...
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A feasibility study that has identified computer-aided engineering (CAE) features and a methodology approach that will support BIT (built-in-test) verification through fault simulation are described. With an example, the authors illustrate the evolutionary fault simulation features and the attendant methodology to support BIT verification by simulation. The simulator functionality and methodology will support the complex simulation of an embedded BIT program. These enhancements can also be effective in verification of ATE (automatic test equipment) functional tests for higher density integrated circuits and boards.< >
A method is presented for simulation with two zillion and three values. The values that are propagated by the simulation include the familiar 0, 1, and X and also a collection of named unknowns and their formal negati...
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A method is presented for simulation with two zillion and three values. The values that are propagated by the simulation include the familiar 0, 1, and X and also a collection of named unknowns and their formal negations. Each value fits into a single computer word. Applications of this restricted symbolic evaluation include design rule checking for circuits with embedded arrays and timing verification. The authors explore these two applications briefly. By carefully choosing rules for combining the two zillion and three values, and the representations of the values, it is possible to make simulation surprisingly efficient. The authors present two variants and an implementation of each. Both are fast; the faster one sometimes yields less information.< >
Two schemes for augmenting hypercubes with spare nodes are presented. In both schemes, fault coverage is local in the sense that only the neighbors of the faulty nodes need to know about the faults. Routing in the pre...
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Two schemes for augmenting hypercubes with spare nodes are presented. In both schemes, fault coverage is local in the sense that only the neighbors of the faulty nodes need to know about the faults. Routing in the presence of faults is accomplished by distributed algorithms that deliver messages reliably to their destination nodes. A message destined to a faulty node will be delivered to the spare node that replaces the faulty node. Both node and link failures may be accommodated in both schemes, and because no switches are used for reconfiguration, there is no assumptions about fault-free switches. The two schemes differ in complexity of interconnections between the spare nodes and the original cube nodes. More complex interconnections result in more flexible coverage algorithms and thus, more reliable systems. However, increased flexibility increases the complexity of the routing algorithm because more care has to be given to the possibility of messages looping in cycles and never reaching their destinations. The reliability of the fault coverage schemes and the efficiency of the routing algorithms are evaluated from simulation results.< >
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