PARET (Parallel Architecture Research and Evaluation Tool) is an object-oriented graphical environment for the study of parallel or multiprocessor systems that provides a laboratory for investigation of alternative ar...
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PARET (Parallel Architecture Research and Evaluation Tool) is an object-oriented graphical environment for the study of parallel or multiprocessor systems that provides a laboratory for investigation of alternative architectural decisions and experiments with such issues as scheduling, mapping, and routing policies. PARET is unique in providing an animated interactive visual tool for parallel systems with a modeling paradigm that is closely linked to its graphical representation. Models have the same morphology regardless of the subsystem represented or the level of detail in the model. Presently, PARET runs on SUN workstations, using color graphics, mouse input, and pop-up menus to control and observe a simulation engine. Ongoing projects using PARET include evaluation of a special-purpose multiprocessor system and use of PARET in a system to create application-specific ICs for signal processing.< >
EXIST (Exploration in Smalltalk) is an integrated environment for exploratory VLSI architectural design implemented in the Smalltalk-80 environment. It consists of a functional simulator (INSIST), a floorplanner (FLOO...
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EXIST (Exploration in Smalltalk) is an integrated environment for exploratory VLSI architectural design implemented in the Smalltalk-80 environment. It consists of a functional simulator (INSIST), a floorplanner (FLOORIST) and a database (DATABIST). EXIST contains several unique features including: editing while in simulation, manual and automated hierarchical floorplan optimization, and user-friendly interface based on the model-view controller paradigm of Smalltalk. These features make EXIST a promising environment for exploration of alternative VLSI architectures, such as RISC (reduced instruction-set computer) controllers.< >
Emerging multicomputerarchitectures provide a platform upon which to realize substantial performance improvements in simulation. Parallel execution is the means to these improvements, yet hurdles remain: the synchron...
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Emerging multicomputerarchitectures provide a platform upon which to realize substantial performance improvements in simulation. Parallel execution is the means to these improvements, yet hurdles remain: the synchronization of simulation time across multicomputer nodes and whether sufficient model parallelism can be identified to enable substantial speedup. Overcoming these obstacles will make speeding up the execution of simulations by several orders of magnitude practical. simulation environments of the future must build on traditional object-oriented methods and the new logic program paradigms in a way which does not hide the parallelism inherent in models. Distributed operating system kernals and language run-time systems must then be able to exploit this parallelism to support concurrent execution of simulations on multicomputers. Finally, these simulation kernels must support this parallelism transparently, that is, without modification at the model source code levels. Without this transparency, models will have to be continually re- written when moving from model develpment, testing, and validation on sequential hardware to parallel hardware for simulation experiments.
The APES system for the design and evaluation of VLSI or WSI array processors is presented. APES makes it possible to study fault-tolerant array architectures and methodologies by simulating the behavior of the system...
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The APES system for the design and evaluation of VLSI or WSI array processors is presented. APES makes it possible to study fault-tolerant array architectures and methodologies by simulating the behavior of the system when faults occur: the type and distribution of faults can be defined by the designer. A diagnostic tool is integrated in APES to evaluate the fault-detection and error-correction capabilities of the system under observation. Another tool makes it possible to perform and evaluate the array reconfiguration after fault occurrence by adopting a user-defined strategy. Features including data entry (using a graphic editor or a hardware description language), the simulation engine, the fault injector, the diagnostic evaluator, and the restructuring/reconfiguration manager are discussed.< >
The author describes his experience with the development of large-scale, highly parallel applications hosted on a variety of parallel processing architectures. He suggests that researchers should not become so caught ...
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The author describes his experience with the development of large-scale, highly parallel applications hosted on a variety of parallel processing architectures. He suggests that researchers should not become so caught up in the search for general and consistent models and programming tools for parallel processing that they forsake the ability to tailor the processing resources of the system to the requirements of the problem, and vice versa. High-level abstractions that hide architectural details may obscure performance issues that are important to the algorithm design process. It is concluded that the parallel processing community does not need a single, uniform set of models, tools or paradigms to achieve success. All that is needed is the same sort of basic design and analysis tools that have served the sequential processing community for a number of years.< >
A probabilistic model for the accumulation of clock skew in synchronous systems is presented. The model is used to derive upper bounds for expected skew and its variance, in tree distribution systems with N synchronou...
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A probabilistic model for the accumulation of clock skew in synchronous systems is presented. The model is used to derive upper bounds for expected skew and its variance, in tree distribution systems with N synchronously clocked processing elements. The results are applied to two specific models for clock distribution. In the first, which is called metric-free, the skew in a buffer stage is Gaussian with a variance independent of wire length. The second, metric, model, is intended to reflect VLSI constraints: the clock skew in a stage is Gaussian with a variance proportional to wire length, and the distribution tree is an H-tree embedded in the plane. Upper bounds on skew are obtained for both models. Estimates of the constants of proportionality as well as the asymptotic behavior have been obtained and verified by simulation.< >
The following topics are dealt with: fault-tolerant computers;associative processors and memories;defect-tolerant components;systolic array processors;signal processing architectures;emerging architectures;multiproces...
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The following topics are dealt with: fault-tolerant computers;associative processors and memories;defect-tolerant components;systolic array processors;signal processing architectures;emerging architectures;multiprocessors;distributed systems;image processing architectures;logic and system simulation;circuit and interconnection simulation;hierarchical design and silicon compilers;logic synthesis and design languages;device modeling and simulation;testing;hardware accelerators;knowledge-based tools;WSI;packaging;physical design;automation and robotics;image processing and graphics;computer networks;parallel/multiprocessing systems;supercomputers;application-specific ICs;intelligent workstations;technology transfer;and reliabiity and maintainability. 251 papers were presented, of which 243 are published in full in the present proceedings, and 8 as abstracts only.
The conference proceedings contain 232 papers (five in summary form only). The following topics are dealt with: robotics;decision support;systems analysis, modeling, and identification;advanced systems theory;artifici...
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The conference proceedings contain 232 papers (five in summary form only). The following topics are dealt with: robotics;decision support;systems analysis, modeling, and identification;advanced systems theory;artificial intelligence and applications;software systems engineering;expert systems;logic and inference;systems design;knowledge-based simulation;human problem-solving and displays;information systems design;neural networks;advanced systems theory;automated manufacturing;perception and image understanding;international conflict resolution;neural network architectures;human-computer interaction;neural and cognitive systems;pattern recognition and image understanding;system design for human interaction;computer vision;adaptive and learning systems;fuzzy sets and systems;pilot's associate program system;biological and vision system cybernetics;and handwriting and associated interface issues.
As a result of recent advances in artificial intelligence, human cognitive modelling, autonomous systems and telerobotics, there is an opportunity to broaden our concepts of technology for projecting action at a dista...
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As a result of recent advances in artificial intelligence, human cognitive modelling, autonomous systems and telerobotics, there is an opportunity to broaden our concepts of technology for projecting action at a distance. We draw on these advances to develop a conceptual and architectural framework that enables efficient projection in time and space of intermingled manipulation and cognition tasks. Where AI-based autonomous systems have previously been concerned with human supervisory intervention primarily at a cognitive level, we add methods for rendezvous, capture and rehandoff of embedded manipulation tasks. Where telerobotics has been concerned with the projection of sensory-motor manipulation, we add the projection of cognitive processing. Thus extended, the two technologies mirror one another and merge into one of "tele-autonomous systems". We introduce notions of how the sensory, cognitive and motor functions of tele-autonomous systems can be factored and transferred back and forth between human and machine. We illustrate how the times to complete tele-autonomous tasks can be reduced through time and space constraint relaxations effected through simple controls: We employ the concepts of forward simulation and predictor display, augmented by "time and position clutches", "time ratio controls" and "time brakes", to control the resulting manipulation paths and event transitions. We sketch some generic architectural and human interface implications of these methods. Finally, we describe our environment for exploring these methods and the results of some recent experiments.
The following topics are dealt with: interconnection networks;memory management;mathematical analysis and computation;parallel processing languages;operating systems;parallel algorithms;array processors;fault-tolerant...
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ISBN:
(纸本)0818607246
The following topics are dealt with: interconnection networks;memory management;mathematical analysis and computation;parallel processing languages;operating systems;parallel algorithms;array processors;fault-tolerant designs;VLSI and optical architectures;performance analysis;multiprocessors;pipeline/vector processors;parallel computation;dataflow computers;hypercube architecture;systolic architecture;artificial intelligence;supercomputing hardware;simulation and modeling;multigrid/mesh applications;vectorization/dataflow processing;graph theory;parallel processing techniques;data structures;distributed processing;and logic programming. 170 papers were presented, all of which are published in full in the present proceedings.
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