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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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Fast-Accurate Non-Polynomial Metamodeling for Nano-CMOS PLL Design Optimization

Fast-Accurate Non-Polynomial Metamodeling for Nano-CMOS PLL ...

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international conference on VLSI Design

作者： Oleg Garitselov Saraju P. Mohanty Elias Kougianos Nano-Systems Design Laboratory Department of Computer Science and Engineering University of North Texas Denton USA Nano-Systems Design Laboratory Department of Engineering Technology University of North Texas Denton USA

At the nanoscale domain, the simulation, design, and optimization time of the circuits have increased significantly due to high-integration density, increasing technology constraints, and complex device models. This necessitates fast design space exploration techniques to meet the shorter time to market driven by consumer electronics. This paper presents non-polynomial metamodels (surrogate models) using neural networks to reduce the design optimization time of complex nano-CMOS circuit with no sacrifice on accuracy. The physical design aware neural networks are trained and used as metamodels to predict frequency, locking time, and power of a PLL circuit. Different architectures for neural networks are compared with traditional polynomial functions that have been generated for the same circuit characteristics. Thorough experimental results show that only 100 sample points are sufficient for neural networks to predict the output of circuits with 21 design parameters within 3% accuracy, which improves the accuracy by 56% over polynomial metamodels. The generated metamodels are used to perform optimization of the PLL using a bee colony algorithm. It is observed that the non-polynomial (using neural networks) metamodels achieve more accurate results than polynomial metamodels in shorter optimization time.

关键词： Phase locked loops Integrated circuit modeling Optimization Polynomials Biological neural networks Neurons

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Model-Based Design for high performance devices oriented to advanced smart solutions

Model-Based Design for high performance devices oriented to ...

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international conference on Information Science and Technology (ICIST)

作者： Loubna Belhamel Arturo Buscarino Antonio Cucuccio Luigi Fortuna Gaetano Rascona University of Catania Catania Italy CNR-IASI Italian National Research Council-Institute for Systems Analysis and Computer Science A. Ruberti Rome Italy STMicroelectronics Catania Italy

ISBN: (数字)9781728166469

ISBN: (纸本)9781728166476

This paper applies Model-Based Design methodologies to develop a high-performance device driver model suitable for advanced smart solutions. These modeling techniques are mandatory to use when designing advanced smart applications based on embedded devices. The paper proposes an innovative approach to accurately models the operations of the STM32 analog converter peripheral for both simulation purpose and to generate an optimized code that integrates on the Low-Level STM32 firmware driver. A new Simulink toolbox has been developed to replicate the ADC functions. Finally, an example has been presented to show the effectiveness of this new modeling approach.

关键词： Performance evaluation Information science Software packages Design methodology Encoding Device drivers Microprogramming

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DC/sup 2/ scheduling for aperiodic tasks in strongly partitioned real-time systems

DC/sup 2/ scheduling for aperiodic tasks in strongly partiti...

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IEEE international conference on embedded and Real-Time Computing systems and Applications (RTCSA)

作者： Daeyoung Kim Yann-Hang Lee Real Time Systems Research Laboratory CISE Department University of Florida Gainesville FL USA Department of Computer Science and Engineering Arizona State University Tempe AZ USA

The strongly partitioned real time system (SP-RTS) provides temporal and spatial partitioning for its integrated real time applications. The SP-RTS architecture adopts a two-level hierarchical scheduling mechanism. In the lower level, multiple partitions (applications) are dispatched under a cyclic scheduling, whereas, in the higher level, multiple periodic tasks of each partition are scheduled according to a fixed priority algorithm. The authors focus on designing algorithms for online scheduling of aperiodic tasks in the SP-RTS environment. The Distance Constraint guaranteed Dynamic Cyclic (DC/sup 2/) scheduler that is proposed uses these basic operations: Left Sliding (LS), Right Putting (RP), and Compacting. These operations dynamically schedule aperiodic tasks within a distance-constrained cyclic schedule. We show that the dynamic applications of these operations do not violate the distance constraint characteristics of a partition cyclic schedule. In addition, the slack time calculation of these dynamic operations can be applied for scheduling hard aperiodic tasks. With the simulation studies, we observed that the DC/sup 2/ can result in a significant performance enhancement in terms of the average response time of soft aperiodic tasks and the acceptance rate for hard aperiodic tasks.

关键词： Real time systems Dynamic scheduling Partitioning algorithms Scheduling algorithm Algorithm design and analysis Aerospace electronics Application software Processor scheduling Laboratories Computational modeling

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Adaptive Modulation and Coding in 5G Networks with Deep Learning

Adaptive Modulation and Coding in 5G Networks with Deep Lear...

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Communication, Computing and Signal Processing (IICCCS), IEEE international conference on

作者： Anjula Gupta Nirmala Reddy Ammar Hameed Shnain K.Revathi S.Gopalakrishnan Chetan K. Verma Department of Computer Application Chandigarh Engineering College Chandigarh Group of Colleges Mohali Punjab India Department of Computer Science & Engineering IES College of Technology Bhopal M.P. India Department Of Computers Techniques Engineering College Of Technical Engineering The Islamic University Najaf Iraq Department Of Computers Techniques Engineering College Of Technical Engineering The Islamic University Of Al Diwaniyah Al Diwaniyah Iraq Prince Shri Venkateshwara Padmavathy Engineering College Chennai India Department of Information Technology Hindustan Institute of Technology and Science Chennai Tamil Nadu India MBIT CVM University Gujrat India

ISBN: (数字)9798350390759

ISBN: (纸本)9798350390766

As part of the present work, it aims to examine the use of deep learning in the improvement of AMC in 5G networks. While traditional AMC methods like the ones mentioned above are applicable to previous generations of the mobile networks, they are not optimal taking into consideration the complexities and the constantly evolving nature of 5G systems. Therefore, we suggest the use of convolutional and recurrent neural networks with the aim of employing deep learning in designing an adaptive system that is capable of predicting the optimal modulation and coding schemes given instantaneous CSI information. It covers data gathering, process modeling, and implementation on a platform designed for 5G consumer network. Thus, the improvement in the data throughput rate, the level of errors, and the degree of satisfaction, obtained through the experimental results, can confirm the optimal nature of the proposed approach. It can be seen that the deep learning-based AMC system is computationally efficient and can be embedded for real-time applications, and the performance of the system is further optimised with improving learning. To conclude, this study reveals the effectiveness of deep learning in transforming AMC in 5G networks, by offering a dependable and dynamic solution the wired and wireless telecommunications networks. In a future work more towards detailing of the model and finding new architectures for the system more refined system can be achieved.

关键词： Deep learning Wireless communication Adaptation models Adaptive systems 5G mobile communication Computational modeling Modulation Throughput Encoding Computational efficiency

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Source Code Annotated Memory Leak Detection for Soft Real Time embedded systems with Resource Constraints

Source Code Annotated Memory Leak Detection for Soft Real Ti...

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IEEE international Symposium on Dependable, Autonomic and Secure Computing (DASC)

作者： Mabel Mary Joy Wolfgang Mueller Franz Josef Rammig C-Lab University of Paderborn Germany Heinz Nixdorf Institute University of Paderborn Germany

With ever increasing complexity of software and increased competition in the market, it is very important to minimize the production to market delivery time. Early phase detection of serious errors in the design and program can be done with automated approaches which save time. Memory leaks are the most important memory related problems which are severe threats to software applications. We propose a novel hybrid automated source code annotated memory leak detection approach for soft real time embedded system software with no garbage collection. We utilize our source code annotation tool to detect the potential memory leak candidates, which are further analyzed in our hybrid leak detection approach. The control flow graph of the source code generated with our annotation tool provides information of all execution paths, where the basic blocks are annotated with specific marks. Our hybrid method combines static and dynamic approaches. Static phase of the hybrid approach detect the potential leak candidates from the control flow graph. Dynamic phase filters false positives from the static phase results and provide results on the actual leaks. In early design stages where a real execution environment and complete executable software are unavailable, a simulation environment and a virtual platform are necessary. Virtual platforms provide flexibility to change the target architecture to be tested. Our proposed dynamic phase of the approach runs on the virtual memory model platform we implemented in SystemC at an abstract level using Transaction Level modeling. The software under test is run on top of this model. This makes our approach faster and provides early results. Our approach can be easily deployed across a variety of architectures as it is compiler independent and does not implement any architecture specific features. Moreover the automated approach provides an efficient methodology to determine potential leaks in early phases of software development.

关键词： Leak detection Software Memory management Resource management Real-time systems Pattern matching

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A new possible branch of computational intelligence for developing real time control in mechatronics

A new possible branch of computational intelligence for deve...

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Annual conference of Industrial Electronics Society

作者： J.K. Tar J.F. Bito I.J. Rudas S.J. Torvinen éInstitute of MathematicsandComputaional ScienceJohn von Neumann Faculty of Informatics Budapest Polytechnic Budapest Hungary Department of Mechanical Engineering Tampere University of Technology Tampere Finland

Recent advances in developing a new branch of soft computing (SC) developed for the control of mechanical devices is reported. Instead of using the architectures of traditional SC it is based on uniform structures obtained from the mathematical framework of classical mechanics. In connection with that the concepts of "minimum operation symplectizing algorithm" (MOSA) and "situation-dependent partial system identification", were developed. The advantages are as follows: (1) a priori known and limited number of parameters; (2) parameter tuning is replaced by simple, explicit, finite, and standard algebraic computations; and (3) to refine the "core algorithm" several interpolation techniques can be incorporated in it. To illustrate its operation simulation examples are given for a special 3-DOF robot arm under a significant environmental interaction.

关键词： Computational intelligence Mechatronics Adaptive control Control systems Coordinate measuring machines computer architecture System identification Interpolation Computational modeling Robots

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A time domain frequency-selective multivariate granger causality approach

A time domain frequency-selective multivariate granger causa...

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Annual international conference of the IEEE Engineering in Medicine and Biology Society (EMBC)

作者： Lutz Leistritz Herbert Witte Institute of Medical Statistics Computer Sciences and Documentation Friedrich Schiller University Jena Jena Germany

The investigation of effective connectivity is one of the major topics in computational neuroscience to understand the interaction between spatially distributed neuronal units of the brain. Thus, a wide variety of methods has been developed during the last decades to investigate functional and effective connectivity in multivariate systems. Their spectrum ranges from model-based to model-free approaches with a clear separation into time and frequency range methods. We present in this simulation study a novel time domain approach based on Granger's principle of predictability, which allows frequency-selective considerations of directed interactions. It is based on a comparison of prediction errors of multivariate autoregressive models fitted to systematically modified time series. These modifications are based on signal decompositions, which enable a targeted cancellation of specific signal components with specific spectral properties. Depending on the embedded signal decomposition method, a frequency-selective or data-driven signal-adaptive Granger Causality Index may be derived.

关键词： Time series analysis Time-frequency analysis Signal resolution Time-domain analysis Computational modeling

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A general framework for formalizing UML with formal languages 01

A general framework for formalizing UML with formal language...

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Proceedings of the 23rd international conference on Software Engineering

作者： William E. McUmber Betty H. C. Cheng Department of Computer Science and Engineering Michigan State University 3115 Engineering Building East Lansing MI

ISBN: (纸本)9780769510507

Informal and graphical modeling techniques enable developers to construct abstract representations of systems. Object-oriented modeling techniques further facilitate the development process. The Unified modeling Language (UML), an object-oriented modeling approach, could be broad enough in scope to represent a variety of domains and gain widespread use. Currently, UML comprises several different notations with no formal semantics attached to the individual diagrams. Therefore, it is not possible to apply rigorous automated analysis or to execute a UML model in order to test its behavior, short of writing code and performing exhaustive testing. We introduce a general framework for formalizing a subset of UML diagrams in terms of different formal languages based on a homomorphic mapping between metamodels describing UML and the formal language. This framework enables the construction of a consistent set of rules for transforming UML models into specifications in the formal language. The resulting specifications derived from UML diagrams enable either execution through simulation or analysis through model checking, using existing tools. This paper describes the use of this framework for formalizing UML to model and analyze embedded systems. A prototype system for generating the formal specifications and results from an industrial case study are also described.

关键词： formal specifications

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CUMULVS: extending a generic steering and visualization middleware for application fault-tolerance

CUMULVS: extending a generic steering and visualization midd...

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Annual Hawaii international conference on System Sciences (HICSS)

作者： P.M. Papadopoulos J.A. Kohl B.D. Semeraro Computer Science and Mathematics Division Oak Ridge National Laboratory Oak Ridge TN USA

CUMULVS is a middleware library that provides application programmers with a simple API for describing viewable and steerable fields in large-scale distributed simulations. These descriptions provide the data type, a logical name of the field/parameter, and the mapping of global indices to local indices (processor and physical storage) for distributed data fields. The CUMULVS infrastructure uses these descriptions to allow an arbitrary number of front-end "viewer" programs to dynamically attach to a running simulation, select one or more fields for visualization, and up-date steerable variables. (Viewer programs can be built using commercial visualization software such as AVS or custom software based on GUI interface builders like Tcl/Tk.) Although these data field descriptions require a small effort on the part of the application programmer, the payoff is a high degree of flexibility for the infrastructure and end-user. This flexibility has allowed us to extend the infrastructure to include "application-directed" checkpointing, where the application determines the essential state that must be saved for a restart. This has the advantage that checkpoints can be smaller and made portable across heterogeneous architectures using the semantic description information that can be included in the checkpoint file.

关键词： Fault tolerance Data visualization Checkpointing Programming profession Application software Libraries Computational modeling Concurrent computing Packaging Fault tolerant systems

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Automated, retargetable back-annotation for host compiled performance and power modeling 13

Automated, retargetable back-annotation for host compiled pe...

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international conference on Hardware/Software Codesign and System Synthesis (CODES)

作者： Suhas Chakravarty Zhuoran Zhao Andreas Gerstlauer Electrical and Computer Engineering The University of Texas at Austin

ISBN: (纸本)9781479914173

With traditional cycle-accurate or instruction-set simulations of processors often being too slow, host-compiled or source-level software execution approaches have recently become popular. Such high-level simulations can achieve order of magnitude speedups, but approaches that can achieve highly accurate characterization of both power and performance metrics are lacking. In this paper, we propose a novel host-compiled simulation approach that provides close to cycle-accurate estimation of energy and timing metrics in a retargetable manner, using flexible, architecture description language (ADL) based reference models. Our automated flow considers typical front- and back-end optimizations by working at the compiler-generated intermediate representation (IR). Path-dependent execution effects are accurately captured through pairwise characterization and backannotation of basic code blocks with all possible predecessors. Results from applying our approach to PowerPC targets running various benchmark suites show that close to native average speeds of 2000 MIPS at more than 98% timing and energy accuracy can be achieved.

关键词： Timing Program processors Computational modeling Accuracy Optimization Estimation Pipelines

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