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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

共 2831 条记录，以下是301-310 订阅

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Exploring the Semantic Gap in Compiling embedded DSLs 18

Exploring the Semantic Gap in Compiling Embedded DSLs

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18th international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Zangerl, Peter Jordan, Herbert Thoman, Peter Gschwandtner, Philipp Fahringer, Thomas Univ Innsbruck Innsbruck Austria

ISBN: (纸本)9781450364942

Optimizing compilers provide valuable contributions to the quality of processed code. The vast majority of application developers rely on those capabilities to obtain binary code efficiently utilizing processing resources. However, compiler proficiency is frequently misjudged by application developers. While for some constellations the effectiveness of those optimizations is grossly underestimated, for others, mostly involving higher-level semantic concepts of embedded DSLs, the compilers' influence on the code quality tends to disappoint. In this paper, we provide examples for the effectiveness and ineffectiveness of state-of-the-art optimizing compilers in improving application code. Based on those observations we characterize the differences between positive and negative examples and provide an in-depth explanation for the short-comings of optimizing compilers. Furthermore, we present a semantic-aware compiler architecture rectifying those deficiencies and outline several example use cases demonstrating our architecture's ability to contribute to the efficiency and the capabilities of embedded DSLs.

关键词： Semantics

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Efficient simulation of 5G Antenna platforms and Circuits using the Characteristic Basis Function Method (CBFM) and GPU Acceleration

Efficient simulation of 5G Antenna platforms and Circuits us...

引用

IEEE international conference on Computational Electromagnetics (ICCEM)

作者： Yang Su Raj Mittra Centre for Intelligent Antenna and Radio Systems University of Waterloo Waterloo ON Canada EMC Lab. Electrical and Computer Engineering Department University of Central Florida Orlando FL USA

ISBN: (数字)9781728134482

ISBN: (纸本)9781728134499

modeling and simulation of electromagnetic devices, such as mobile phones, operating at millimeter wavelengths, e.g., at 30GHz, is challenging because the dimensions of the platform are typically large as compared to the operating wavelength. In this work, we propose several strategies for addressing the issue of CPU time and memory consumption, while preserving the accuracy of the computation. This include geometry simplification as well as application of a numerical algorithm for memory reduction and GPU acceleration. Memory reduction is achieved by employing an efficient iteration-free technique called the Characteristic Basis Functions Method (CBFM) proposed in [1] , to solve problems involving a large number of degrees of freedom. The CBFM has been extensively investigated by a number of authors, including [2] , to analyze objects embedded in multi-layered media.

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BIBNet: An Efficient Super Resolution with Bottleneck-In-Bottleneck

BIBNet: An Efficient Super Resolution with Bottleneck-In-Bot...

引用

international Joint conference on Neural Networks (IJCNN)

作者： Simyung Chang Keuntek Lee Shobhit Jain Cheul-hee Hahm Visual Display Division Samsung Electronics Suwon Korea

ISBN: (数字)9781728169262

ISBN: (纸本)9781728169279

Deep Neural Networks have enabled remarkable progress in the field of single image super resolution (SR). However, these models are often large and complex to be applied for real-world applications with limited resources as in mobile and embedded systems. We investigate whether the typical low latency models as MobileNet can be expected of comparable efficiency at SR tasks with recently reported SR performance in the literature. To this end, a moderate and effective architecture, Bottleneck-In-Bottleneck (BIB), is introduced in this paper. The BIB uses multiple expansion factors of the residual blocks in the form of a bottleneck, reducing computation complexity while utilizing advantageous factors of large feature dimensions. We also propose BIBNet with multiple BIB blocks, which can easily adjust its size and computational cost to create a variety of efficient and high-performance models. Extensive experiments show that, with fewer parameters and computations, BIBNet achieves highly competitive performance compared to other conventional SR methods with more complex architectures.

关键词： Convolution Computational modeling Image resolution computer architecture Task analysis Computational efficiency Machine learning

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NS-3 Model of an IoT network

NS-3 Model of an IoT network

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international conference on Computing, Communication & Automation (ICCCA)

作者： Ravi Kishore Kodali Bysani Kirti National Institute of Technology Warangal WARANGAL

ISBN: (数字)9781728163246

ISBN: (纸本)9781728163253

The Internet of Things is making significant changes to the world we live in from the way we drive to how we make purchases. The Internet of Things platform is responsible for collecting diverse information from sophisticated sensors and providing a common language for devices and apps to communicate with each other. A typical IoT network consists of various embedded sensors, processors and communication hardware. To know how a designed network would perform in real-time, the need for a simulation tool arises as buying the resources necessary for experimental purposes becomes very expensive. ns-3 is one such tool used for simulating real-world networks by writing scripts in C++ and Python on a single computer. ns-3 helps to create various virtual nodes and with the help of the various Helper classes it provides, we can install the necessary devices, internet stacks, application, etc. to our nodes. This paper aims to design and construct an IoT-based network, simulate it using ns-3 and understand how the simulation results obtained can be put to use.

关键词： Computational modeling simulation Tools Writing Real-time systems Sensors Internet of Things

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Evaluation of Approximate Operators Case Study: Sobel Filter Application Executed On An Approximate RISC-V Platform 18

Evaluation of Approximate Operators Case Study: Sobel Filter...

引用

18th international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Ndour, Genevieve Jost, Tiago Trevisan Molnos, Anca Durand, Yves Tisserand, Arnaud Univ Grenoble Alpes CEA LETI Grenoble France Univ Rennes 1 CNRS INRIA IRISA Rennes France Univ Bretagne Sud CNRS Labs STICC UMR 6285 Lorient France

ISBN: (纸本)9781450364942

Approximate computing techniques have been proposed to decrease the energy consumption or improve the performance of computation. Several designs of approximate arithmetic operators are proposed in the literature, suggesting that the operators' energy can be reduced up to 46%. This paper puts existing work in perspective by studying the impact of these operators in a processor targeting the embedded systems. We augment a RISC-V processor with approximate addition and multiplication that support a variable bit-width in the range of 1 to 16 bits. We investigate the error-energy trade-off for a Sobel filter application. The results indicate that, for an acceptable output image degradation, 7.5% of the energy is saved. We conclude that the benefits of using approximate operators in embedded systems processors, have yet to be proved.

关键词： embedded systems approximate computing operators energy

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Fast Parallel simulation of a Manycore Architecture with a Flit-level On-chip Network Model 18

Fast Parallel Simulation of a Manycore Architecture with a F...

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18th international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Kang, Shin-haeng Kang, Jintaek Ha, Soonhoi Seoul Natl Univ Seoul South Korea

ISBN: (纸本)9781450364942

The reliance on simulation for the design of a new architecture continues to increase as the complexity of the architecture increases with more cores integrated and a complex communication fabric. A good compromise between the simulation speed and accuracy should be made in order to explore the wide architectural design space at the early design phase. In this work, we present a novel manycore simulator that achieves fast and scalable performance with a trace-driven parallel simulation technique. Since the communication delay affects the simulation accuracy heavily, the proposed simulator supports a high-speed accurate on-chip network model, which can capture link/buffer congestions. Its development is motivated by an industry project to design a new manycore architecture with 96 cores with a NoC architecture. Experimental results show that the proposed simulator could run real parallel benchmark applications with more than 450 Kcycles/sec/core. It marks a Pareto-optimal simulator between speed and accuracy, compared with existent simulators.

关键词： Manycore Network-on-chip Parallel simulation

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Upgrade of the Ball and Plate Laboratory Model 16th

Upgrade of the Ball and Plate Laboratory Model

引用

16th international-Federation-of-Automatic-Control (IFAC) conference on Programmable Devices and embedded systems PDES

作者： Brezina, Adam Tkacik, Milan Tkacik, Tomas Jadlovska, Slavka Tech Univ Kosice Fac Elect Engn & Informat Dept Cybernet & Artificial Intelligence Letna 9 Kosice 04200 Slovakia

This paper deals with the overall hardware and software upgrade of the Ball&Plate laboratory model used at the Center of Modern Control Techniques and Industrial Informatics (CMCT&II) at Department of Cybernetics and Artificial Intelligence (DCAI), FEEI, TUKE. Reasons for upgrading the model are described, along with the proposed solution. Design and construction of new control hardware for the model is presented. The paper next describes the implementation of program modules for controlling the position of the ball on the plate at level of the MicroController Unit (MCU) and the supervisor computer. Several approaches of image recognition with the purpose to obtain ball position are tested and compared. Finally, the paper presents the model-based design and verification of a PSD control algorithm for the Ball&Plate model. After the upgrade, the model can be used at the CMCTSLII for both research and teaching purposes, with the emphasis on the implementation of applications with high demands on hardware performance, where higher sampling rates of the control algorithms are required. (C) 2019, IFAC (international Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved.

关键词： Cyber-physical systems Electronic design embedded systems Image processing Unstable system computer vision

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Optimizing Cellular Automata Execution by Distributed Discrete Event simulation Techniques

Optimizing Cellular Automata Execution by Distributed Discre...

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Euromicro conference on Parallel, Distributed and Network-Based Processing

作者： Andrea Giordano Donato D’Ambrosio Rocco Rongo William Spataro Alessio De Rango ICAR-CNR Rende Cosenza Italy Department of Matematics and Computer Science University of Calabria Rende Cosenza Italy Department of Environmental Engineering University of Calabria Rende Cosenza Italy

ISBN: (数字)9781728165820

ISBN: (纸本)9781728165837

Cellular Automata (CA) are parallel models well-suited for studying complex systems that are based on local rules of evolution. Notable examples of application are found in fluid-dynamics, crowd simulation, flow-simulation and many more. Nevertheless, CA can be fruitfully exploited as a support in numerical approaches, such as finite element and finite volume methods. Though easily parallelizable by domain partitioning among the nodes of a parallel system, the performance and scalability of cellular automata executed on parallel/distributed machines are limited due to the need of synchronizing nodes at each computational step. With the aim of reducing the synchronization burden, we here present a preliminary study on techniques stemmed from the Discrete-Event simulation field for the optimization of CA on distributed memory architectures. Preliminary results, executed in a distributed memory environment, have shown the usefulness of the considered approach in reducing execution times and therefore in improving the speed up of the parallel execution of the test case.

关键词： Computational modeling Automata Synchronization Numerical models Optimization Memory architecture Mathematical model

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A New Generic HLS Approach for Heterogeneous Computing On the Feasibility of High-Level Synthesis in HSA-Compatible systems 18

A New Generic HLS Approach for Heterogeneous Computing On th...

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18th international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Holzinger, Philipp Reichenbach, Marc Fey, Dietmar Friedrich Alexander Univ Erlangen Nuremberg Chair Comp Architecture Dept Comp Sci Erlangen Germany

ISBN: (纸本)9781450364942

Recent advances like deep learning algorithms or virtual reality applications require an amount of computational power in increasingly smaller devices never seen before. Heterogeneous architectures are seen as a solution to this problem, since they provide a significantly better performance per watt. However, their comparatively difficult integration and programming are a major drawback of this solution. The Heterogeneous System Architecture (HSA) Foundation accepted this problem and published a set of specifications to provide a uniform solution for different architectures. This has been successfully applied to GPUs and DSPs, but is insufficiently researched for FPGAs. However, the usage of reconfigurable logic can further increase the efficiency of embedded systems, while the hurdle of integration can be lowered by high-level synthesis (HLS). Therefore, a combination of the HSA specifications with HLS seems worthwhile to increase the heterogeneity and ease the programmability of FPGAs. This paper provides a suitability analysis of the HSA Intermediate Language (HSAIL) for HLS with suggestions for further improvements to the specification as well as an associated proof of concept. The results show that it is indeed possible to build such a hybrid HLS flow based on the HSA standard, where parts of the process can be shared with other classes of accelerators like GPUs. This implies that progress in the GPU sector like the available source languages can faster carry over to FPGAs and improve the general accessibility.

关键词： Heterogeneous System architectures HSA Foundation High-Level Synthesis HLS Hardware Accelerator FPGA

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EXTRA: An Open Platform for Reconfigurable architectures 18

EXTRA: An Open Platform for Reconfigurable Architectures

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18th international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Ciobanu, Catalin Bogdan Stramondo, Giulio Varbanescu, Ana Lucia Brokalakis, Andreas Nikitakis, Antonis Di Tucci, Lorenzo Rabozzi, Marco Stornaiuolo, Luca Santambrogio, Marco Chrysos, Grigorios Vatsolakis, Charalampos Georgios, Charitopoulos Pnevmatikatos, Dionisios Univ Amsterdam Amsterdam Netherlands Synelixis Solut Chalkida Greece Politecn Milan Milan Italy Telecommun Syst Inst Khania Greece

ISBN: (纸本)9781450364942

Reconfigurable hardware is becoming increasingly mainstream, evolving to a valid alternative to Graphics Processing Units-based hardware accelerators. However, several major challenges remain for migrating existing software to heterogeneous reconfigurable architectures. The EXTRA project aims to develop an integrated environment for developing and programming reconfigurable architectures. The EXTRA platform enables the joint optimization of architecture, tools, and reconfiguration technology, and targets the future High Performance Computing hardware nodes. In this paper, we present four innovative EXTRA technologies: (1) a hardwares-software co-design framework;(2) a parallel memory system;(3) a decoupled access execute framework for reconfigurable technology;and (4) transparent access and virtualization of reconfigurable hardware accelerators. Moreover, we describe how the EXTRA technologies targeting the Amazon F1 cloud compute instances can be used in medical applications such as the retinal image segmentation.

关键词： FPGA Exascale Polymorphic PolyMem CAOS DAER RACOS

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