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10th IEEE international conference and Workshop on the Engineering of computer-Based systems

作者： Agrawal, A Ledeczi, A Vanderbilt Univ Inst Software Integrated Syst Nashville TN 37235 USA

ISBN: (纸本)0769519172

Heterogeneous embedded systems, where configurable or application specific hardware devices (FPGAs and ASICs) are used alongside traditional processors, are becoming more and more widely used To facilitate rapid design and development of such heterogeneous hardware/software systems, it is essential to expand the software design cycle to integrate hardware modeling and simulation. Co-simulation and exploration of the joint design space are key problems. To design, develop and verify such systems, different kinds of simulations at various levels of granularity are required The hardware modeling and simulation framework of the Model-Based Integrated simulation Framework (MILAN) integrates these requirements into a single powerful design, development and simulation environment.

关键词： Application software computer interfaces embedded software embedded system Field programmable gate arrays Hardware Power system modeling Software design Software systems Testing

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Energy Efficient Stream-based Configurable Architecture for embedded Platforms

Energy Efficient Stream-based Configurable Architecture for ...

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international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Pratas, Frederico Tomas, Pedro Trancoso, Pedro Sousa, Leonel Univ Tecn Lisboa INESC ID IST Lisbon Portugal Univ Cyprus Dept Comp Sci Nicosia Cyprus

ISBN: (纸本)9781467322973;9781467322966

Reconfigurable hardware can be used as an energy and performance efficient co-processing solution to accelerate certain types of applications. To facilitate the design of hardware accelerators we have proposed a methodology that adopts the stream-based computing model and the usage of Graphics Processing Units as prototyping platforms. In this paper we go a step further and propose a new modular architecture for low-power reconfigurable systems to easily map the stream-based algorithms. In particular, the architecture consists of a semi-programable accelerator set that can be adapted to the application needs in terms of functional units and number of streaming engines. The proposed embedded architecture mates the exibility of recon. gurable hardware with the advantages of stream computing for the strict needs of embedded recon. gurable devices. We show a possible organization for this architecture. Moreover, we provide a general case study to analyze the scalability of the proposed architecture in an Altera FPGA. Our experimental results show that a significant speed-up can be achieved compared to general purpose processors using low-power FPGA devices. Our preliminary estimates show that it is also possible to achieve energy savings of up to 118x.

关键词： reconfigurable hardware Building construction ARCHITECTURE configurability embedded platform hardware accelerator embedding Platform energy saving Energy efficiency Scalability Field programmable gate arrays LOW POWER

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Towards a transformation chain modeling language

Towards a transformation chain modeling language

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6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Vanhooff, Bert Van Baelen, Stefan Hovsepyan, Aram Joosen, Wouter Berbers, Yolande Katholieke Univ Leuven Dept Comp Sci B-3001 Heverlee Belgium

ISBN: (纸本)3540364102

The Model Driven Development (MDD) paradigm stimulates the use of models as the main artifacts for software development. These models can be situated at high levels of abstraction, close to the application's business domain. Many consecutive automatic transformations (a transformation chain) can be applied to these models to add the necessary details in order to generate a concrete implementation. This means that a large part of the total development effort is relocated to the development of transformations and hence we should have the necessary tooling support for designing transformation chains. In this paper we propose a metamodel for a transformation chain modeling language that enables implementation independent composition of transformations. We also propose a concrete syntax for this language that is based on UML activity diagrams.

关键词： computer programming languages

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A trace-based scenario database for high-level simulation of multimedia MP-SoCs

A trace-based scenario database for high-level simulation of...

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international conference on embedded computer systems

作者： Van Stralen, Peter Pimentel, Andy D. Computer Systems Architecture Group Informatics Institute University of Amsterdam Netherlands

ISBN: (纸本)9781424479382

High-level simulation and design space exploration nowadays are key ingredients for system-level design of modern multimedia embedded systems. The majority of the work in this area evaluates systems under a single, fixed application workload. In reality, however, the application workload in such systems (i.e., the applications that are concurrently executing and contending for system resources), and therefore the intensity and nature of the application demands, can change dramatically over time. To facilitate the simulation and exploration of different workload scenarios, this paper presents the concept of a so-called scenario database, which has been integrated in our Sesame system-level simulation framework. This scenario database compactly stores application scenarios and allows for generating application workloads - in the form of event traces - belonging to the stored scenarios for the purpose of scenario-aware simulation in Sesame. ©2010 IEEE.

关键词： Database systems

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DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator 1

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20th international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Steiner, Lukas Jung, Matthias Prado, Felipe S. Bykov, Kirill Wehn, Norbert Tech Univ Kaiserslautern Kaiserslautern Germany Fraunhofer IESE Kaiserslautern Germany

ISBN: (数字)9783030609399

ISBN: (纸本)9783030609399;9783030609382

The simulation of DRAMs (Dynamic Random Access Memories) on system level requires highly accurate models due to their complex timing and power behavior. However, conventional cycle-accurate DRAM models often become the bottleneck for the overall simulation speed. A promising alternative are DRAM simulation models based on Transaction Level modeling, which can be fast and accurate at the same time. In this paper we present DRAMSys4.0, which is, to the best of our knowledge, the fastest cycle-accurate open-source DRAM simulator and has a large range of functionalities. DRAMSys4.0 includes a novel simulator architecture that enables a fast adaptation to new DRAM standards using a Domain Specific Language. We present optimization techniques to achieve a high simulation speed while maintaining full temporal accuracy. Finally, we provide a detailed survey and comparison of the most prominent cycle-accurate open-source DRAM simulators with regard to their supported features, analysis capabilities and simulation speed.

关键词： DRAM simulation SystemC TLM

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Ultra fast cycle-accurate compiled emulation of inorder pipelined architectures

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JOURNAL OF systems ARCHITECTURE 2007年第8期53卷 501-510页

作者： Farfeleder, Stefan Krall, Andreas Horspool, Nigel TU Wien Inst Comp Sprachen Vienna Austria Univ Victoria Dept Comp Sci Victoria BC V8W 2Y2 Canada

Emulation of one architecture on another is useful when the architecture is under design, when software must be ported to a new platform or is being developed for systems which are still under development, or for embedded systems that insufficient resources to support the software development process. Emulation using an interpreter is typically slower than normal execution by up to 3 orders of magnitude. Our approach instead translates the program from the original architecture to another architecture while faithfully preserving its semantics at the lowest level. The emulation speeds are comparable to, and often faster than, programs running on the original architecture. Partial evaluation of architectural features is used to achieve such impressive performance, while permitting accurate statistics collection. Accuracy is at the level of the number of clock cycles spent executing each instruction (hence the description cycle-accurate). (c) 2006 Elsevier B.V. All rights reserved.

关键词： instruction set emulator interpreter compiled emulation pipelined VLIW architecture

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Advantages of Java processors in cache performance and power for embedded applications

Advantages of Java processors in cache performance and power...

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6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Beck, Antonio Carlos S. Rutzig, Mateus B. Carro, Luigi Univ Fed Rio Grande do Sul Inst Informat BR-90501970 Porto Alegre RS Brazil

ISBN: (纸本)3540364102

Java, with its advantages as being an overspread multiplatform object oriented language, has been gaining popularity in the embedded system market over the years. Furthermore, because of its extra layer of interpretation, it is also believed that it is a slow language while being executed. However, when this execution is done directly in hardware, advantages because of its stack nature start to appear. One of these advantages concerns the memory utilization, impacting in less accesses and cache misses. In this work we analyze this impact in performance and energy consumption, comparing a Java processor with a RISC one based on a MIPS with similar characteristics.

关键词： Java programming language

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Calibration of abstract performance models for system-level design space exploration

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JOURNAL OF SIGNAL PROCESSING systems FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2008年第2期50卷 99-114页

作者： Pimentel, Andy D. Thompson, Mark Polstra, Simon Erbas, Cagkan Univ Amsterdam Inst Informat Comp Syst Architecture Grp NL-1098 SJ Amsterdam Netherlands

High-level performance modeling and simulation have become a key ingredient of system-level design as they facilitate early architectural design space exploration. An important precondition for such high-level modeling and simulation methods is that they should yield trustworthy performance estimations. This requires validation ( if possible) and calibration of the simulation models, which are two aspects that have not yet been widely addressed in the system-level community. This article presents a number of mechanisms for both calibrating isolated model components as well as a system-level performance model as a whole. We discuss these model calibration mechanisms in the context of our Sesame system-level simulation framework. Two illustrative case studies will also be presented to indicate the merits of model calibration.

关键词： system-level modeling and simulation performance analysis model calibration

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A hierarchical modeling framework for on-chip communication architectures 02

A hierarchical modeling framework for on-chip communication ...

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international conference on computer-Aided Design

作者： Zhu, XP Malik, S Princeton Univ Princeton NJ 08544 USA

ISBN: (纸本)0780376072

The communication sub-system of complex IC systems is increasingly critical for achieving system performance. Given this, it is important that the on-chip communication architecture should be included in any quantitative evaluation of system design during design space exploration. While there are several mature methodologies for the modeling and evaluation of architectures of processing elements, there is relatively little work done in modeling of an extensive range of on-chip communication architectures, and integrating this into a single modeling and simulation environment combining processing element and on-chip communication architectures. This paper describes a modeling framework with accompanying simulation tools that attempts to fill this gap. Based on an analysis of a wide range of on-chip communication architectures, we describe how a specific hierarchical class library can be used to develop new on-chip communication architectures, or variants of existing ones with relatively little incremental effort. We demonstrate this through three case studies including two commercial on-chip bus systems and an on-chip packet switching network. Here we show that through careful analysis and construction it is possible for the modeling environment to support the common features of these architectures as part of the library and permit instantiation of the individual architectures as variants of the library design. As part of this methodology we also show how different levels of abstraction of the model can be supported and viewed as different variants that can be used in an accuracy versus simulation time trade-off.

关键词： computer architecture Software prototyping Terminology Prototypes Virtual prototyping Space exploration Instruction sets Network-on-a-chip Spine Network topology

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embedded computer systems: architectures, modeling, and simulation 1

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丛书名： Lecture Notes in computer Science

1000年

作者： Alex Orailoglu Matthias Jung Marc Reichenbach

This book constitutes the refereed proceedings of the 20th international conference on embedded computer systems: architectures, modeling, and simulation, SAMOS 2020, held in Samos, Greece, in July 2020.*

ISBN: (数字)9783030609399

ISBN: (纸本)9783030609382

关键词： computer System Implementation computer Hardware Software Engineering/Programming and Operating systems Information systems and Communication Service computer Communication Networks Artificial Intelligence

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