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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

共 2831 条记录，以下是301-310 订阅

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Instruction buffer with limited control flow and loop nest support

Instruction buffer with limited control flow and loop nest s...

引用

2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Guzma, Vladimír Pitkänen, Teemu Takala, Jarmo Department of Computer Systems Tampere University of Technology FI-33720 Tampere Finland

ISBN: (纸本)9781457708008

In this work, we present a minimalistic, energy efficient implementation of instruction buffer. We use loop detection and execution trace analysis to find most commonly executed loops in already scheduled application and tailor instruction buffer size to the size of most commonly executed loop(s). In addition to our previous work, we allow buffering of loops with limited control flow (early exit from the loop or early return to the beginning of the loop). We also show how analysis of loop nests can decrease the number of times loop body is copied from memory into the buffer. Our results show that in case of favorable loop nest, we can execute all but initial loop iterations from the instruction buffer, keeping instruction memory in the deselect mode. © 2011 IEEE.

关键词： Energy efficiency

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modeling Nested for Loops with Explicit Parallelism in Synchronous DataFlow Graphs 19th

Modeling Nested for Loops with Explicit Parallelism in Synch...

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19th international conference on embedded computer systems: architectures, modeling, and simulation (SAMOS)

作者： Honorat, Alexandre Desnos, Karol Pelcat, Maxime Nezan, Jean-Francois Univ Rennes INSA Rennes CNRS IETR UMR 6164 F-35000 Rennes France Inst Pascal UCA SIGMA CNRS UMR 6602 Clermont Ferrand France

ISBN: (纸本)9783030275624;9783030275617

A common problem when developing signal processing applications is to expose and exploit parallelism in order to improve both throughput and latency. Many programming paradigms and models have been introduced to serve this purpose, such as the Synchronous DataFlow (SDF) Model of Computation (MoC). SDF is used especially to model signal processing applications. However, the main difficulty when using SDF is to choose an appropriate granularity of the application representation, for example when translating imperative functions into SDF actors. In this paper, we propose a method to model the parallelism of perfectly nested for loops with any bounds and explicit parallelism, using SDF. This method makes it possible to easily adapt the granularity of the expressed parallelism, thanks to the introduced concept of SDF iterators. The usage of SDF iterators is then demonstrated on the Scale Invariant Feature Transform (SIFT) image processing application.

关键词： SDF Parallelism

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Characterizing communication behavior of dataflow programs using trace analysis 14

Characterizing communication behavior of dataflow programs u...

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14th international conference on embedded computer systems: architectures, modeling and simulation, SAMOS 2014

作者： Janneck, Jorn W. Casale Brunet, Simone Mattavelli, Marco Department of Computer Science Lund University Sweden EPFL SCI STI MM Ecole Polytechnique Fédérale de Lausanne Switzerland

ISBN: (纸本)9781479937707

This paper investigates the relationship between two ways of analyzing streaming systems: trace analysis for dataflow programs with firing, and network calculus for network flows. While the former focuses on the structure of the dataflow computation while idealizing the interaction with the environment, the latter characterizes the temporal properties of flows of data, largely abstracting from the computations that connect them. In this work, we show how a trace analysis can be used to derive a description of communication behavior of a dataflow program in terms of network calculus, which is then applied to answering a question about the buffer sizing. The example being studied is an MPEG-4 video decoder. © 2014 IEEE.

关键词： Calculations

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A cycle-accurate micro-architecture simulation framework for embedded processors

A cycle-accurate micro-architecture simulation framework for...

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international conference on computer Engineering and systems (ICCES 06)

作者： Ghanem, Ahmed K. El-Mahdy, Ahmed H. Abd El-Salam, Ibrahim Alexandria Univ Fac Eng Dept Comp Sci & Automat Control Alexandria Egypt

ISBN: (纸本)9781424402717

The growth in embedded systems applications and sophistication increased the need for rapid development and modeling of embedded processors. embedded processors are usually application specific. This causes the strong need for modeling environments that can be used for rapid generation of detailed micro-architecture processor simulators. However, existing simulation tools in this category are far less mature and mostly commercial. This paper presents a generic cycle-accurate micro-architecture simulation framework for embedded processors. The framework is designed to generate an RTL (Register Transfer Level) cycle accurate simulator. The framework is built in Java to provide features like extensibility, ability to be changed easily and platform independence. It provides the above features while being as fast as most known available frameworks. The paper uses ARM1022E as an example for embedded processors due to its wide range of applications like modems, cellular phones and automobiles. It simulates its two instruction set architectures (ISA): ARM (32-bit ISA) and THUMB (16-bit ISA). The paper verifies the framework by comparing the ARM simulator with ARMulator (from ARM Ltd.). It also compares the current simulation speed with available known frameworks. Lastly, the paper provides a study of ADPCM (Adaptive Differential Pulse Code Modulation) decode performance on the ARM1022E processor using the framework.

关键词： embedded systems

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Key research challenges for successfully applying MDD within Real-Time embedded Software development

Key research challenges for successfully applying MDD within...

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6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Hovsepyan, Aram Van Baelen, Stefan Vanhooff, Bert Joosen, Wouter Berbers, Yolande Katholieke Univ Leuven Dept Computerwetenschappen B-3001 Heverlee Belgium

ISBN: (纸本)3540364102

Model-Driven Development (MDD) is a software development paradigm that promotes the use of models at different levels of abstraction and perform transformations between them to derive one or more concrete application implementations. In this paper we analyze the current status of MDD regarding its applicability for the development of Real-Time embedded Software. We discuss different modeling framework approaches used to specify the various models, and compare OMG/MDA-based approaches (MOF, UML Profiles and executable UML) with a generic MDD-based approach (GME). Finally, we identify the key challenges for future MDD research in order to successfully apply MDD within RTES Development. These challenges are mainly situated in the field of modeling and standardization of abstraction levels, model transformations and code generation, traceability, and integration of existing software within the MDD development process

关键词： Software engineering

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VGM-Bench: FPU Benchmark Suite for computer Vision, computer Graphics and Machine Learning Applications 20th

VGM-Bench: FPU Benchmark Suite for Computer Vision, Computer...

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20th international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Cremona, Luca Fornaciari, William Galimberti, Andrea Romanoni, Andrea Zoni, Davide Politecn Milan P zza Leonardo Da Vinci 32 I-20133 Milan Italy

ISBN: (纸本)9783030609399;9783030609382

With the Internet-of-things revolution, embedded devices are in charge of an ever increasing number of tasks ranging from sensing, up to Artificial Intelligence (AI) functions. In particular, AI is gaining importance since it can dramatically improve the QoS perceived by the final user and it allows to cope with problems whose algorithmic solution is hard to find. However, the associated computational requirements, mostly made of floating-point processing, impose a careful design and tuning of the computing platforms. In this scenario, there is a need for a set of benchmarks representative of the emerging AI applications and useful to compare the efficiency of different architectural solutions and computing platforms. In this paper we present a suite of benchmarks encompassing computer Graphics, computer Vision and Machine Learning applications, which are greatly used in many AI scenarios. Such benchmarks, differently from other suites, are kernels tailored to be effectively executed in bare-metal and specifically stress the floating-point support offered by the computing platform.

关键词： Benchmarks Machine learning Artificial intelligence Floating-point FPU

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Modified hotspot cache architecture: A low energy fast cache for embedded processors

Modified hotspot cache architecture: A low energy fast cache...

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6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Ali, Kashif Aboelaze, Mokhtar Datta, Suprakash York Univ Dept Comp Sci & Engn Toronto ON M3J 2R7 Canada

ISBN: (纸本)1424401550

The cache memory plays a crucial role in the performance of any processor. The cache memory (SRAM), especially the on chip cache, is 3-4 times faster than the main memory (DRAM). It can vastly improve the processor performance and speed. Also the cache consumes much less energy than the main memory. That leads to a huge power saving which is very important for embedded applications. In today's processors, although the cache memory reduces the energy consumption of the processor, however the energy consumption in the on-chip cache account to almost 40% of the total energy consumption of the processor. In this paper, we propose a cache architecture, for the instruction cache, that is a modification of the hotspot architecture. Our proposed architecture consists of a small filter cache in parallel with the hotspot cache, between the L1 cache and the main memory. The small filter cache is to hold the code that was not captured by the hotspot cache. We also propose a prediction mechanism to steer the memory access to either the hotspot cache, the filter cache, or the L1 cache. Our design has both a faster access time and less energy consumption compared to both the filter cache and the hotspot cache architectures. We use Mibench and Mediabench benchmarks, together with the simplescalar simulator in order to evaluate the performance of our proposed architecture and compares it with the filter cache and the hotspot cache architectures. The simulation results show that our design outperforms both the filter cache and the hotspot cache in both the average memory access time and the energy consumption.

关键词： Cache memory

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Rapid implementation and optimisation of DSP systems on SoPC heterogeneous platforms

Rapid implementation and optimisation of DSP systems on SoPC...

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5th international Workshop on embedded computer systems - architectures, modeling, and simulation

作者： McAllister, J Woods, R Reilly, D Fischaber, S Hasson, R Queens Univ Belfast ECIT Belfast BT3 9DT Antrim North Ireland

ISBN: (纸本)354026969X

The emergence of programmable logic devices as processing platforms for digital signal processing applications poses challenges concerning rapid implementation and high level optimization of algorithms on these platforms. This paper describes Abhainn, a rapid implementation methodology and toolsuite for translating an algorithmic expression of the system to a working implementation on a heterogeneous multiprocessor/field programmable gate array platform, or a standalone system on programmable chip solution. Two particular focuses for Abhainn are the automated but configurable realisation of inter-processor communuication fabrics, and the establishment of novel dedicated hardware component design methodologies allowing algorithm level transformation for system optimization. This paper outlines the approaches employed in both these particular instances.

关键词： embedded systems

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Accelerating high-level engineering computations by automatic compilation of geometric algebra to hardware accelerators

Accelerating high-level engineering computations by automati...

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2010 10th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2010

作者： Huthmann, Jens Müller, Peter Stock, Florian Hildenbrand, Dietmar Koch, Andreas Embedded Systems and Applications Group Technische Universität Darmstadt Germany Computer Science Department Technische Universität Darmstadt Germany

ISBN: (纸本)9781424479382

Geometric Algebra (GA), a generalization of quaternions, is a very powerful form for intuitively expressing and manipulating complex geometric relationships common to engineering problems. The actual evaluation of GA expressions, though, is extremely compute intensive due to the high-dimensionality of data being processed. On standard desktop CPUs, GA evaluations take considerably longer than conventional mathematical formulations. GPUs do offer sufficient throughput to make the use of concise GA formulations practical, but require power far exceeding the budgets for most embedded applications. While the suitability of low-power reconfigurable accelerators for evaluating specific GA computations has already been demonstrated, these often required a significant manual design effort. We present a proof-of-concept compile flow combining symbolic and hardware optimization techniques to automatically generate accelerators from the abstract GA descriptions without user intervention that are suitable for high-performance embedded computing. ©2010 IEEE.

关键词： Program processors

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Two-dimensional fast cosine transform for vector-STA architectures

Two-dimensional fast cosine transform for vector-STA archite...

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5th international Workshop on embedded computer systems - architectures, modeling, and simulation

作者： Robelly, JP Lehmann, A Fettweis, G Tech Univ Dresden Vodafone Chair Mobile Commun Syst D-01062 Dresden Germany

ISBN: (纸本)354026969X

A vector algorithm for computing the two-dimensional Discrete Cosine Transform (2D-VDCT) is presented. The formulation of 2D-VDCT is stated under the framework provided by elements of multilinear algebra. This algebraic framework provides not only a formalism for describing the 2D-VDCT, but it also enables the derivation by pure algebraic manipulations of an algorithm that is well suited to be implemented in SIMD-vector signal processors with a scalable level of parallelism. The 2D-VDCT algorithm can be implemented in a matrix oriented language and a suitable compiler generates code for our fan-lily of STA (Synchronous Transfer Architecture) vector architectures with different amounts of SIMD-parallelism. We show in this paper how important speedup factors are achieved by this methodology.

关键词： Cosine transforms

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