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IEEE/CVF conference on computer Vision and Pattern Recognition (CVPR)

作者： Gholami, Amir Kwon, Kiseok Wu, Bichen Tai, Zizheng Yue, Xiangyu Jin, Peter Zhao, Sicheng Keutzer, Kurt Univ Calif Berkeley EECS Berkeley CA 94720 USA

ISBN: (数字)9781538661000

ISBN: (纸本)9781538661000

One of the main barriers for deploying neural networks on embedded systems has been large memory and power consumption of existing neural networks. In this work, we introduce SqueezeNext, a new family of neural network architectures whose design was guided by considering previous architectures such as SqueezeNet, as well as by simulation results on a neural network accelerator. This new network is able to match AlexNet's accuracy on the ImageNet benchmark with 112x fewer parameters, and one of its deeper variants is able to achieve VGG-19 accuracy with only 4.4 Million parameters, (31x smaller than VGG19). SqueezeNext also achieves better top-5 classification accuracy with 1.3x fewer parameters as compared to MobileNet, but avoids using depthwise-separable convolutions that are inefficient on some mobile processor platforms. This wide range of accuracy gives the user the ability to make speed-accuracy tradeoffs, depending on the available resources on the target hardware. Using hardware simulation results for power and inference speed on an embedded system has guided us to design variations of the baseline model that are 2.59x/8.26x faster and 2.25x/7.5x more energy efficient as compared to SqueezeNet/AlexNet without any accuracy degradation.

关键词： Neural networks Hardware computer architecture Semiconductor process modeling embedded systems Power demand Computational modeling

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Scheduling Real-time HiL Co-simulation of Cyber-Physical systems on Multi-core architectures 24

Scheduling Real-time HiL Co-simulation of Cyber-Physical Sys...

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24th IEEE international conference on embedded and Real-Time Computing systems and Applications (RTCSA)

作者： Saidi, Salah Eddine Pernet, Nicolas Sorel, Yves IFP Energies Nouvelles Rueil Malmaison France INRIA Paris France

ISBN: (纸本)9781538677599

When designing complex cyber-physical systems, engineers have to integrate numerical models from different modeling environments in order to simulate the whole system and estimate its global performances. Co-simulation refers to such joint simulation of heterogeneous models. If some parts of the system are physically available, it is possible to connect these parts to the co-simulation in a Hardware-in-the-Loop (HiL) approach. In this case, the simulation has to be performed in real-time where models execution consists in periodically reacting to the real (physically available) components and providing periodic output updates. This paper deals with the parallelization and scheduling of real-time Hardware-in-the-Loop co-simulation of numerical models on multi-core architectures. A method for defining real-time constraints that have to be met is proposed. Also, an ILP formulation as well as a heuristic are proposed to solve the problem of scheduling the co-simulation on a multi-core architecture while satisfying the previously defined real-time constraints. The proposed approach is evaluated for different sizes of co-simulations and multi-core processors.

关键词： co-simulation HiL scheduling real-time multi-core

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A Model-Based Concept for RTOS Portability 15

A Model-Based Concept for RTOS Portability

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15th IEEE/ACS international conference on computer systems and Applications (AICCSA)

作者： Gomes, Renata Martins Baunach, Marcel Graz Univ Technol Graz Austria

ISBN: (纸本)9781538691205

The amount and diversity of connected computing platforms in the Internet of Things (IoT) is expected to increase exponentially throughout the next years, together with their dependability requirements. This imposes many challenges to software and hardware developers and calls for safe and secure real-time operating systems (RTOSs) that are portable to different or changing hardware. Middleware ports, including RTOS ports, must keep functional and non-functional behavior constant towards the application. Current middleware portability approaches for embedded systems, however, are arduous and error prone. We present a novel approach towards portability of embedded RTOSs based on the formal, hardware-independent and detailed specification of RTOS kernels. With additional models of relevant MCU properties and instruction set architectures (ISA), we are able to generate low level RTOS code for different target architectures. This paper focuses on the hardware-independent model of the context switch within a multi-tasking RTOS. With the general approach, we expect to (1) reduce the effort for maintaining and porting RTOS code, as well as the (2) likeliness for errors, (3) make it easier to test new kernel concepts during OS development, (4) improve security by modeling different levels of access permissions for memory or peripherals depending on the execution mode, and (5) improve safety by formally proving the correctness and consistency of the models.

关键词： RTOS portability code generation formal modeling Event-B IoT

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Worst-Case Reaction Time Optimization on Deterministic Multi-Core architectures with Synchronous Languages

Worst-Case Reaction Time Optimization on Deterministic Multi...

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IEEE international conference on embedded and Real-Time Computing systems and Applications (RTCSA)

作者： Nicolas Hili Alain Girault Éric Jenn IRT Saint-Exupéry Toulouse France CNRS Univ. Grenoble Alpes. Inria Grenoble France Thales AVS Toulouse France

In this paper, we propose a new approach for the predictability and optimality of the inter-core communication and execution of tasks allocated on different cores of multicore architectures. Our approach is based on the execution of synchronous programs written in the ForeC programming language on deterministic architectures called PREcision Timed. The originality of the work resides in the time-triggered model of computation and communication that allows for a very precise control over the thread execution. Synchronization is done via configurable Time Division Multiple Access (TDMA) arbitrations where the optimal size and offset of the time slots are computed to reduce the inter-core synchronization costs. We implemented a robotic application and simulated it using MORSE, a robotic simulation environment. Results show that the model we propose guarantees time-predictable inter-core communication, the absence of concurrent accesses (without relying on hardware mechanisms), and allows for optimized execution throughput.

关键词： Instruction sets Time division multiple access Multicore processing Real-time systems Computational modeling Task analysis

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A retrospective recount of computer architecture research with a data-driven study of over four decades of ISCA publications

arXiv

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arXiv 2019年

作者： Anjum, Omer Hwu, Wen-Mei Xiong, Jinjun IBM-ILLINOIS Center for Cognitive Computing Systems Research

The ACM/IEEE international Symposium on computer Architecture (ISCA) conference is one of the premier forums for presenting, debating and advanc- ing new ideas and experimental results in computer architecture. According to recent calls for papers, research topics are solicited on a broad range of areas, including, but not limited to: processors, memories, storage systems, architectures, interconnection networks, instructions, thread-level parallelism, data-level parallelism, dependable architectures, architecture support for paral- lel software development, architecture support for security, power and energy efficient architectures, application specific architectures, reconfigurable architec-tures, embedded architectures, network and router architectures, architectures for emerging technologies, architecture modeling and performance evaluation. Copyright © 2019, The Authors. All rights reserved.

关键词： Network architecture

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Work-in-Progress: Multiple Alignment of Packet Sequences for Efficient Communication in a Many-Core Neuromorphic System

Work-in-Progress: Multiple Alignment of Packet Sequences for...

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international conference on Compilers, architectures and Synthesis for embedded systems (CASES)

作者： Urgese, Gianvito Peres, Luca Barchi, Francesco Macii, Enrico Acquaviva, Andrea Politecn Torino Dept Control & Comp Engn I-10129 Turin Italy

ISBN: (纸本)9781538655641

In this era, the requirement of high-performance computing at low power cost can be met by the parallel execution of an application on a large number of programmable cores. Emerging many-core architectures provide dense interconnection fabrics leading to new communication requirements. In particular, the effective exploitation of synchronous and asynchronous channels for fast communication from/to internal cores and external devices is a key issue for these architectures. In this paper, we propose a methodology for clustering sequential commands used for configuring the parallel execution of tasks on a globally asynchronous locally synchronous multi-chip many-core neuromorphic platform. With the purpose of reducing communication costs and maximise the exploitation of the available communication bandwidth, we adapted the Multiple Sequence Alignment (MSA) algorithm for clustering the unicast streams of packets used for the configuration of each core so as to generate a coherent multicast stream that configures all cores at once. In preliminary experiments, we demonstrate how the proposed method can lead up to a 97% reduction in packet transmission thus positively affecting the overall communication cost.

关键词： Unicast computer architecture Neuromorphics Clustering algorithms Task analysis Routing Computational modeling

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Designing Application-Specific Heterogeneous architectures from Performance Models

Designing Application-Specific Heterogeneous Architectures f...

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IEEE international Symposium on embedded Multicore Socs (MCSoC)

作者： Thanh Cong François Charot INRIA Univ Rennes Univ Rennes INRIA CNRS IRISA

In this paper, we propose an approach for designing application-specific heterogeneous systems based on performance models through combining accelerator and processor core models. An application-specific program is profiled by the dynamic execution trace and is used to construct a data flow model of the accelerator. modeling of the processor is partitioned into an instruction set architecture (ISA) execution and a micro-architecture specific timing model. These models are implemented on FPGAs to take advantage of their parallelism and speed up the simulation when architecture complexity increases. This approach aims to ease the design of multi-core multi-accelerator architecture, consequently contributes to explore the design space by automating the design steps. A case study is conducted to confirm that presented design flow can model the accelerator starting from an algorithm, validate its integration in a simulation framework, allowing precise performance to be estimated. We also assess the performance of our RISC-V single-core and RISC-V-based heterogeneous architecture models.

关键词： computer architecture Hardware Field programmable gate arrays Computational modeling Registers Timing Acceleration

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ACM international conference Proceeding Series

ACM International Conference Proceeding Series

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18th Annual international conference on embedded computer systems: architectures, modeling and simulation, SAMOS 2018

ISBN: (纸本)9781450364942

The proceedings contain 33 papers. The topics discussed include: a performance evaluation of multi-FPGA architectures for computations of information transfer;massively parallel computation of linear recurrence equations with graphics processing units;a first-order approximation of microarchitecture energy-efficiency;delays and states in dataflow models of computation;communication-aware scheduling algorithms for synchronous dataflow graphs on multicore systems;towards power management verification of time-triggered systems using virtual platforms;architectural considerations for FPGA acceleration of machine learning applications in MapReduce;and fast parallel simulation of a manycore architecture with a flit-level on-chip network model.

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Timing Characteristics of Sensor simulation in an HIL Environment

Timing Characteristics of Sensor Simulation in an HIL Enviro...

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IEEE international conference on Intelligent Data Acquisition and Advanced Computing systems

作者： Igor Khimchenko Peter Schulz IDiAL Fachhochschule Dortmund University of Applied Sciences and Arts Faculty of Electrical Engineering Fachhochschule Dortmund University of Applied Sciences and Arts

ISBN: (纸本)9781728140704

A large number of different applications are associated with different types of embedded systems where sensors play the key role in the creating of a particular view of an environment a system is being operated in. embedded systems are often characterized as the soft- or hard-real-time systems, with high requirements for safety, thus imposing strict requirements for the timing behavior and accuracy of sensors in order to ensure determinism and dependability of a system. At early stage of a system design, analysis or optimization, the satisfaction of the requirements can be checked with models of sensors. The authors aim to investigate the timing performance and accuracy achieved during simulation of the same sensor model implemented in two different ways: as a software artifact and as a field programmable gate arrays (FPGA) solution. This article constitutes a part of the research activities defined in [1].

关键词： Sensor Model modeling simulation Software HIL FPGA MATLAB Simulink high intensity lighting Sensors Field programmable gate arrays Research Activities MATLAB simulating computer software embedded systems modeling time characteristic Determinism

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Designing Fast Convolutional Engines for Deep Learning Applications 25

Designing Fast Convolutional Engines for Deep Learning Appli...

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25th IEEE international conference on Electronics, Circuits and systems (ICECS)

作者： Spagnolo, Fanny Perri, Stefania Frustaci, Fabio Corsonello, Pasquale Univ Calabria Dept Informat Modeling Elect & Syst Engn Arcavacata Di Rende Italy Univ Calabria Dept Mech Energy & Management Engn Arcavacata Di Rende Italy

ISBN: (纸本)9781538695623

Deep learning is rapidly becoming a strong boost to the already pervasive field of computer vision. State-of-the-art Convolutional Neural Networks reach accuracies comparable to human senses. However, the high computational load and low energy efficiency make their implementation on modern embedded systems hard. In this paper, several strategies for designing fast convolutional engines suitable to hardware accelerate Convolutional Neural Networks are evaluated. When implemented within a complete embedded system based on a Zynq Ultrascale+ SoC device, two of the proposed architectures achieve a peak performance of 131.6 GMAC/s at 234MHz running frequency, by occupying at most similar to 13% of the DSP slices available on chip. All the proposed engines overcome state-of-the-art competitors, exhibiting a performance/DSP utilization ratio up to 29.6 times higher.

关键词： Convolutional Neural Networks FPGA DSP slices MACs SIMD architectures

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