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embedded computer systems: architectures, modeling, and simulation 1

引用

丛书名： Lecture Notes in computer Science

1000年

作者： Alex Orailoglu Marc Reichenbach Matthias Jung

ISBN: (数字)9783031150746

ISBN: (纸本)9783031150739

This book constitutes the proceedings of the 22;international conference on embedded computer systems: architectures, modeling, and simulation, SAMOS 2021, which took place in July 2022 in Samos, Greece.;The 21 full papers presented in this volume were carefully reviewed and selected from 44 submissions. The papers are organized in topics as follows: High level synthesis; memory systems; processor architecture; embedded software systems and beyond; deep learning optimization; extra-functional property estimation; innovative architectures and tools for security; european research projects on digital systems, services, and platforms.

关键词： computer System Implementation Control Structures and Microprogramming Software Engineering/Programming and Operating systems Input/Output and Data Communications

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Designing Applications for Heterogeneous Many-Core architectures with the FlexTiles Platform 15

Designing Applications for Heterogeneous Many-Core Architect...

引用

international conference on embedded computer systems architectures modeling and simulation

作者： Janssen, Benedikt Schwiegelshohn, Fynn Koedam, Martijn Duhem, Francois Masing, Leonard Werner, Stephan Huriaux, Christophe Courtay, Antoine Wheatley, Emilie Goossens, Kees Lemonnier, Fabrice Millet, Philippe Becker, Juergen Sentieys, Olivier Huebner, Michael Ruhr Univ Bochum Bochum Germany Eindhoven Univ Technol NL-5600 MB Eindhoven Netherlands Karlsruhe Inst Technol D-76021 Karlsruhe Germany Thales Res & Technol Palaiseau France Univ Rennes 1 IRISA F-35014 Rennes France Inria Rocquencourt France Sundance Multiproc Technol Chesham England

ISBN: (纸本)9781467373111

The FlexTiles Platform has been developed within a Seventh Framework Programme project which is co-funded by the European Union with ten participants of five countries. It aims to create a self-adaptive heterogeneous many-core architecture which is able to dynamically manage load balancing, power consumption and faulty modules. Its focus is to make the architecture efficient and to keep programming effort low. Therefore, the concept contains a dedicated automated tool-flow for creating both the hardware and the software, a simulation platform that can execute the same binaries as the FPGA prototype and a virtualization layer to manage the final heterogeneous many-core architecture for run-time adaptability. With this approach software development productivity can be increased and thus, the time-to-market and development costs can be decreased. In this paper we present the FlexTiles Development Platform with a many-core architecture demonstration. The steps to implement, validate and integrate two use-cases are discussed.

关键词： Seventh Framework Programme self-adaptive heterogeneous many-core high efficiency low development effort

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AADL simulation and Performance Analysis in SystemC

AADL Simulation and Performance Analysis in SystemC

引用

14th IEEE international conference on Engineering Complex computer systems

作者： Varona-Gomez, Roberto Villar, Eugenio Univ Cantabria E-39005 Santander Spain

ISBN: (纸本)9781424444830

Due to the increasing complexity of embedded systems, new design methodologies have to be adopted, since traditional techniques are no longer efficient. Model-based engineering enables the designer to confront these concerns using the architecture description of the system as the main axis during the design cycle. Defining the architecture of the system before its implementation enables the analysis Of constraints imposed on the system from the beginning of the design cycle until the final implementation. AADL has been proposed for designing and analyzing SW and HW architectures for real-time mission-critical embedded systems. Although the Behavioral Annex improves its simulation semantics, AADL is a language for analyzing architectures and not for simulating them. In this paper, AADS, an AADL simulation tool is presented. AADS supports the performance analysis of the AADL specification throughout the refinement process from the initial system architecture until the complete, detailed application and execution platform are developed. In this way, AADS enables the verification of the initial timing constraints during the complete design process.

关键词： embedded systems

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DeePar-SCA: Breaking Parallel architectures of Lattice Cryptography via Learning Based Side-Channel Attacks 20th

DeePar-SCA: Breaking Parallel Architectures of Lattice Crypt...

引用

20th international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Aydin, Furkan Kashyap, Priyank Potluri, Seetal Franzon, Paul Aysu, Aydin North Carolina State Univ Raleigh NC 27606 USA

ISBN: (纸本)9783030609399;9783030609382

This paper proposes the first deep-learning based side-channel attacks on post-quantum key-exchange protocols. We target hardware implementations of two lattice-based key-exchange protocols-Frodo and NewHope-and analyze power side-channels of the security-critical arithmetic functions. The challenge in applying side-channel attacks stems from the single-trace nature of the protocols: each new execution will use a fresh and unique key, limiting the adversary to a single power measurement. Although such single-trace attacks are known, they have been so far constrained to sequentialized designs running on simple micro-controllers. By using deep-learning and data augmentation techniques, we extend those attacks to break parallelized hardware designs, and we quantify the attack's limitations. Specifically, we demonstrate single-trace deep-learning based attacks that outperform traditional attacks such as horizontal differential power analysis and template attacks by up to 900% and 25%, respectively. The developed attacks can therefore break implementations that are otherwise secure, motivating active countermeasures even on parallel architectures for key-exchange protocols.

关键词： Deep-learning Power side-channels Lattice-based key-exchange protocols

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A Toolchain for UML-based modeling and simulation of Networked embedded systems

A Toolchain for UML-based Modeling and Simulation of Network...

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UKSim-AMSS 15th international conference on computer Modelling and simulation (UKSim)

作者： Ebeid, Emad Fummi, Franco Quaglia, Davide Univ Verona Dep Comp Sci I-37100 Verona Italy

ISBN: (纸本)9780769549941;9781467364218

We present a toolchain to model and automatically generate executable simulation code for networked embedded systems applications. First, we provide a UML extension for modeling the network in distributed embedded systems. Second, we present a toolchain to automatically translate the UML model into an intermediate description and then to SystemC executable code. Finally, the developed simulation framework is based on the state-of-the-art network simulator named SCNSL which also provides a comprehensive library of well-tested simulation models for communication networks. The framework is explained on two different case studies related to wired/wireless network applications, one for home automation and the other for agriculture applications.

关键词： UML SystemC embedded systems Network modeling simulation

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Hybrid code description for developing fast and resource efficient image processing architectures 16

Hybrid code description for developing fast and resource eff...

引用

16th international conference on embedded computer systems: architectures, modeling and simulation, SAMOS 2016

作者： Haublein, Konrad Reichenbach, Marc Reiche, Oliver Akif Ozkan, M. Fey, Dietmar Hannig, Frank Teich, Jurgen Computer Architecture Martensstraße 3 Erlangen91058 Germany Hardware-Software-Co-Design Cauerstraße 11 Erlangen91058 Germany

ISBN: (纸本)9781509030767

Image processing algorithms applied on programmable embedded systems very often do not meet the given constraints in terms of real time capability. Mapping these algorithms to reconfigurable hardware solves this issue, but demands further specific knowledge in hardware development. The design process can be accelerated by code generation through high-level synthesis, which is very flexible. However, the quality of synthesis depends on many factors like the provided constraints, code description, and algorithmic complexity. Hence, optimizing these parameters may improve the generated results in terms of logic and memory utilization, as well as data throughput and synthesis duration. In this work, we aim to exploit domain-specific knowledge for a hybrid code description in order to benefit from rapid development through high-level synthesis in combination with throughput optimized generic hardware descriptions. By utilizing code generation techniques, the entire design flow gets accelerated. Our synthesis results show a similar resource utilization and achievable throughput to a pure HDL described hardware. © 2016 IEEE.

关键词： Codes (symbols)

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Design Space Exploration in Application-Specific Hardware Synthesis for Multiple Communicating Nested Loops

Design Space Exploration in Application-Specific Hardware Sy...

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international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Corvino, Rosilde Gamatie, Abdoulaye Geilen, Marc Jozwiak, Lech Tech Univ Eindhoven POB 513 NL-5600 MB Eindhoven Netherlands CNRS LIFL Lille France

ISBN: (纸本)9781467322973;9781467322966

Application specific MPSoCs are often used to implement high-performance data-intensive applications. MP-SoC design requires a rapid and efficient exploration of the hardware architecture possibilities to adequately orchestrate the data distribution and architecture of parallel MPSoC computing resources. Behavioral specifications of data-intensive applications are usually given in the form of a loop-based sequential code, which requires parallelization and task scheduling for an efficient MPSoC implementation. Existing approaches in application specific hardware synthesis, use loop transformations to efficiently parallelize single nested loops and use Synchronous Data Flows to statically schedule and balance the data production and consumption of multiple communicating loops. This creates a separation between data and task parallelism analyses, which can reduce the possibilities for throughput optimization in high-performance data-intensive applications. This paper proposes a method for a concurrent exploration of data and task parallelism when using loop transformations to optimize data transfer and storage mechanisms for both single and multiple communicating nested loops. This method provides orchestrated application specific decisions on communication architecture, memory hierarchy and computing resource parallelism. It is computationally efficient and produces high-performance architectures.

关键词： Space Exploration Loops data distribution Custom design COMMUNICATING ARCHITECTURE Synclitism parallelism TASK SCHEDULING data transmission parallelization computer hardware Building construction

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A flash file system to support fast mounting for NAND flash memory based embedded systems

A flash file system to support fast mounting for NAND flash ...

引用

6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Park, Song-Hwa Lee, Tae-Hoon Chung, Ki-Dong Pusan Natl Univ Dept Comp Sci Pusan 609735 South Korea

ISBN: (纸本)3540364102

In embedded systems, NAND flash memory is typically used as a storage medium because of its non-volatility, fast access time and solid-state shock resistance. However, it suffers from out-place-up date, limited erase cycles and page based read/write operations. Flash file systems such as JFFS2 and YAFFS, allocate memory spaces using LFS (Log-structured File System) to solve these problems. Because of this, many pieces of a file are scattered through out flash memory. Therefore, these file systems should scan entire flash memory to construct the data structures during the mounting. This means that it takes a long time to mount such file systems on a large chip. In this paper, we design and propose a new flash memory file system which targets mobile devices that require fast mounting. We experimented on the file system performance and the results show that we improve the mounting time by 64%-76% as flash usage compared to YAFFS.

关键词： Flash memory

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ARAL-CR: An adaptive reasoning and learning cognitive radio platform

ARAL-CR: An adaptive reasoning and learning cognitive radio ...

引用

2010 10th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2010

作者： Chen, Sao-Jie Hsiung, Pao-Ann Yu, Chu Yen, Mao-Hsu Sezer, Sakir Schulte, Michael Hu, Yu-Hen Graduate Institute of Electronics Engineering National Taiwan University Taipei Taiwan Department of Computer Science and Information Engineering National Chung Cheng University Chiayi Taiwan Department of Electronic Engineering National ILan University ILan Taiwan Department of Computer Science and Engineering National Taiwan Ocean University Keelung Taiwan Institute of Electronics Communications and Information Technology Queen's University Belfast United Kingdom Department of Electrical and Computer Engineering University of Wisconsin-Madison Madison WI 53706 United States

ISBN: (纸本)9781424479382

This paper discusses the realization of a cognitive radio (CR) reconfigurable communication architecture and platform. In particular, four key research activities are presented: (1) the design of a reasoning and learning framework for CR adaptation, (2) a software-defined radio (SDR) baseband system using GNU Radio, (3) the design of a multi-band/multi-protocol RF front-end, and (4) the design of a reconfigurable baseband transceiver. ©2010 IEEE.

关键词： Cognitive radio

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RVfplib: A Fast and Compact Open-Source Floating-Point Emulation Library for Tiny RISC-V Processors 21st

RVfplib: A Fast and Compact Open-Source Floating-Point Emula...

引用

21st international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Perotti, Matteo Tagliavini, Giuseppe Mach, Stefan Bertaccini, Luca Benini, Luca Swiss Fed Inst Technol Gloriastr 35 CH-8092 Zurich Switzerland Univ Bologna Viale Risorgimento 2 I-40136 Bologna Italy

ISBN: (纸本)9783031045806;9783031045790

Small, low-cost IoT devices rely on floating-point (FP) software emulation on 32-bit integer cores when the cost of a full-fledged FPU is not affordable. Thus, the performance and code size of the FP emulation library are decisive for meeting energy and memory-size constraints. We propose RVfplib, the first ISA-optimized open-source library for single and double-precision IEEE 754 FP emulation on RV32IM[C] cores. RVfplib is 59% smaller and 2x faster than the GCC emulation library, on average. On benchmark programs, code size reduction is 39%, and performance boost 1.5x. RVfplib is 5.3% smaller than the leading closed-source RISC-V commercial library.

关键词： RISC-V embedded IoT Floating-point Library Size Performance

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