检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

2,721 篇 会议
57 册 图书
53 篇 期刊文献

馆藏范围

2,831 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,288 篇 工学
- 1,119 篇 计算机科学与技术...
- 591 篇 软件工程
- 286 篇 电气工程
- 158 篇 电子科学与技术（可...
- 150 篇 控制科学与工程
- 137 篇 信息与通信工程
- 50 篇 机械工程
- 44 篇 动力工程及工程热...
- 19 篇 仪器科学与技术
- 19 篇 建筑学
- 18 篇 材料科学与工程（可...
- 18 篇 安全科学与工程
- 17 篇 土木工程
- 16 篇 生物医学工程（可授...
- 14 篇 交通运输工程
- 14 篇 航空宇航科学与技...
- 13 篇 力学（可授工学、理...
- 12 篇 生物工程
- 11 篇 光学工程
275 篇 理学
- 173 篇 数学
- 81 篇 系统科学
- 38 篇 物理学
- 33 篇 统计学（可授理学、...
- 14 篇 化学
- 14 篇 生物学
142 篇 管理学
- 119 篇 管理科学与工程(可...
- 52 篇 工商管理
- 30 篇 图书情报与档案管...
21 篇 经济学
- 21 篇 应用经济学
20 篇 法学
- 20 篇 社会学
11 篇 医学
6 篇 教育学
5 篇 农学
3 篇 军事学
1 篇 文学
1 篇 艺术学

主题

763 篇 computational mo...
616 篇 computer archite...
361 篇 hardware
222 篇 embedded systems
144 篇 analytical model...
142 篇 embedded system
134 篇 computer simulat...
128 篇 application soft...
123 篇 mathematical mod...
116 篇 field programmab...
112 篇 real time system...
103 篇 program processo...
90 篇 embedded computi...
89 篇 kernel
84 篇 software
83 篇 computer science
82 篇 parallel process...
81 篇 registers
73 篇 control systems
72 篇 algorithm design...

机构

10 篇 school of electr...
9 篇 rhein westfal th...
8 篇 institute for co...
8 篇 center for embed...
7 篇 center for embed...
7 篇 department of co...
6 篇 eindhoven univer...
6 篇 computer systems...
6 篇 natl tech univ a...
6 篇 computer systems...
6 篇 institute for co...
6 篇 fraunhofer iese ...
5 篇 school of automa...
5 篇 school of electr...
5 篇 university of za...
5 篇 embedded systems...
5 篇 university of te...
5 篇 national cims en...
5 篇 the university o...
5 篇 eindhoven univer...

作者

19 篇 leupers rainer
16 篇 soudris dimitrio...
16 篇 ascheid gerd
14 篇 dimitrios soudri...
13 篇 rainer leupers
12 篇 gerd ascheid
12 篇 pimentel andy d.
11 篇 blume holger
11 篇 takala jarmo
11 篇 holger blume
10 篇 andy d. pimentel
10 篇 jung matthias
9 篇 mohamed abid
9 篇 fornaciari willi...
9 篇 pnevmatikatos di...
9 篇 kostas siozios
9 篇 christian haubel...
9 篇 andreas gerstlau...
9 篇 wehn norbert
8 篇 f. fummi

语言

2,818 篇 英文
8 篇 中文
5 篇 其他

检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

共 2831 条记录，以下是331-340 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

FPGA based application specific processing for sensor nodes

FPGA based application specific processing for sensor nodes

引用

2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Nyländen, Teemu Janhunen, Janne Hannuksela, Jari Silvén, Olli Computer Science and Engineering Laboratory University of Oulu Finland Centre for Wireless Communications University of Oulu Finland

ISBN: (纸本)9781457708008

Energy efficient sensor nodes are among the rapidly expanding applications for embedded systems technology. Typically, the processing resources in sensor nodes are based on programmable micro-controllers and digital signal processors, and the same processing architecture is used regardless of the actual task of the node. This regularly results in at least an order of magnitude over-provisioning of resources, and in higher power consumption than would be needed by tightly application specific processing solutions. Currently, experiments show that Flash FPGA technology enables implementing precisely provisioned processing for sensor nodes with energy efficiency that rivals off-the-shelf processor solutions. The expected competitiveness originates from savings in silicon real-estate, and lowered software overheads, as inherently parallel tasks can be offloaded to dedicated hardware accelerators on the same die with a microcontroller unit, and radio baseband. The results pave the way for a novel type of self-powered sensor nodes whose processing resources are configured according to their tasks. © 2011 IEEE.

关键词： Sensor nodes

来源：评论

学校读者我要写书评

暂无评论

A Critical Assessment of DRAM-PIM architectures - Trends, Challenges and Solutions 22nd

A Critical Assessment of DRAM-PIM Architectures - Trends, Ch...

引用

22nd international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Sudarshan, Chirag Sadi, Mohammad Hassani Steiner, Lukas Weis, Christian Wehn, Norbert TU Kaiserslautern Microelect Syst Design Res Grp Kaiserslautern Germany

ISBN: (纸本)9783031150746;9783031150739

Recently, we are witnessing a surge in DRAM-based Processing in Memory (PIM) publications from academia and industry. The architectures and design techniques proposed in these publications vary largely, ranging from integration of computation units in the DRAM IO region (i.e., without modifying DRAM core circuits) to modifying the highly optimized DRAM sub-arrays inside the banks for computation operations. Additionally, the underlying memory type, e.g., DDR4, LPDDR4, GDDR6 and HBM2, for DRAM-PIM is also different. This paper presents the assessment of DRAM-PIM architectural design decisions adapted in all DRAM-PIM publications. Our study presents an in-depth analysis of computation unit placement location, i.e., from the chip-level down to DRAM sub-array-level, and discusses the implementation challenges for a computation unit in various regions of commodity DRAM architectures. We also elaborate on the architectural bottlenecks associated with the scalability of DRAM-PIM performance and energy gains, and present architectural approaches to address the issues. Finally, our assessment covers other important design dimensions, such as computation data formats and DRAM-PIM memory controller design.

关键词： Processing-in-Memory PIM DRAM CNN DNN

来源：评论

学校读者我要写书评

暂无评论

embedded computer systems: architectures, modeling, and simulation 1

引用

丛书名： Lecture Notes in computer Science

1000年

作者： Alex Orailoglu Marc Reichenbach Matthias Jung

ISBN: (数字)9783031150746

ISBN: (纸本)9783031150739

This book constitutes the proceedings of the 22;international conference on embedded computer systems: architectures, modeling, and simulation, SAMOS 2021, which took place in July 2022 in Samos, Greece.;The 21 full papers presented in this volume were carefully reviewed and selected from 44 submissions. The papers are organized in topics as follows: High level synthesis; memory systems; processor architecture; embedded software systems and beyond; deep learning optimization; extra-functional property estimation; innovative architectures and tools for security; european research projects on digital systems, services, and platforms.

关键词： computer System Implementation Control Structures and Microprogramming Software Engineering/Programming and Operating systems Input/Output and Data Communications

来源：评论

学校读者我要写书评

暂无评论

MGSim-A simulation environment for multi-core research and education

MGSim-A simulation environment for multi-core research and e...

引用

2013 13th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2013

作者： Poss, Raphael Lankamp, Mike Yang, Qiang Fu, Jian Uddin, Man Jesshope, Chris R. University of Amsterdam Computer Systems Architecture Group Science Park 904 1098XH Amsterdam Netherlands

ISBN: (纸本)9781479901036

This article presents MGSim1, an open source discrete event simulator for on-chip hardware components developed at the University of Amsterdam. MGSim is used as research and teaching vehicle to study the fine-grained hardware/software interactions on many-core chips with and without hardware multithreading. MGSim's component library includes support for core models with different instruction sets, a configurable interconnect, multiple configurable cache and memory models, a dedicated I/O subsystem, and comprehensive monitoring and interaction facilities. The default model configuration shipped with MGSim implements Microgrids, a multi-core architecture with hardware concurrency management. MGSim is furthermore written mostly in C++ and uses object classes to represent chip components. It is optimized for architecture models that can be described as process networks. © 2013 IEEE.

关键词： C++ (programming language)

来源：评论

学校读者我要写书评

暂无评论

ImpBench revisited: An extended characterization of implant-processor benchmarks

ImpBench revisited: An extended characterization of implant-...

引用

2010 10th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2010

作者： Strydis, Christos Dave, Dhara Gaydadjiev, Georgi N. Computer Engineering Lab. Delft University of Technology P.O. Box 5031 2600 GA Delft Netherlands

ISBN: (纸本)9781424479382

Implants are nowadays transforming rapidly from rigid, custom-based devices with very narrow applications to highly constrained albeit multifunctional embedded systems. These systems contain cores able to execute software programs so as to allow for increased application versatility. In response to this trend, a new collection of benchmark programs for guiding the design of implant processors, ImpBench, has already been proposed and characterized. The current paper expands on this characterization study by employing a geneticalgorithm- based, design-space exploration framework. Through this framework, ImpBench components are evaluated in terms of their implications on implant-processor design. The benchmark suite is also expanded by introducing one new benchmark and two new stressmarks based on existing ImpBench benchmarks. The stressmarks are proposed for achieving further speedups in simulation times without polluting the processor-exploration process. Profiling results reveal that processor configurations generated by the stressmarks follow with good fidelity - except for some marked exceptions - ones generated by the aggregated ImpBench suite. Careful use of the stressmarks can seriously reduce simulation times up to x30, which is an impressive speedup and a good tradeoff between DSE speed and accuracy. ©2010 IEEE.

关键词： Genetic algorithms

来源：评论

学校读者我要写书评

暂无评论

NanoController: A Minimal and Flexible Processor Architecture for Ultra-Low-Power Always-On System State Controllers 22nd

NanoController: A Minimal and Flexible Processor Architectur...

引用

22nd international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Weissbrich, Moritz Paya-Vaya, Guillermo Tech Univ Carolo Wilhelmina Braunschweig Chair Chip Design Embedded Comp Muhlenpfordtstr 22-23 D-38106 Braunschweig Germany

ISBN: (纸本)9783031150746;9783031150739

Distributed nodes in IoT and wireless sensor networks, which are powered by small batteries or energy harvesting, are constrained to very limited energy budgets. By intelligent power management and power gating strategies for the main microcontroller of the system, the energy efficiency can be significantly increased. However, timer-based, periodical power-up sequences are too inflexible to implement these strategies, and the use of a programmable power management controller demands minimum area and ultra-low power consumption from this system part itself. In this paper, the NanoController processor architecture is proposed, which is intended to be used as a flexible system state controller in the always-on domain of smart devices. The NanoController features a compact ISA, minimal silicon area and power consumption, and enables the implementation of efficient power management strategies in comparison to much simpler and constrained always-on timer circuits. For a power management control application of an electronic door lock, the NanoController is compared to small state-of-the-art controller architectures and has up to 86% smaller code size and up to 92% less silicon area and power consumption for 65 nm standard cell ASIC implementations.

关键词： Instruction-set architecture Processor architecture Ultra-low-power microcontroller

来源：评论

学校读者我要写书评

暂无评论

Hard Edges: Hardware-Based Control-Flow Integrity for embedded Devices 21st

Hard Edges: Hardware-Based Control-Flow Integrity for Embedd...

引用

21st international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Christou, George Vasiliadis, Giorgos Athanasopoulos, Elias Ioannidis, Sotiris Fdn Res & Technol Hellas FORTH ICS Iraklion Greece Univ Cyprus Nicosia Cyprus Tech Univ Crete TUC ECE Khania Greece

ISBN: (纸本)9783031045806;9783031045790

Control-Flow Integrity (CFI) is a popular technique to defend against State-of-the-Art exploits, by ensuring that every (indirect) control-flow transfer points to a legitimate address and it is part of the Control-flow Graph (CFG) of a program. Enabling CFI in real systems is not straightforward, since in many cases the actual CFG of a program can only be approximated. Even in the case where there is perfect knowledge of the CFG, ensuring that all return instructions will return to their actual call sites, without employing a shadow stack, is questionable. In this work, we explore the implementation of a full-featured CFI-enabled Instruction Set Architecture (ISA) on actual hardware. Our new instructions provide the finest possible granularity for both intra-function and inter-function Control-Flow Integrity. We implement hardware-based CFI (HCFI) by modifying a SPARC SoC and evaluate the prototype on an FPGA board by running SPECInt benchmarks instrumented with a fine-grained CFI policy. HCFI can effectively protect applications from code-reuse attacks, while adding less than 1% average runtime and 2% power consumption overhead, making it particularly suitable for embedded systems.

关键词： System-on-chip

来源：评论

学校读者我要写书评

暂无评论

Performance Evaluation of the Intel Xeon Phi Manycore Architecture Using Parallel Video-Based Driver Assistance Algorithms 14

Performance Evaluation of the Intel Xeon Phi Manycore Archit...

引用

international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Arndt, Oliver Jakob Becker, Daniel Giesemann, Florian Paya-Vaya, Guillermo Bartels, Christopher Blume, Holger Leibniz Univ Hannover Inst Microelect Syst D-30167 Hannover Germany Siemens AG Corp Technol D-81739 Munich Germany

ISBN: (纸本)9781479937707

Computational-intensive algorithms are often realized with dedicated or customized hardware architectures suffering from high development costs and low flexibility thereafter. Instead, modern multicore and manycore processors can execute a diversity of software applications (e.g., driver assistance systems) written in portable high-level programming languages resulting in less porting effort at lower costs for power-consumption tolerant fields. For instance, the Intel Xeon Phi manycore processor featuring 61 cores offers not only a high theoretical peak performance but also a supportive tool chain for the software development in high-level programming languages. In contrast to traditional general-purpose multicore processors, this manycore architecture, however, exhibits different processor characteristics, inter-core communication topologies, and instruction sets. In this paper, we introduce the parallel implementation of a histogram of oriented gradients algorithm for pedestrian detection. Using a parallel semi-global matching algorithm as well, serving as an additional driver assistance algorithm, we present an in-depth performance analysis case study on the Intel Xeon Phi and also note distinct characteristics of this target platform. To allow a fair comparison, we not only rate an Intel Xeon 16-core general-purpose processor, but also present a platform comparison to customized hardware architectures.

关键词： PROCESSOR Performance Evaluation hardware architecture high-level programming languages ARCHITECTURE Software design computer software tool chain Driver Assistance systems Applications software Drivers histograms Parallel Lines Multi-core processors Building construction

来源：评论

学校读者我要写书评

暂无评论

On-chip bus modeling for power and performance estimation

引用

international conference on embedded computer systems - architectures, modeling and simulation

作者： Lee, Je-Hoon Cho, Young-Shin Kim, Seok-Man Cho, Kyoung-Rok Chungbuk Informat Technol Ctr CBNU BK21 Chungbuk South Korea Samsung SDI PDP Dev Team Cheonan South Korea CCNS Lab Cheongju Chugnbuk South Korea

ISBN: (纸本)9783540736226

This paper presented a latency and power model to determine the bus configuration of a target SoC system at its early design stage. The latency model analyzed the latencies of an on-chip bus and provided throughput reflecting the bus configuration. The power model provided power estimation based on the pre-determined bus architecture. This paper showed new parameters to devise the proposed models such as bus usage, active bridge ratio, etc. Moreover, we evaluated the throughput of the bus and compared this with the required throughput of the target SoC, including a number of real IPs. This target SoC was configured based on the estimation results obtained from the proposed bus model. This estimation were compared with the simulation results of target SoC design for verifying the accuracy of the proposed model. The evaluation showed that the accuracies of the proposed model for the latency and the power model were over 85% and 92%, respectively. This result set the standard for an efficient bus structure for a SoC design.

关键词： SoC on-chip bus bus modeling bus latency

来源：评论

学校读者我要写书评

暂无评论

A Toolchain for UML-based modeling and simulation of Networked embedded systems

A Toolchain for UML-based Modeling and Simulation of Network...

引用

UKSim-AMSS 15th international conference on computer Modelling and simulation (UKSim)

作者： Ebeid, Emad Fummi, Franco Quaglia, Davide Univ Verona Dep Comp Sci I-37100 Verona Italy

ISBN: (纸本)9780769549941;9781467364218

We present a toolchain to model and automatically generate executable simulation code for networked embedded systems applications. First, we provide a UML extension for modeling the network in distributed embedded systems. Second, we present a toolchain to automatically translate the UML model into an intermediate description and then to SystemC executable code. Finally, the developed simulation framework is based on the state-of-the-art network simulator named SCNSL which also provides a comprehensive library of well-tested simulation models for communication networks. The framework is explained on two different case studies related to wired/wireless network applications, one for home automation and the other for agriculture applications.

关键词： UML SystemC embedded systems Network modeling simulation

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共284页 << < 30 31 32 33 34 35 36 37 38 39 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：