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2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Almer, Oscar Böhm, Igor Von Koch, Tobias Edler Franke, Björn Kyle, Stephen Seeker, Volker Thompson, Christopher Topham, Nigel Institute for Computing Systems Architecture University of Edinburgh United Kingdom Software Engineering for Embedded Systems Group Technical University Berlin Germany

ISBN: (纸本)9781457708008

In recent years multi-core processors have seen broad adoption in application domains ranging from embedded systems through general-purpose computing to large-scale data centres. simulation technology for multi-core systems, however, lags behind and does not provide the simulation speed required to effectively support design space exploration and parallel software development. While state-of-the-art instruction set simulators (Iss) for single-core machines reach or exceed the performance levels of speed-optimised silicon implementations of embedded processors, the same does not hold for multi-core simulators where large performance penalties are to be paid. In this paper we develop a fast and scalable simulation methodology for multi-core platforms based on parallel and just-in-time (Jit) dynamic binary translation (Dbt). Our approach can model large-scale multi-core configurations, does not rely on prior profiling, instrumentation, or compilation, and works for all binaries targeting a state-of-the-art embedded multi-core platform implementing the ARCompact instruction set architecture (Isa). We have evaluated our parallel simulation methodology against the industry standard Splash-2 and Eembc MultiBench benchmarks and demonstrate simulation speeds up to 25,307 Mips on a 32-core 86 host machine for as many as 2048 target processors whilst exhibiting minimal and near constant overhead. © 2011 IEEE.

关键词： embedded systems

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Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform

Design space exploration of systolic realization of QR facto...

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2010 10th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2010

作者： Biswas, Prasenjit Varadarajan, Keshavan Alle, Mythri Nandy, S.K. Narayan, Ranjani CADL IISc Bangalore India Morphing Machines Bangalore India

ISBN: (纸本)9781424479382

In the world of high performance computing huge efforts have been put to accelerate Numerical Linear Algebra (NLA) kernels like QR Decomposition (QRD) with the added advantage of reconfigurability and scalability. While popular custom hardware solution in form of systolic arrays can deliver high performance, they are not scalable, and hence not commercially viable. In this paper, we show how systolic solutions of QRD can be realized efficiently on REDEFINE, a scalable runtime reconfigurable hardware platform. We propose various enhancements to REDEFINE to meet the custom need of accelerating NLA kernels. We further do the design space exploration of the proposed solution for any arbitrary application of size n x n. We determine the right size of the sub-array in accordance with the optimal pipeline depth of the core execution units and the number of such units to be used per sub-array. ©2010 IEEE.

关键词： Reconfigurable architectures

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FPGA based application specific processing for sensor nodes

FPGA based application specific processing for sensor nodes

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2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Nyländen, Teemu Janhunen, Janne Hannuksela, Jari Silvén, Olli Computer Science and Engineering Laboratory University of Oulu Finland Centre for Wireless Communications University of Oulu Finland

ISBN: (纸本)9781457708008

Energy efficient sensor nodes are among the rapidly expanding applications for embedded systems technology. Typically, the processing resources in sensor nodes are based on programmable micro-controllers and digital signal processors, and the same processing architecture is used regardless of the actual task of the node. This regularly results in at least an order of magnitude over-provisioning of resources, and in higher power consumption than would be needed by tightly application specific processing solutions. Currently, experiments show that Flash FPGA technology enables implementing precisely provisioned processing for sensor nodes with energy efficiency that rivals off-the-shelf processor solutions. The expected competitiveness originates from savings in silicon real-estate, and lowered software overheads, as inherently parallel tasks can be offloaded to dedicated hardware accelerators on the same die with a microcontroller unit, and radio baseband. The results pave the way for a novel type of self-powered sensor nodes whose processing resources are configured according to their tasks. © 2011 IEEE.

关键词： Sensor nodes

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Design of a Unified Transport Triggered Processor for LDPC/Turbo Decoder

Design of a Unified Transport Triggered Processor for LDPC/T...

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13th international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Shahabuddin, Shahriar Janhunen, Janne Bayramoglu, Muhammet Fatih Juntti, Markku Ghazi, Amanullah Silven, Olli Univ Oulu Dept Commun Engn SF-90100 Oulu Finland Univ Oulu Dept Comp Sci & Engn SF-90100 Oulu Finland

ISBN: (纸本)9781479901036

This paper summarizes the design of a programmable processor with transport triggered architecture (TTA) for decoding LDPC and turbo codes. The processor architecture is designed in such a manner that it can be programmed for LDPC or turbo decoding for the purpose of internetworking and roaming between different networks. The standard trellis based maximum a posteriori (MAP) algorithm is used for turbo decoding. Unlike most other implementations, a supercode based sum-product algorithm is used for the check node message computation for LDPC decoding. This approach ensures the highest hardware utilization of the processor architecture for the two different algorithms. Up to our knowledge, this is the first attempt to design a TTA processor for the LDPC decoder. The processor is programmed with a high level language to meet the time-to-market requirement. The optimization techniques and the usage of the function units for both algorithms are explained in detail. The processor achieves 22.64 Mbps throughput for turbo decoding with a single iteration and 10.12 Mbps throughput for LDPC decoding with five iterations for a clock frequency of 200 MHz.

关键词： computer architecture maximum likelihood estimation optimisation parity check codes turbo codes

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Current Analysis Approaches and Performance Needs for Whole Slide Image Processing in Breast Cancer Diagnostics 15

Current Analysis Approaches and Performance Needs for Whole ...

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international conference on embedded computer systems architectures modeling and simulation

作者： Pollanen, Irene Braithwaite, Billy Haataja, Keijo Ikonen, Tiia Toivanen, Pekka Univ Eastern Finland Sch Comp Kuopio Campus Kuopio Finland

ISBN: (纸本)9781467373111

In this paper, the current approaches and performance needs for whole slide image (WSI) analysis processing in breast cancer diagnostics are discussed. WSIs provide high resolution digital image data from the patient's diseased tissue. Digital whole slide images are typically very large and contain a high amount of information. Digitizing tissue specimen into the form of digital images allows the development and application of computational analysis algorithms. Biological tissues are complex with variance in tissue structures between healthy individuals as well as between patients with the same disease. Furthermore, the tissue preparation and digitization usually generates a lot of artifacts and more complexity, which causes classification challenges. This variance and also the large size of the images make creating an accurate and reliable automated breast cancer image analysis a challenge. In the ALMARVI project we aim at generating and implementing efficient histopathological image analysis algorithms in our breast cancer analysis scheme. This paper focuses on discussing relevant information concerning histopathological breast cancer diagnosis, and could also be considered as an introduction to the concept of WSI analysis to non-experts. Since the WSI sizes are very large (up to 40 GB with no compression) there are challenges on the computational analysis which requires computationally efficient tools and suitable approaches to relieve the problems caused by the large size of the images.

关键词： whole slide image breast cancer computer-aided diagnosis

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Reconfigurable computing for future vision-capable devices 15

Reconfigurable computing for future vision-capable devices

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15th international conference on embedded computer systems: architectures, modeling and simulation, SAMOS 2015

作者： López, Miguel Bordallo Nieto, Alejandro Silvén, Olli Bóutellier, Jani Vilariño, David López University of Oulu Finland CITIUS Universidad de Santiago de Compostela Spain

ISBN: (纸本)9781467373111

Mobile devices have been identified as promising platforms for interactive vision-based applications. However, this type of applications still pose significant challenges in terms of latency, throughput and energy-efficiency. In this context, the integration of reconfigurable architectures on mobile devices allows dynamic reconfiguration to match the computation and data flow of interactive applications, demonstrating significant performance benefits compared to general purpose architectures. This paper presents concepts laying on platform level adaptability, exploring the acceleration of vision-based interactive applications through the utilization of three reconfigurable architectures: A low-power EnCore processor with a Configurable Flow Accelerator co-processor, a hybrid reconfigurable SIMD/MIMD platform and Transport-Triggered Architecture-based processors. The architectures are evaluated and compared with current processors, analyzing their advantages and weaknesses in terms of performance and energy-efficiency when implementing highly interactive vision-based applications. The results show that the inclusion of reconfigurable platforms on mobile devices can enable the computation of several computationally heavy tasks with high performance and small energy consumption while providing enough flexibility. © 2015 IEEE.

关键词： Reconfigurable architectures

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Rapid implementation and optimisation of DSP systems on FPGA-centric heterogeneous platforms

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JOURNAL OF systems ARCHITECTURE 2007年第8期53卷 511-523页

作者： McAllister, J. Woods, R. Fischaber, S. Malins, E. Queens Univ Belfast ECIT Belfast BT3 9DT Antrim North Ireland

The emergence of programmable logic devices as single-chip heterogeneous processing platforms for digital signal processing applications poses challenges concerning rapid implementation and high level optimisation of algorithms on these platforms. This paper describes Abhainn, a rapid implementation methodology and toolsuite for translating an algorithmic expression of the system to a working solution on FPGA-centric embedded platforms. Two particular focuses for Abhainn are the automated but configurable reallisation of inter-processor communication fabrics, and the establishment of novel dedicated hardware component design methodologies allowing algorithm level transformation for system optimisation. This paper outlines the approaches employed in these areas and demonstrates their effectiveness on high end signal processing beamforming applications. (c) 2007 Elsevier B.V. All rights reserved.

关键词： FPGA DSP electronic system level design heterogeneous platform embedded computing

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SHARQ: Software-Defined Hardware-Managed Queues for Tile-Based Manycore architectures 19th

SHARQ: Software-Defined Hardware-Managed Queues for Tile-Bas...

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19th international conference on embedded computer systems: architectures, modeling, and simulation (SAMOS)

作者： Rheindt, Sven Maier, Sebastian Schmaus, Florian Wild, Thomas Schroeder-Preikschat, Wolfgang Herkersdorf, Andreas Tech Univ Munich TUM Arcisstr 21 D-80333 Munich Germany Friedrich Alexander Univ Erlangen Nurnberg FAU Schlosspl 4 D-91054 Erlangen Germany

ISBN: (纸本)9783030275624;9783030275617

The recent trend towards tile-based manycore architectures has helped to tackle the memory wall by physically distributing memories and processing nodes. Distributed operating systems and applications allow to exploit the increased scalability of such architectures, but still face the data-to-task locality challenge. As inter-tile communication, thread synchronization and data transport often impose significant software overhead on such architectures, many applications would benefit from a more efficient and powerful communication primitive with minimal software involvement. We propose software-defined hardware-managed queues for distributed computing architectures that enable efficient inter-tile communication by leveraging application-specific queues with arbitrarily sized elements. To ensure (remote) processing of queued elements, SHARQ introduces the concept of an optional handler task, which is scheduled by hardware on demand. Queue and memory management, intra- and inter-tile data transfer, and handler task invocation are entirely handled by hardware. Only the dynamic queue creation at runtime is performed in software. As an example use-case, we integrated SHARQ into the MPI library. The evaluation with the MPI-based NAS benchmarks shows a reduction in execution time by up to 48% for the communication intense IS kernel in a 4 x 4 tile design on an FPGA platform with a total of 80 LEON3 cores.

关键词： Distributed architectures Hardware accelerator Inter-tile communication Hardware/software codesign MPMC queue NoC

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The DESERVE project: Towards future ADAS functions 14

The DESERVE project: Towards future ADAS functions

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international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Kutila, Matti Pyykonen, Pasi van Koningsbruggen, Paul Pallaro, Nereo Perez-Rastelli, Joshue VTT Tech Res Ctr Finland Tampere Finland Technolution BV Gouda Netherlands Ctr Ric FIAT Turin Italy INRIA Le Chesnay France

ISBN: (纸本)9781479937707

This article introduces the objectives and structure of the European research project DESERVE that is co-funded by the ARTEMIS-JU and national funding bodies. The project started in September 2012 with a duration of 3 years. The project aims to establish a new embedded SW and HW design by using a more efficient development process (including the enabling general platform concept and tool chain) in order to overcome challenges in reducing component costs and development time of future ADAS functions for modern vehicles. Both the process and the platform concept will be demonstrated with innovative ADAS functions in 3 passenger cars, 1 truck and 1 motorcycle. embedded hardware and software units have been developed for improving electronic horizon band of vehicles by detecting objects in front. Moreover, driver/motorcycle rider awareness is analysed by monitoring his/her actions online. The systems need to be robust and reliable in different environment conditions (night time, rain, etc.). The DESERVE platform distinguishes three layers of intelligence: perception, application and intervention& warning control. The demonstrators will be based on software development tools from Elektrobit (ADTF) and Intempora (RTmaps). These tools are used to create 10 innovative ADAS applications as part of an integral ADAS development platform, following a new design and development process. Since the project is highly application oriented, the requirements have been adapted mainly from the ISO 26262 standard and the AUTOSAR framework which ensures compatibility with the existing automotive software environment.

关键词： automotive ADAS function driver monitoring camera traffic safety embedded systems

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Predictable Dynamic embedded Data Processing

Predictable Dynamic Embedded Data Processing

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international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Geilen, Marc Stuijk, Sander Basten, Twan Eindhoven Univ Technol Dept Elect Engn NL-5600 MB Eindhoven Netherlands

ISBN: (纸本)9781467322973;9781467322966

Cyber-physical systems interact with their physical environment. In this interaction, non-functional aspects, most notably timing, are essential to correct operation. In modern systems, dynamism is introduced in many different ways. The additional complexity threatens timely development and reliable operation. Applications often have different modes of operation with different resource requirements and different levels of required quality-of-service. Moreover, multiple applications in dynamically changing combinations share a platform and its resources. To preserve efficient development of such systems, dynamism needs to be taken into account as a primary concern, not as a verification or tuning effort after the design is done. This requires a model-driven design approach in which timing of interaction with the physical environment is taken into consideration;formal models capture applications and their platforms in the physical environment. Moreover, platforms with resources and resource arbitration are needed that allow for predictable and reliable behavior to be realized. Run-time management is further required to deal with dynamic use-cases and dynamic trade-offs encountered at run-time. In this paper, we present a model-driven approach that combines model-based design and synthesis with development of platforms that support predictable, repeatable, composable realizations and a run-time management approach to deal with dynamic use-cases at run-time. A formal, compositional model is used to exploit Pareto-optimal trade-offs in the system use. The approach is illustrated with dataflow models with dynamic application scenarios, a predictable platform architecture and run-time resource management that determines optimal trade-offs through an efficient knapsack heuristic.

关键词： Runtime physical environment Platform resource requirements operation mode Time Management management of resources Surgery dynamism

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