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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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The impact of the AC922 Architecture on Performance of Deep Neural Network Training

The impact of the AC922 Architecture on Performance of Deep ...

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international conference on High Performance Computing & simulation (HPCS)

作者： Paweł Rościszewski Michał Iwański Paweł Czarnul Faculty of Electronics Telecommunications and Informatics Gdańsk University of Technology Poland IBM Systems IBM Poland

ISBN: (数字)9781728144849

ISBN: (纸本)9781728144856

Practical deep learning applications require more and more computing power. New computing architectures emerge, specifically designed for the artificial intelligence applications, including the IBM Power System AC922. In this paper we confront an AC922 (8335-GTG) server equipped with 4 NVIDIA Volta V100 GPUs with selected deep neural network training applications, including four convolutional and one recurrent model. We report performance results depending on batch sizes and GPU selection and compare them with the results from another contemporary workstation based on the same set of GPUs - NVIDIA® DGX Station ™ . The results show that the AC922 performs better in all tested configurations, achieving improvements up to 10.3%. Profiling indicates that the improvement is due to the efficient I/O pipeline. The performance differences depend on the specific model, rather than on the model class (RNN/CNN). Both systems offer good scalability up to 4 GPUs. In certain cases there is a significant difference in performance depending on exactly which GPUs are used for computations.

关键词： Training Servers computer architecture Bandwidth Computational modeling Benchmark testing Machine learning

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Design Space Exploration of embedded Applications on Heterogeneous CPU-GPU Platforms

Design Space Exploration of Embedded Applications on Heterog...

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international conference on High Performance Computing & simulation (HPCS)

作者： Abdullah Siddiqui Gul N. Khan Electrical Computer and Biomedical Engineering Ryerson University Toronto Ontario Canada

ISBN: (数字)9781728144849

ISBN: (纸本)9781728144856

CPU-GPU platforms possess the potential of enhancing the performance of applications through some unique and diverse capabilities of both CPU-GPU devices. As a result, the methodologies for CPU/GPU system design space exploration for various applications are now considerably more challenging on these heterogeneous platforms. In this paper, we present a heuristic algorithm for partitioning the computation of applications between a CPU and GPU, while satisfying the user-defined constraints. Our methodology leverages the SIMD-related computing and hierarchical memory model of GPUs to optimize application mapping and allocation to CPU-GPU systems. The algorithm partitions the application, which is specified as a Directed Acyclic Graph (DAG), for a CPU-GPU platform to meet the objectives specified by the user. The effectiveness of our methodology is demonstrated by efficiently partitioning and executing MJPEG decoder and benchmark applications on a CPU-GPU system.

关键词： Graphics processing units Task analysis Partitioning algorithms Genetic algorithms Computational modeling Resource management Parallel processing

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Numerical simulation of transient air flow in a large scale high density data centers 14th

Numerical simulation of transient air flow in a large scale ...

引用

14th international Energy Conversion Engineering conference, IECEC 2018

作者： Khalil, Essam E. Rahman, Yousri Abd El Maksoud, Waleed Abdel M.elbialy, Esmail Cairo University Cairo Egypt

ISBN: (数字)9781624105715

ISBN: (纸本)9781624105715

computer systems have been a source of high power dissipation either from microprocessors, memory and support chips and mass storage. A high thermal density data center using these computer systems has resulted in a very high power density at room level. These computer systems are represented by and included in a rack. Normally a standard rack is two meters high and can accommodate an equivalent of 34 thin desktop computer systems. If each system consumes around 300 W, a standard rack in a data center can consume up to 7.2 kW. While a data center can be consisted of hundreds of racks, this results in very high heat dissipation in the data center. For the racks to operate at normal operating conditions, a suitable air conditioning system should be designed to remove the high heat dissipation. Using simple energy balance and steady state analysis is no longer adequate to rely on for a proper design and analysis of air flow and temperature distributions in a data center. In this paper, a computational fluid dynamics (CFD) model of a prototype data center is presented to make the case for such modeling. The study is carried out using CFD simulation techniques as embedded in the commercially available CFD code (ANSYS V.16). The CFD modeling techniques solved the continuity, momentum and energy conservation equations in addition to standard k – Ε model equations for turbulence closure. © 2018, American Institute of Aeronautics and Astronautics Inc, AIAA. All rights reserved.

关键词： Computational fluid dynamics

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A Multi-agent simulation for the Research on the Market Equilibrium Phenomena Using Q-Network Algorithm

A Multi-agent Simulation for the Research on the Market Equi...

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international conference on Communication Technology (ICCT)

作者： Jinyan Wang Bo Chen College of Mathematics and Computer Science Fuzhou University Fuzhou Fujian Province China

For the problems related to market equilibrium in complex market environments, analyses are conducted in the past, using some mathematical models and the game theory. These methods are based on the economic structural equations themselves, ignoring the interactions between economic subjects, and the hypothesis of subject homogeneity has no reference in the real world. On contrast, this paper proposes a multi-agent simulation model, from the microscopic point of view. In such simulation, agents interact with each other, and the decisions are made by agent-embedded AI systems, the Q-network. Therefore, there is no need to elaborate the behavioral rule for each agent, or manually set up too many assumptions. This paper assumes that the simulated market operates in a hypothetical way, in which there are two types of economic entities, namely, banks and enterprises. Banks and enterprises lending behaviors lead to a symbiotic relationship between the banks and the enterprises, while business-to-business transactions make the enterprises symbiotically compete with each other. In the experiment, the observed behavior of each agent can be reasonably explained. Agents endogenously generate intelligent behavioral patterns compatible with the environment. Therefore, this AI-based method can replace the artificially designated decision-making strategy in simulations of market, thus facilitating related economic researches.

关键词： Economics Mathematical model Companies Decision making Markov processes Training Computational modeling

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Improving MPI reduction performance for manycore architectures with OpenMP and data compression

Improving MPI reduction performance for manycore architectur...

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2018 IEEE/ACM Performance modeling, Benchmarking and simulation of High Performance computer systems, PMBS 2018

作者： Shan, Hongzhang Williams, Samuel Johnson, Calvin W. Computational Research Division Lawrence Berkeley National Laboratory BerkeleyCA94720 United States Department of Physics San Diego State University San DiegoCA92182 United States

ISBN: (纸本)9781728101828

MPI reductions are widely used in many scientific applications and often become the scaling performance bottleneck. When performing reductions on vectors, different algorithms have been developed to balance messaging overhead and bandwidth. However, most implementations have ignored the effect of single-thread performance not scaling as fast as aggregate network bandwidth. In this work, we propose, implement, and evaluate two approaches (threading and exploitation of sparsity) to accelerate MPI reductions on large vectors when running on manycore-based supercomputers. Our benchmark results show that our new techniques improve the MPI-Reduce performance up to 4 × and improve BIGSTICK application performance by up to 2.6 ×. © 2018 IEEE.

关键词： Supercomputers

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Hiding Side-channel Leakage through Hardware Randomization: a Comprehensive Overview 17

Hiding Side-channel Leakage through Hardware Randomization: ...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Mentens, Nele Katholieke Univ Leuven IMEC COSIC Kasteelpark Arenberg 10 B-3001 Leuven Belgium

ISBN: (纸本)9781538634370

This paper gives (i) an overview of the reconfiguration capabilities of modern hardware devices and (ii) a summary and comparison of hardware architectures that use random reconfiguration as a countermeasure against side-channel attacks. We categorize the architectures according to their suitability for specic hardware platforms. Further, we compare the reconfiguration methods and the attacks that the countermeasures protect against. Although the presented randomization countermeasures can usually be applied to a broad range of algorithms, evaluation results are presented for specific cryptographic algorithms. In most cases, randomization countermeasures can be combined with other countermeasures that are tailored to specific algorithms.

关键词： Field programmable gate arrays Hardware Table lookup Cryptography Power demand Registers Field programmable gate arrays Table lookup computer hardware Power demand Registers cryptography Randomisation Reconfiguration channel leak Hardware Platform ARCHITECTURE

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Translation Validation of Code Generation from the SIGNAL Data-Flow Language to Verilog

Translation Validation of Code Generation from the SIGNAL Da...

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international conference on Semantics, Knowledge and Grid (SKG)

作者： Hafiz Muhammad Amjad Kai Hu Jianwei Niu Noor Khan Loïc Besnard Jean-Pierre Talpin School of Computer Science & Engineering Beihang University Beijing China IRISA Rennes France INRIA Campus de Beaulieu Rennes France

ISBN: (数字)9781728158235

ISBN: (纸本)9781728158242

The SIGNAL is a high-level synchronous data-flow language for the design and implementation of safety-critical embedded systems. It provides a unified framework for specification, modeling, formal analysis, and automatic code generation for different general-purpose languages like Java, C, and C++. However, fully implemented and verified open source tool for code generation from SIGNAL to Hardware Description Language (HDL) is not available. This paper describes the formal verification of the generated Verilog code from the SIGNAL language. Proving the correctness of generated code is very important when it is for safety-critical embedded systems. We use the translation validation technique for verifying the correctness of the generated code. In this approach, the Polychrony Toolset builds the models of source SIGNALprograms with its associated model checker SIGALI. The open source tool Yosys generates models for target Verilog programs in the SMT-LIB standard format. We transform the model generated by Yosys to the model accepted by the SIGALI model checker. Finally, we use the SIGALI model checker to validate the translation by symbolic simulation between both source and target program models. The target program may have fewer behaviors than the source program therefore if the model of the target program implies the model of the source program, it means the target program preserves the semantics of the source program, and the translation is correct.

关键词： Hardware design languages Mathematical model Clocks Semantics Tools embedded systems Encoding

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modeling Traffic Workloads in Data-center Network simulation Tools

Modeling Traffic Workloads in Data-center Network Simulation...

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international conference on High Performance Computing & simulation (HPCS)

作者： Luis Gonzalez-Naharro Jesus Escudero-Sahuquillo Pedro J. García Francisco J. Quiles Jose Duato Wenhao Sun Xiang Yu Hewen Zheng Department of Computing Systems University of Castilla-La Mancha Spain Universitat Politècnica de València Spain Huawei Technologies Co. Ltd. China

ISBN: (数字)9781728144849

ISBN: (纸本)9781728144856

POSTER PAPER Data-centers are commonly used by most important cloud providers worldwide in order to provide storage and computing resources, and, based on these resources, advanced IT services and applications. With the expected explosion of data in the next few years, Data-centers will require new architectures to cope with the new requirements of applications and users. One of the crucial subsystems within the Data-center architecture that must evolve accordingly to the new requirements is the interconnection network or Data-center network (DCN). The DCN performance (basically, high communication bandwidth and low latency) must be guaranteed, otherwise the DCN becoming the system bottleneck. There are several key issues that DCN designers must make decisions on, such as the network topology, routing algorithm, congestion management, etc. An important aspect that impacts on the DCN design are the network communication patterns generated by applications and services. In that sense, an accurate modeling of these traffic workloads would help network designers to make better decisions. In this paper, we present an analysis of the few available studies on traffic modeling for DCNs, in order to gather a set of parameters that define the behaviour of common traffic workloads. Based on these parameters, we have implemented a synthetic DCN traffic generator, which has been included in our simulation framework in order to feed the network with the inferred traffic workloads. We have conducted extensive simulations to test the impact of the parameter variation on the network performance. From the obtained results, we can conclude that the destination distribution is crucial for the network performance. Higher oversubscription of destinations generates incast scenarios that lead to congestion situations and head-of-line blocking, affecting other flows that do not contribute to the incast situation and so spoiling the network performance.

关键词： Facebook computer architecture Bandwidth Analytical models Web servers Load modeling

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SysRT: A Modular Multiprocessor RTOS Simulator for Early Design Space Exploration 17

SysRT: A Modular Multiprocessor RTOS Simulator for Early Des...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Xiao, Jun Pimentel, Andy Lipari, Giuseppe Univ Amsterdam Amsterdam Netherlands Univ Lille Lille France

ISBN: (纸本)9781538634370

Modern embedded systems increasingly accommodate several applications running concurrently on a multiprocessor platform managed by a real-time operating system (RTOS). The increasing design complexity of such systems calls for good design tools to evaluate real-time performance during the very early stages of design. To this end, fast system-level simulators that allow for efficient hardware/software co-simulation are essential. In this paper, we present SysRT, a generic and high-level RTOS simulator that is highly suited for early design space exploration (DSE). The simulator contains different types of application models and a modular RTOS kernel model, all developed in SystemC. Efficient and precise modeling of preemptive scheduling is achieved via an event-driven simulation approach, allowing simulations to be performed much faster than cycle-accurate simulations. At the same time, the kernel model is developed to be generic and modular to support for easy plug-in of new schedulers as well as new resource sharing protocols. Comparing SysRT with state-of-art simulators, it achieves faster simulation speeds with an identically small simulation error. We demonstrate the flexibility of SysRT and its benefits for early DSE using experiments with a mixed workload executing on multiprocessor platforms with different numbers of cores.

关键词： Task analysis Kernel Real-time systems Unified modeling language computer architecture Timing Computational modeling UML task analysis computer Architecture real-time systems Computational modeling Space Exploration simulator Kernel Modularity Multiprocessor Seeds analog error

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Run-time Mapping Algorithm for Dynamic Workloads using Process Merging Transformations 17

Run-time Mapping Algorithm for Dynamic Workloads using Proce...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Sinaei, Sima Fatemi, Omid Pimentel, Andy D. Univ Tehran Tehran Elect & Comp Dept Tehran Iran Univ Amsterdam Informat Inst Amsterdam Netherlands

ISBN: (纸本)9781538634370

Exploration of task mappings has an important role to achieve high performance in heterogeneous multi-processor system-on-chip (MPSoC) platforms. The application workloads in modern MPSoC-based embedded systems are becoming increasingly dynamic. Different applications concurrently execute and contend for resources in such systems. In this paper, a run-time algorithm is proposed to analytically evaluate the system throughput of to-be-executed applications (modelled as Kahn Process Networks, KPNs) in order to quickly determine a proper resource binding for these applications. Merging transformations on the KPNs are applied to capture the cases in which the number of processes in the KPN is larger than the number of available processing resources, thereby modeling the effects of binding multiple processes to a single processor. We evaluated our algorithm using a heterogeneous MPSoC system with several applications. Our experimental results revealed that during runtime, the performance of selected mapping with regard to available resources is close to the optimal performance obtained by exhaustive search and simulation. Therefore, the results clearly confirm that our algorithm is effective.

关键词： embedded systems multiprocessor-systems-on-chip (MPSoCs) run-time mapping design space exploration of heterogeneous MPSoCs process merging performance evaluation

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