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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

共 2831 条记录，以下是361-370 订阅

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NanoController: A Minimal and Flexible Processor Architecture for Ultra-Low-Power Always-On System State Controllers 22nd

NanoController: A Minimal and Flexible Processor Architectur...

引用

22nd international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Weissbrich, Moritz Paya-Vaya, Guillermo Tech Univ Carolo Wilhelmina Braunschweig Chair Chip Design Embedded Comp Muhlenpfordtstr 22-23 D-38106 Braunschweig Germany

ISBN: (纸本)9783031150746;9783031150739

Distributed nodes in IoT and wireless sensor networks, which are powered by small batteries or energy harvesting, are constrained to very limited energy budgets. By intelligent power management and power gating strategies for the main microcontroller of the system, the energy efficiency can be significantly increased. However, timer-based, periodical power-up sequences are too inflexible to implement these strategies, and the use of a programmable power management controller demands minimum area and ultra-low power consumption from this system part itself. In this paper, the NanoController processor architecture is proposed, which is intended to be used as a flexible system state controller in the always-on domain of smart devices. The NanoController features a compact ISA, minimal silicon area and power consumption, and enables the implementation of efficient power management strategies in comparison to much simpler and constrained always-on timer circuits. For a power management control application of an electronic door lock, the NanoController is compared to small state-of-the-art controller architectures and has up to 86% smaller code size and up to 92% less silicon area and power consumption for 65 nm standard cell ASIC implementations.

关键词： Instruction-set architecture Processor architecture Ultra-low-power microcontroller

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Profiling Dilithium Digital Signature Traces for Correlation Differential Side Channel Attacks 20th

Profiling Dilithium Digital Signature Traces for Correlation...

引用

20th international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Fournaris, Apostolos P. Dimopoulos, Charis Koufopavlou, Odysseas Res Ctr ATHENA Ind Syst Inst Patras Sci Pk Patras Greece Univ Patras Elect & Comp Engn Dept Rion Campus Patras Greece

ISBN: (纸本)9783030609399;9783030609382

A significant concern for the candidate schemes of the NIST postquantum cryptography standardization project is the protection they support against side-channel attacks. One of these candidate schemes currently in the NIST standardization race is the Dilithium signature scheme. This postquantum signature solution has been analyzed for side channel attack resistance especially against timing attacks. Expanding our attention on other types of side-channel analysis, this work is focused on correlation based differential side channel attacks on the polynomial multiplication operation of Dilithium digital signature generation. In this paper, we describe how a Correlation Power Attack should be adapted for the Dilithium signature generation and describe the attack process to be followed. We determine the conditions to be followed in order for such an attack to be feasible, (isolation of polynomial coefficient multiplication inpower traces) and we create a power trace profiling paradigm for the Dilithium signature scheme executed in embedded systems to showcase that the conditions can be met in practice. Expanding the methodology of recent works that mainly use simulations for power trace collection, in this paper, power trace capturing and profiling analysis of the signature generation process was succesfully done on a, noisy, Commercial off-the-shelf ARM Cortex-M4 embedded system.

关键词： Postquantum cryptography Side channel attack Secure embedded systems

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Towards scalable I/O on a many-core architecture

Towards scalable I/O on a many-core architecture

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2010 10th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2010

作者： Hicks, Michael A. Van Tol, Michiel W. Jesshope, Chris R. Informatics Institute University of Amsterdam Netherlands

ISBN: (纸本)9781424479382

The limitations of conventional processor performance scaling mean that general purpose many-core processors are increasingly becoming a reality. Conventional hardware device input/output (I/O), interrupt handling and operating system stacks scale poorly and are inefficient when compared with the parallelism that these architectures provide. Many-core I/O requires a decentralised approach where not every core is directly connected to the I/O infrastructure. As such, this paper discusses a software and hardware model designed to take full advantage of I/O parallelism in the Self-adaptive Virtual Processor (SVP) concurrency model and the Microgrid many-core architecture. The generic software I/O stack presented describes a high-level method by which clients and I/O resources can communicate and synchronise in a parallel and decentralised environment. The associated hardware implementation provides a facility to the higher-level interface through the introduction of specialised I/O Cores which enable direct high-speed communication between external devices and the bespoke on-chip Cache-Only Memory Architecture (COMA). ©2010 IEEE.

关键词： Parallel architectures

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Reconfigurable multiple operation array

Reconfigurable multiple operation array

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5th international Workshop on embedded computer systems - architectures, modeling, and simulation

作者： Calderon, H Vassiliadis, S Delft Univ Technol EEMCS Comp Engn Lab Dept Elect Engn Delft Netherlands

ISBN: (纸本)354026969X

In this paper, we investigate the collapsing of eight multi-operand addition related operations into a single and common (3:2) counter array. We consider for this unit multiplication in integer and fractional representations, the Sum of Absolute Differences (SAD) in unsigned, signed magnitude and two's complement notation. Furthermore, the unit also incorporates a Multiply-Accumulation unit, (MAC) for two's complement notation. The proposed multiple operation unit was constructed around 10 element arrays that can be reduced using well known counter techniques, which are feed with the necessary data to perform the proposed eight operations: It is estimated that 6/8 of the basic (3:2) counter array is shared by the operations. The obtained results of the presented unit indicates that is capable of processing a 4x4 SAD macro-block in 36.35 ns and takes 30.43 ns to process the rest of the operations using a VIRTEX 11 PRO xc2vp100-7ff1696 FPGA device.

关键词： embedded systems

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High-Level Synthesis of Digital Circuits from Template Haskell and SDF-AP 22nd

High-Level Synthesis of Digital Circuits from Template Haske...

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22nd international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Folmer, H. H. de Groote, R. Bekooij, M. J. G. Univ Twente CAES Comp Architectures Embedded Syst Enschede Netherlands Sax Hogesch Enschede Netherlands

ISBN: (纸本)9783031150746;9783031150739

Functional languages as input specifications for HLS-tools allow to specify data dependencies but do not contain a notion of time nor execution order. In this paper, we propose a method to add this notion to the functional description using the dataflow model SDF-AP. SDF-AP consists of patterns that express consumption and production that we can use to enforce resource usage. We created an HLS-tool that can synthesize parallel hardware, both data and control path, based on the repetition, expressed in Higher-Order Functions, combined with specified SDF-AP patterns. Our HLS-tool, based on Template Haskell, generates an Abstract Syntax Tree based on the given patterns and the functional description uses the Clash-compiler to generate VHDL/Verilog. Case studies show consistent resource consumption and temporal behavior for our HLS-tool. A comparison with a commercially available HLS-tool shows that our tool outperforms in terms of latency and sometimes in resource consumption. The method and tool presented in this paper offer more transparency to the developer and allow to specify more accurately the synthesized hardware compared to what is possible with pragmas of the Vitis HLS-tool.

关键词： High level synthesis

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Hybrid functional and instruction level power modeling for embedded processors

Hybrid functional and instruction level power modeling for e...

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6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Blume, Holger Becker, Daniel Botteck, Martin Brakensiek, Joerg Noll, Tobias G. Univ Aachen Rhein Westfal TH Aachen Chair Elect Engn & Comp Syst D-52062 Aachen Germany Nokia Res Ctr D-44807 Bochum Germany

ISBN: (纸本)3540364102

In this contribution the concept of Functional-Level Power Analysis (FLPA) for power estimation of programmable processors is extended in order to model even embedded general purpose processors. The basic FLPA approach is based on the separation of the processor architecture into functional blocks like e.g. processing unit, clock network, internal memory etc. The power consumption of these blocks is described by parameterized arithmetic models. By application of a parser based automated analysis of assembler codes the input parameters of the arithmetic functions like e.g. the achieved degree of parallelism or the kind and number of memory accesses can be computed. For modeling an embedded general purpose processor (here, an ARM940T) the basic FLPA modeling concept had to be extended to a so-called hybrid functional level and instruction level model in order to achieve a good modeling accuracy. The approach is exemplarily demonstrated and evaluated applying a variety of basic digital signal processing tasks ranging from basic filters to complete audio decoders. Estimated power figures for the inspected tasks are compared to physically measured values. A resulting maximum estimation error of less than 8 % is achieved.

关键词： Program processors

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Software/network Co-simulation of heterogeneous industrial networks architectures

Software/network Co-simulation of heterogeneous industrial n...

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Proceedings - IEEE international conference on computer Design: VLSI in computers and Processors, ICCD 2004

作者： Fummi, F. Martini, S. Monguzzi, M. Perbellini, G. Poncino, M. Universitá di Verona Verona Italy Sitek S.p.A S.G. Lupatoto Italy Embedded Systems Design Center Verona Italy

ISBN: (纸本)0769522319

The work presents a modeling and analysis framework for heterogeneous industrial networks architectures which is based on a tight integration of a network simulator with embedded software, middleware and a real-time operating system. This framework is suitable for modeling and simulating the behavior of typical components involved in factory automation applications (e.g., PLCs, remote controllers, operational screens, etc.) when they are connected through heterogeneous industrial networks. Experiments show that the framework allows to take early architectural decisions by evaluating the expected system performance based on the available models. © 2004 IEEE.

关键词： computer architecture

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simulation OF embedded computer CODE.

SIMULATION OF EMBEDDED COMPUTER CODE.

引用

Proceedings of the 1985 Summer computer simulation conference.

作者： Wells, Brian H. Raytheon Co Bedford MA USA Raytheon Co Bedford MA USA

ISBN: (纸本)0317609459

The composition of defense systems is becoming more software oriented every day. New system architectures are taking maximum advantage of reductions in computer costs and increased memory and throughput capabilities. Existing systems are being converted from purely hardware systems to hybrid system that use computers for many of the decision and control functions. This paper reviews the system development process and presents five options for modeling computer software embedded in hybrid systems. The utility and fidelity with the actual system provided by each modeling option are discussed. Then the cost and schedule, for developing a simulation for an example system, are determined and used to perform an evaluation of the modeling options. The evaluation shows that two of the modeling options are undesirable, based on cost. Based on schedule constraints, the remaining three options should be used in an evolutionary manner to provide the necessary simulation capabilities early in the system development process.

关键词： computer simulation

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RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM 19th

RRAMSpec: A Design Space Exploration Framework for High Dens...

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19th international conference on embedded computer systems: architectures, modeling, and simulation (SAMOS)

作者： Mathew, Deepak M. Chinazzo, Andre Lucas Weis, Christian Jung, Matthias Giraud, Bastien Vivet, Pascal Levisse, Alexandre Wehn, Norbert Tech Univ Kaiserslautern Kaiserslautern Germany Fraunhofer Inst Expt Software Engn IESE Kaiserslautern Germany Univ Grenoble Alpes CEA LETI MINATEC Campus Grenoble France Ecole Polytech Fed Lausanne Embedded Syst Lab ESL Lausanne Switzerland

ISBN: (纸本)9783030275624;9783030275617

Resistive RAM (RRAM) is a promising emerging Non-Volatile Memory candidate due to its scalability and CMOS compatibility, which enables the fabrication of high density RRAM crossbar arrays in Back-End-Of-Line CMOS processes. Fast and accurate architectural models of RRAM crossbar devices are required to perform system level design space explorations of new Storage Class Memory (SCM) architectures using RRAM e.g. Non-Volatile-DIMM-P (NVDIMM-P). The major challenge in architectural modeling is the trade-off between accuracy and computing intensity. In this paper we present RRAMSpec, an architecture design space exploration framework, which enables fast exploration of various architectural trade-offs in designing high density RRAM devices, at accuracy levels close to circuit level simulators. The framework estimates silicon area, timings, and energy for RRAM devices. It outperforms state-of-the-art RRAM modeling tools by conducting architectural explorations at very high accuracy levels within few seconds of execution time. Our evaluations show various trade-offs in designing RRAM crossbar arrays with respect to array sizes, write time and write energy. Finally we present the influence of technology scaling on different RRAM design trade-offs.

关键词： RRAM ReRAM Crossbar NVM

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Efficient and effective simulation of memory maps for system-on-chip

Efficient and effective simulation of memory maps for system...

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11th IEEE international conference and Workshop on Engineering of computer-Based systems (ECBS 2004)

作者： Luculli, G

ISBN: (纸本)0769521258

dThe design of complex system-on-chip (SOC) requires new methods and tools for the optimization of embedded software which is executed on ever more complex hardware architectures. The tuning of the memory subsystem is particularly difficult due to the many design parameters which are involved and the long time which is required to simulate different design configurations. In this paper, we propose a very effective mechanism for the simulation of generic memory maps on architectures with instruction and/or data cache memory. An important characteristic of our implementation is its large flexibility: any memory map and any cache configuration can be simulated without the need to modify or to re-compile the application code. We implemented such mechanism in our ISA retargetable environment and we showed that it loosely impacts the simulation performance.

关键词： embedded systems

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