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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

共 2831 条记录，以下是361-370 订阅

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Exploring Different Execution Paradigms in Exposed Datapath architectures with Buffered Processing Units 17

Exploring Different Execution Paradigms in Exposed Datapath ...

引用

17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Bhagyanath, Anoop Schneider, Klaus Univ Kaiserslautern Dept Comp Sci Kaiserslautern Germany

ISBN: (纸本)9781538634370

Exposed datapath processor architectures allow the software to bypass register usage by directly moving intermediate results between processing units with suitable instructions. Synchronous Control Asynchronous Dataflow (SCAD) is a new exposed datapath architecture consisting of a grid of processing units with buffers to store their input and output values. Code generation inspired from queue machines can utilize the bypassing capability of such exposed datapath architectures with buffered processing units and can completely eliminate the use of registers this way. In this paper, we consider different execution paradigms of SCAD that make a compromise between hardware complexity, hardware scalability, and the use of instruction-level parallelism. To that end, we study both resource- and time-optimal code for all variants that we determine by satisfiability modulo theories (SMT) solvers. Experimental results show that the execution paradigm followed by our original SCAD architecture makes a reasonable compromise between hardware complexity and the use of instruction-level parallelism while maintaining hardware scalability.

关键词： computer architecture Registers Buffer storage Hardware Scalability Encoding Complexity theory Registers computer hardware BUFFER STORAGE Scalability computer Architecture Complexity theory instruction-level parallelism ARCHITECTURE Legal Executions

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Extraction of Recursion Level Parallelism for embedded Multicore systems 17

Extraction of Recursion Level Parallelism for Embedded Multi...

引用

17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Aguilar, Miguel Angel Leupers, Rainer Ascheid, Gerd Eusse, Juan Fernando Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst Aachen Germany Silex GmbH Herne Germany

ISBN: (纸本)9781538634370

Recursive programs that typically implement divide-and-conquer algorithms are well-suited for multicore systems, as they offer a high degree of parallelization potential. So far, existing parallelizing compilers have mainly focused on extracting other parallel patterns, such as data or pipeline level parallelism. In this paper, we propose a toolflow for the extraction of recursion level parallelism for embedded multicore systems. To achieve this, the toolflow verifies not only the mutual independence of recursive call-sites, but also selects an appropriate task granularity to ensure a good trade-off between load balancing and parallelization overhead. Profitable parallelization opportunities are implemented by using compiler directives from the OpenMP tasking model. Results show the effectiveness of our toolflow, as it is able to speedup sequential recursive programs between 2.5x and 3.8x on a quad-core platform.

关键词： Task analysis Multicore processing Parallel processing Analytical models Performance analysis Static analysis Load management task analysis load management PARALLEL PROCESSING (computerS) ANALYSIS MODELS Multi-core processors parallelism Synclitism Recursion Recursive Procedure parallelizing compilers parallelization

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A New State Model for DRAMs Using Petri Nets 17

A New State Model for DRAMs Using Petri Nets

引用

17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Jung, Matthias Kraft, Kira Wehn, Norbert Fraunhofer IESE D-67663 Kaiserslautern Germany Univ Kaiserslautern D-67663 Kaiserslautern Germany

ISBN: (纸本)9781538634370

The functionality of DRAMs, especially the state transitions are described in JEDEC standards. These standards contain a finite state machine, which intends to provide an overview of the possible state transitions and the commands to control them. However, today's DRAMs are highly concurrent devices as they provide bank parallelism. The state diagram used in JEDEC standards does not model this concurrency and furthermore it is misleading in several aspects. In this paper, for the first time we present an easily comprehensive model of the DRAM states and transitions, using a Petri Net, which covers also the DRAM concurrency.

关键词： Random access memory Petri nets Inhibitors Standards Parallel processing computer architecture Concurrent computing Petri nets random access machine computer Architecture PARALLEL PROCESSING (computerS) Parallel programming DRAM1 gene Inhibitors Joint Electron Device Engineering Council State Change finite state machines

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System simulation with gem5 and SystemC The Keystone for Full Interoperability 17

System Simulation with gem5 and SystemC The Keystone for Ful...

引用

17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Menard, Christian Castrillon, Jeronimo Jung, Matthias Wehn, Norbert Tech Univ Dresden Dresden Germany Fraunhofer IESE Kaiserslautern Germany Univ Kaiserslautern Kaiserslautern Germany

ISBN: (纸本)9781538634370

SystemC TLM based virtual prototypes have become the main tool in industry and research for concurrent hardware and software development, as well as hardware design space exploration. However, there exists a lack of accurate, free, changeable and realistic SystemC models of modern CPUs. Therefore, many researchers use the cycle accurate open source system simulator gem5, which has been developed in parallel to the SystemC standard. In this paper we present a coupling of gem5 with SystemC that offers full interoperability between both simulation frameworks, and therefore enables a huge set of possibilities for system level design space exploration. Furthermore, we show that the coupling itself only induces a relatively small overhead to the total execution time of the simulation.

关键词： Time-varying systems Time-domain analysis Couplings Timing Protocols Hardware Industries Time domain analysis Couplings time-varying systems computer hardware execution time systems simulation protocols industries coupling Interoperability Space Exploration keystone

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Supervised Testing of Concurrent Software in embedded systems 17

Supervised Testing of Concurrent Software in Embedded System...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Jahic, Jasmin Kuhn, Thomas Jung, Matthias Wehn, Norbert Fraunhofer IESE Embedded Software Engn Kaiserslautern Germany Univ Kaiserslautern Microelectron Syst Design Res Grp Kaiserslautern Germany

ISBN: (纸本)9781538634370

The migration of sequential embedded software to multicore processors is a challenging task. Parallelization of software introduces concurrency bugs (e.g. data races), which only conditionally appear during testing because they strongly depend on the timing of the execution. Therefore, traditional testing approaches cannot efficiently test concurrent software. More appropriate are analysis approaches that prove the absence of software faults. Current approaches often produce false positives as they fail to consider all relevant synchronization sources. In this paper, we complement current analysis techniques by considering a scheduling scheme as a synchronization mechanism. We narrow the analysis by analyzing only relevant variants in execution timing that might produce concurrency bugs. Therefore, we eliminate a family of false positives caused by ignoring the scheduling synchronization. Engineers can optimize this scheduling scheme to satisfy different requirements. Our approach uses virtual prototyping to enable design space exploration of systems with complex scheduling schemes by investigating the influence of the scheduling scheme on the synchronization of concurrent software.

关键词： Data Races Testing Concurrency Scheduling LLVM FERAL Virtual Prototyping

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Task Graph Mapping and Scheduling on Heterogeneous architectures Under Communication Constraints 17

Task Graph Mapping and Scheduling on Heterogeneous Architect...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Emeretlis, A. Tsakoulis, T. Theodoridis, G. Alefragis, P. Voros, N. Univ Patras Dept Elect & Comp Engn Patras Greece TEI Western Greece Dept Comp Informat Engn Antirio Greece

ISBN: (纸本)9781538634370

An approach for mapping applications represented as Directed Acyclic Graphs (DAGs) on platforms consisting of heterogeneous cores considering the communication overhead between the cores is introduced. The approach is based on the Benders decomposition principle and integrates Integer Linear and Constraint Programming formulations. Both formulations take into account the communication delay between dependent tasks that are assigned to different cores trying to optimize the application's execution time. The proposed approach succeeds to provide the optimal solution in all cases of synthetic and real-application DAGs, while the pure ILP model fails more than half of them. Also, the average solution time of the proposed method is about 1 minute, whereas for instances solved by both models, the speedup equals to 11x over the ILP model.

关键词： Multicore processing Processor scheduling Integer linear programming Constraint programming

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Rethinking Virtual Network Embedding in Reconfigurable Networks 15

Rethinking Virtual Network Embedding in Reconfigurable Netwo...

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15th IEEE Annual international conference on Sensing, Communication, and Networking (SECON)

作者： Curran, Max Rahman, Md. Shaifur Gupta, Himanshu Sekar, Vyas SUNY Stony Brook Dept Comp Sci Stony Brook NY 11794 USA Carnegie Mellon Univ Dept ECE Pittsburgh PA 15213 USA

ISBN: (纸本)9781538642818

The virtual network embedding (VNE) problem of mapping virtual network (VN) requests to a substrate network is a key component of network virtualization in datacenters. In a bid to improve datacenter network's performance and cost, there has been recent interest in "reconfigurable" network architectures, wherein the network topology can be changed at runtime to better handle current traffic patterns. Such reconfigurable networks seem naturally well-suited for efficient network virtualization-as networks can be "tailored" to accommodate the incoming VN requests. Motivated by the above, in this paper, we address the problem of virtual network embedding in reconfigurable networks;to the best of our knowledge, this has not been addressed before. In particular, we address the VNE problem in reconfigurable networks under two different models of VN link demands: fixed-bandwidth and stochastic-bandwidth demands. The former is the traditional model, while we propose the the latter to improve network utilization and leverage the runtime reconfiguration capability of reconfigurable networks. For the stochastic demand model, we employ a novel concept of embedding with "runtime-binding," wherein the embedding of a VN link is "configured" at runtime (via network reconfiguration) depending on the prevailing network state and traffic. We evaluate the efficiency of our proposed models and techniques via simulation using real VN requests and traffic statistics from large datacenters, and show that our proposed models and techniques offer significant performance advantages (up to 30-40%) over traditional models.

关键词： Substrates Bandwidth Runtime Computational modeling Stochastic processes Space exploration Servers

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Modelled, simulation and Design of Collecting Grid of Stray Currents in Slab Track in DC Electrified Railway systems

Modelled, Simulation and Design of Collecting Grid of Stray ...

引用

2018 IEEE international conference on Electrical systems for Aircraft, Railway, Ship Propulsion and Road Vehicles and international Transportation Electrification conference, ESARS-ITEC 2018

作者： Coves, Jordi Aguilar, Jose Sanchez Rull-Duran, Joan Electric Traction Technology IDOM Barcelona Spain MEP Department IDOM Bilbao Spain Electrical Department UPC Barcelona Spain

ISBN: (纸本)9781538641927

The stray currents are the fraction of traction return current returning by earth in at grade configurations, or by metallic structures (reinforcement bars) in case of viaducts and tunnels. These currents expose steel reinforcement bars to corrosion. The obvious alternative to minimize the risk of corrosion is to minimize the stray current, using insulation sleeper insulating pads and insulated bolts in fastener blocks. However, due to mechanic wearing by train operation, aging, or accumulation of waste, the level of insulation between rail and structures decreases with time, which increases the stray currents. A common palliative method for this is to install a Stray Current Collector (SCC), a conductive grid or mat, embedded in the concrete structure below the rails. The SCC can be connected to earth and to return circuit in different ways. The objectives of the paper are to get a model of leakage resistances including the SCC system, to determine the effectiveness of SCC and the best connection scheme. © 2018 IEEE.

关键词： Insulation

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DVFS-Enabled Power-Performance Trade-Off in MPSoC SW Application Mapping 17

DVFS-Enabled Power-Performance Trade-Off in MPSoC SW Applica...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Onnebrink, Gereon Walbroel, Florian Klimt, Jonathan Leupers, Rainer Ascheid, Gerd Murillo, Luis Gabriel Schurmans, Stefan Chen, Xiaotao Harn, YwhPyng Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst Aachen Germany Silexica GmbH Cologne Germany Huawei Technol Co Ltd Bridgewater NJ USA

ISBN: (纸本)9781538634370

Heterogeneous MPSoCs are seen as the solution to tackle performance and power demands in the embedded domain. Their HW and SW complexity necessitates an automatic approach to find the most efficient task-to-processor mapping of parallel applications. Tight power budgets require efficient task mapping, and optimally setting the voltage and frequency of each processor. This paper proposes a novel heuristic that minimises the average power consumption, while meeting performance constraints. Integrated into an industrial SW mapping framework, the applicability is validated using three different case studies and representative benchmarks. Moreover, the power-performance trade-off is discussed. A comparison with the optimal solution complements the evaluation, revealing a loss of 19% by the heuristic, but 700x faster execution.

关键词： Power demand Task analysis Optimization Benchmark testing Switches Leakage currents Clocks Benchmark testing Power demand task analysis Timing devices Switches leakage currents Leakage currents power budget MAPPING(MATHEMATICAL) tradeoffs Heuristics

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Pipelined FPGA coprocessor for Elliptic Curve Cryptography based on Residue Number System 17

Pipelined FPGA coprocessor for Elliptic Curve Cryptography b...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Matutino, Pedro Miguens Araujo, Juvenal Sousa, Leonel Chaves, Ricardo INESC ID ISEL IPL Lisbon Portugal Univ Lisbon INESC ID IST Lisbon Portugal

ISBN: (纸本)9781538634370

In this paper a novel pipelined FPGA coprocessor for ECC is proposed, exploiting the parallelism capabilities of RNS to the computation of large operand algorithms. This intrinsic characteristic of representing large integer numbers as a set of smaller and independent values allows for the parallelization of the computationally heavy large operand multiplications, required in asymmetrical cryptographic algorithms. Towards a compact and performance efficient design, the RNS coprocessor supports a single highly pipelined multi-modulo arithmetic unit. Implementation results, on FPGA of this RNS based ECC coprocessor, suggest one of the smallest programmable designs with a proportional performance when compared with related state of the art. Additionally, the resulting architecture allows for the computation of varying key sizes without changing the design or its implementation.

关键词： Elliptic curve cryptography Coprocessors computer architecture Field programmable gate arrays Encryption Elliptic curves Elliptic curve cryptography Coprocessors Field programmable gate arrays residue number systems computer Architecture Elliptic curves cryptography state of the art EMERGENCY CONTROL CENTERS Error correction codes

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