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Fine-Grained Power modeling of Multicore Processors Using FFNNs 1

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20th international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Sagi, Mark Doan, Nguyen Anh Vu Fasfous, Nael Wild, Thomas Herkersdorf, Andreas Tech Univ Munich Munich Germany

ISBN: (数字)9783030609399

ISBN: (纸本)9783030609399;9783030609382

To minimize power consumption while maximizing performance, today's multicore processors rely on fine-grained run-time dynamic power information - both in the time domain, e.g. mu s to ms, and space domain, e.g. core-level. The state-of-the-art for deriving such power information is mainly based on predetermined power models which use linear modeling techniques to determine the core-performance/corepower relationship. However, with multicore processors becoming ever more complex, linear modeling techniques cannot capture all possible core-performance related power states anymore. Although, artificial neural networks (ANN) have been proposed for coarse-grained power modeling of servers with time resolutions in the range of seconds, no work has yet investigated fine-grained ANN-based power modeling. In this paper, we explore feed-forward neural networks (FFNNs) for core-level power modeling with estimation rates in the range of 10 kHz. To achieve a high estimation accuracy, we determine optimized neural network architectures and train FFNNs on performance counter and power data from a complex-out-of-order processor architecture. We show that, relative power estimation error decreases on average by 7.5% compared to a state-of-the-art linear power modeling approach and decreases by 5.5% compared to a multivariate polynomial regression model. Furthermore, we propose an implementation for run-time inference of the power modeling FFNN and show that the area overhead is negligible.

关键词： Processor Multicore Power modeling Estimation Core-level Artificial neural network ANN FFNN Accuracy Error Overhead

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SensorOS:: A new operating system for time critical WSN applications

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international conference on embedded computer systems - architectures, modeling and simulation

作者： Kuorilehto, Mauri Alho, Timo Hannikainen, Marko Hamalainen, Timo D. Tampere Univ Technol Inst Digital & Comp Syst POB 553 FI-33101 Tampere Finland Nokia Technol Platforms Tampere Finland

ISBN: (纸本)9783540736226

This paper presents design and implementation of a multi-threading Operating System (OS), SensorOS, for resource constrained Wireless Sensor Network (WSN) nodes. Compared to event-handler kernels, such as TinyOS, SensorOS enables coexistence of multiple time critical application tasks. SensorOS supports preemptive priority-based scheduling, very fine-granularity timing, and message passing inter-process communication. SensorOS has been implemented for resource constrained Tampere University of Technology WSN (TUTWSN) nodes. In TUTWSN node platform with 2 MIPS PIC micro-controller unit, SensorOS kernel uses 6964 B code and 115 B data memory. The context swap time is 92 mu s and the variance of timing accuracy for a high priority thread less than 5 mu s. The results show that the realtime coordination of WSN applications and protocols can be managed by a versatile OS even on resource constrained nodes.

关键词： computer operating systems

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Multicore Communications API (MCAPI) implementation on an FPGA multiprocessor

Multicore Communications API (MCAPI) implementation on an FP...

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2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Matilainen, Lauri Salminen, Erno Hämäläinen, Timo D. Hämäläinen, Marko Tampere University of Technology Department of Computer Systems P.O. Box 553 33101 Tampere Finland

ISBN: (纸本)9781457708008

The design and implementation of an application programming interface (API) is a trade-off between abstraction it provides and overheads it causes. This paper presents an implementation of Multicore Communications API (MCAPI) on a heterogeneous platform consisting of FPGA-based multiprocessor system-on-chip (MPSoC) connected via PCIe to an external CPU board. The purpose is to provide a unified programming API to different processor and OS types as well as hardware IP-blocks. MCAPI is shown to meet these requirements. We show the MCAPI transport implementation on three processors and two buses, measure the overhead cost, and analyze the effort required to port an application from a PC to the MPSoC. The measured library memory footprint is less than 25KB and the roundtrip communication latency is diminishing low only few dozen clock cycles compared to non-MCAPI implementation. © 2011 IEEE.

关键词： Field programmable gate arrays (FPGA)

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SHARQ: Software-Defined Hardware-Managed Queues for Tile-Based Manycore architectures 19th

SHARQ: Software-Defined Hardware-Managed Queues for Tile-Bas...

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19th international conference on embedded computer systems: architectures, modeling, and simulation (SAMOS)

作者： Rheindt, Sven Maier, Sebastian Schmaus, Florian Wild, Thomas Schroeder-Preikschat, Wolfgang Herkersdorf, Andreas Tech Univ Munich TUM Arcisstr 21 D-80333 Munich Germany Friedrich Alexander Univ Erlangen Nurnberg FAU Schlosspl 4 D-91054 Erlangen Germany

ISBN: (纸本)9783030275624;9783030275617

The recent trend towards tile-based manycore architectures has helped to tackle the memory wall by physically distributing memories and processing nodes. Distributed operating systems and applications allow to exploit the increased scalability of such architectures, but still face the data-to-task locality challenge. As inter-tile communication, thread synchronization and data transport often impose significant software overhead on such architectures, many applications would benefit from a more efficient and powerful communication primitive with minimal software involvement. We propose software-defined hardware-managed queues for distributed computing architectures that enable efficient inter-tile communication by leveraging application-specific queues with arbitrarily sized elements. To ensure (remote) processing of queued elements, SHARQ introduces the concept of an optional handler task, which is scheduled by hardware on demand. Queue and memory management, intra- and inter-tile data transfer, and handler task invocation are entirely handled by hardware. Only the dynamic queue creation at runtime is performed in software. As an example use-case, we integrated SHARQ into the MPI library. The evaluation with the MPI-based NAS benchmarks shows a reduction in execution time by up to 48% for the communication intense IS kernel in a 4 x 4 tile design on an FPGA platform with a total of 80 LEON3 cores.

关键词： Distributed architectures Hardware accelerator Inter-tile communication Hardware/software codesign MPMC queue NoC

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Design of a Unified Transport Triggered Processor for LDPC/Turbo Decoder

Design of a Unified Transport Triggered Processor for LDPC/T...

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13th international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Shahabuddin, Shahriar Janhunen, Janne Bayramoglu, Muhammet Fatih Juntti, Markku Ghazi, Amanullah Silven, Olli Univ Oulu Dept Commun Engn SF-90100 Oulu Finland Univ Oulu Dept Comp Sci & Engn SF-90100 Oulu Finland

ISBN: (纸本)9781479901036

This paper summarizes the design of a programmable processor with transport triggered architecture (TTA) for decoding LDPC and turbo codes. The processor architecture is designed in such a manner that it can be programmed for LDPC or turbo decoding for the purpose of internetworking and roaming between different networks. The standard trellis based maximum a posteriori (MAP) algorithm is used for turbo decoding. Unlike most other implementations, a supercode based sum-product algorithm is used for the check node message computation for LDPC decoding. This approach ensures the highest hardware utilization of the processor architecture for the two different algorithms. Up to our knowledge, this is the first attempt to design a TTA processor for the LDPC decoder. The processor is programmed with a high level language to meet the time-to-market requirement. The optimization techniques and the usage of the function units for both algorithms are explained in detail. The processor achieves 22.64 Mbps throughput for turbo decoding with a single iteration and 10.12 Mbps throughput for LDPC decoding with five iterations for a clock frequency of 200 MHz.

关键词： computer architecture maximum likelihood estimation optimisation parity check codes turbo codes

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The DESERVE project: Towards future ADAS functions 14

The DESERVE project: Towards future ADAS functions

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international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Kutila, Matti Pyykonen, Pasi van Koningsbruggen, Paul Pallaro, Nereo Perez-Rastelli, Joshue VTT Tech Res Ctr Finland Tampere Finland Technolution BV Gouda Netherlands Ctr Ric FIAT Turin Italy INRIA Le Chesnay France

ISBN: (纸本)9781479937707

This article introduces the objectives and structure of the European research project DESERVE that is co-funded by the ARTEMIS-JU and national funding bodies. The project started in September 2012 with a duration of 3 years. The project aims to establish a new embedded SW and HW design by using a more efficient development process (including the enabling general platform concept and tool chain) in order to overcome challenges in reducing component costs and development time of future ADAS functions for modern vehicles. Both the process and the platform concept will be demonstrated with innovative ADAS functions in 3 passenger cars, 1 truck and 1 motorcycle. embedded hardware and software units have been developed for improving electronic horizon band of vehicles by detecting objects in front. Moreover, driver/motorcycle rider awareness is analysed by monitoring his/her actions online. The systems need to be robust and reliable in different environment conditions (night time, rain, etc.). The DESERVE platform distinguishes three layers of intelligence: perception, application and intervention& warning control. The demonstrators will be based on software development tools from Elektrobit (ADTF) and Intempora (RTmaps). These tools are used to create 10 innovative ADAS applications as part of an integral ADAS development platform, following a new design and development process. Since the project is highly application oriented, the requirements have been adapted mainly from the ISO 26262 standard and the AUTOSAR framework which ensures compatibility with the existing automotive software environment.

关键词： automotive ADAS function driver monitoring camera traffic safety embedded systems

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Fast and cycle-accurate simulation of multi-threaded applications on SMP architectures using hybrid prototyping 16

Fast and cycle-accurate simulation of multi-threaded applica...

引用

international conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)

作者： Saboori, Ehsan Abdi, Samar Concordia Univ Montreal PQ Canada

ISBN: (纸本)9781450344838

This paper presents a fast and cycle accurate simulation environment for early power-performance analysis of multi-threaded applications targeted to symmetric multiprocessing embedded architectures. Our simulation environment leverages the hybrid prototyping technique, where a lightweight emulation kernel performs logical simulation of multiple identical cores on top of a single physical instance of a core. The technique does not require a detailed timing model of the core hardware because the application threads execute directly on the target core. Previous work on hybrid prototyping supported modeling of only statically scheduled threads, thereby severely limiting its modeling capabilities. In this work, we describe the modeling of dynamic RTOS scheduler as well as hardware interrupts on top of the emulation kernel, in order to support the simulation of unmodified multi-threaded applications. Our experimental results demonstrate the high accuracy, simulation speed and scalability of our hybrid prototyping-based simulation models.

关键词： Hybrid prototyping embedded systems Multicore design Rapid prototyping Symmetrical Multi Processor Virtual prototyping FPGA prototyping

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Reconfigurable computing for future vision-capable devices 15

Reconfigurable computing for future vision-capable devices

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15th international conference on embedded computer systems: architectures, modeling and simulation, SAMOS 2015

作者： López, Miguel Bordallo Nieto, Alejandro Silvén, Olli Bóutellier, Jani Vilariño, David López University of Oulu Finland CITIUS Universidad de Santiago de Compostela Spain

ISBN: (纸本)9781467373111

Mobile devices have been identified as promising platforms for interactive vision-based applications. However, this type of applications still pose significant challenges in terms of latency, throughput and energy-efficiency. In this context, the integration of reconfigurable architectures on mobile devices allows dynamic reconfiguration to match the computation and data flow of interactive applications, demonstrating significant performance benefits compared to general purpose architectures. This paper presents concepts laying on platform level adaptability, exploring the acceleration of vision-based interactive applications through the utilization of three reconfigurable architectures: A low-power EnCore processor with a Configurable Flow Accelerator co-processor, a hybrid reconfigurable SIMD/MIMD platform and Transport-Triggered Architecture-based processors. The architectures are evaluated and compared with current processors, analyzing their advantages and weaknesses in terms of performance and energy-efficiency when implementing highly interactive vision-based applications. The results show that the inclusion of reconfigurable platforms on mobile devices can enable the computation of several computationally heavy tasks with high performance and small energy consumption while providing enough flexibility. © 2015 IEEE.

关键词： Reconfigurable architectures

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Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform

Design space exploration of systolic realization of QR facto...

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2010 10th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2010

作者： Biswas, Prasenjit Varadarajan, Keshavan Alle, Mythri Nandy, S.K. Narayan, Ranjani CADL IISc Bangalore India Morphing Machines Bangalore India

ISBN: (纸本)9781424479382

In the world of high performance computing huge efforts have been put to accelerate Numerical Linear Algebra (NLA) kernels like QR Decomposition (QRD) with the added advantage of reconfigurability and scalability. While popular custom hardware solution in form of systolic arrays can deliver high performance, they are not scalable, and hence not commercially viable. In this paper, we show how systolic solutions of QRD can be realized efficiently on REDEFINE, a scalable runtime reconfigurable hardware platform. We propose various enhancements to REDEFINE to meet the custom need of accelerating NLA kernels. We further do the design space exploration of the proposed solution for any arbitrary application of size n x n. We determine the right size of the sub-array in accordance with the optimal pipeline depth of the core execution units and the number of such units to be used per sub-array. ©2010 IEEE.

关键词： Reconfigurable architectures

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Predictable Dynamic embedded Data Processing

Predictable Dynamic Embedded Data Processing

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international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Geilen, Marc Stuijk, Sander Basten, Twan Eindhoven Univ Technol Dept Elect Engn NL-5600 MB Eindhoven Netherlands

ISBN: (纸本)9781467322973;9781467322966

Cyber-physical systems interact with their physical environment. In this interaction, non-functional aspects, most notably timing, are essential to correct operation. In modern systems, dynamism is introduced in many different ways. The additional complexity threatens timely development and reliable operation. Applications often have different modes of operation with different resource requirements and different levels of required quality-of-service. Moreover, multiple applications in dynamically changing combinations share a platform and its resources. To preserve efficient development of such systems, dynamism needs to be taken into account as a primary concern, not as a verification or tuning effort after the design is done. This requires a model-driven design approach in which timing of interaction with the physical environment is taken into consideration;formal models capture applications and their platforms in the physical environment. Moreover, platforms with resources and resource arbitration are needed that allow for predictable and reliable behavior to be realized. Run-time management is further required to deal with dynamic use-cases and dynamic trade-offs encountered at run-time. In this paper, we present a model-driven approach that combines model-based design and synthesis with development of platforms that support predictable, repeatable, composable realizations and a run-time management approach to deal with dynamic use-cases at run-time. A formal, compositional model is used to exploit Pareto-optimal trade-offs in the system use. The approach is illustrated with dataflow models with dynamic application scenarios, a predictable platform architecture and run-time resource management that determines optimal trade-offs through an efficient knapsack heuristic.

关键词： Runtime physical environment Platform resource requirements operation mode Time Management management of resources Surgery dynamism

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