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international conference on embedded computer systems architectures modeling and simulation

作者： Pollanen, Irene Braithwaite, Billy Haataja, Keijo Ikonen, Tiia Toivanen, Pekka Univ Eastern Finland Sch Comp Kuopio Campus Kuopio Finland

ISBN: (纸本)9781467373111

In this paper, the current approaches and performance needs for whole slide image (WSI) analysis processing in breast cancer diagnostics are discussed. WSIs provide high resolution digital image data from the patient's diseased tissue. Digital whole slide images are typically very large and contain a high amount of information. Digitizing tissue specimen into the form of digital images allows the development and application of computational analysis algorithms. Biological tissues are complex with variance in tissue structures between healthy individuals as well as between patients with the same disease. Furthermore, the tissue preparation and digitization usually generates a lot of artifacts and more complexity, which causes classification challenges. This variance and also the large size of the images make creating an accurate and reliable automated breast cancer image analysis a challenge. In the ALMARVI project we aim at generating and implementing efficient histopathological image analysis algorithms in our breast cancer analysis scheme. This paper focuses on discussing relevant information concerning histopathological breast cancer diagnosis, and could also be considered as an introduction to the concept of WSI analysis to non-experts. Since the WSI sizes are very large (up to 40 GB with no compression) there are challenges on the computational analysis which requires computationally efficient tools and suitable approaches to relieve the problems caused by the large size of the images.

关键词： whole slide image breast cancer computer-aided diagnosis

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Profiling Dilithium Digital Signature Traces for Correlation Differential Side Channel Attacks 20th

Profiling Dilithium Digital Signature Traces for Correlation...

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20th international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Fournaris, Apostolos P. Dimopoulos, Charis Koufopavlou, Odysseas Res Ctr ATHENA Ind Syst Inst Patras Sci Pk Patras Greece Univ Patras Elect & Comp Engn Dept Rion Campus Patras Greece

ISBN: (纸本)9783030609399;9783030609382

A significant concern for the candidate schemes of the NIST postquantum cryptography standardization project is the protection they support against side-channel attacks. One of these candidate schemes currently in the NIST standardization race is the Dilithium signature scheme. This postquantum signature solution has been analyzed for side channel attack resistance especially against timing attacks. Expanding our attention on other types of side-channel analysis, this work is focused on correlation based differential side channel attacks on the polynomial multiplication operation of Dilithium digital signature generation. In this paper, we describe how a Correlation Power Attack should be adapted for the Dilithium signature generation and describe the attack process to be followed. We determine the conditions to be followed in order for such an attack to be feasible, (isolation of polynomial coefficient multiplication inpower traces) and we create a power trace profiling paradigm for the Dilithium signature scheme executed in embedded systems to showcase that the conditions can be met in practice. Expanding the methodology of recent works that mainly use simulations for power trace collection, in this paper, power trace capturing and profiling analysis of the signature generation process was succesfully done on a, noisy, Commercial off-the-shelf ARM Cortex-M4 embedded system.

关键词： Postquantum cryptography Side channel attack Secure embedded systems

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Efficient and effective simulation of memory maps for system-on-chip

Efficient and effective simulation of memory maps for system...

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11th IEEE international conference and Workshop on Engineering of computer-Based systems (ECBS 2004)

作者： Luculli, G

ISBN: (纸本)0769521258

dThe design of complex system-on-chip (SOC) requires new methods and tools for the optimization of embedded software which is executed on ever more complex hardware architectures. The tuning of the memory subsystem is particularly difficult due to the many design parameters which are involved and the long time which is required to simulate different design configurations. In this paper, we propose a very effective mechanism for the simulation of generic memory maps on architectures with instruction and/or data cache memory. An important characteristic of our implementation is its large flexibility: any memory map and any cache configuration can be simulated without the need to modify or to re-compile the application code. We implemented such mechanism in our ISA retargetable environment and we showed that it loosely impacts the simulation performance.

关键词： embedded systems

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An optimization methodology for memory allocation and task scheduling in SoCs via linear programming

An optimization methodology for memory allocation and task s...

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6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Ristau, Bastian Fettweis, Gerhard Tech Univ Dresden Vodafone Chair Mobile Commun Syst D-01062 Dresden Germany

ISBN: (纸本)3540364102

Applications for system on chips become more and more complex. Also the number of available components (DSPs, ASICs, Memories, etc.) rises continuously. These facts necessitate a structured method for selecting components, mapping applications and evaluating the chosen configuration and mapping. In this work we present a methodology for the last named. We will consider optimization of memory allocation and task scheduling as a packing problem and minimize needed memory area. The results can be used as one element of an automated performance analysis for a given system on a high abstraction level. This analysis is essential for establishing a framework that iterates over a large quantity of possible systems. Considering a part of the H.264 codec as an example we will illustrate the results. Furthermore we will show that results can be retrieved fast compared to other NP-hard problems due to intelligent formulation of conditions within the linear program.

关键词： Storage allocation (computer)

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modeling the Temperature Bias of Power Consumption for Nanometer-Scale CPUs in Application Processors 14

Modeling the Temperature Bias of Power Consumption for Nanom...

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international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： De Vogeleer, Karel Memmi, Gerard Jouvelot, Pierre Coelho, Fabien TELECOM ParisTech INFRES CNRS LTCI UMR 5141 Paris France MINES ParisTech Paris France

ISBN: (纸本)9781479937707

We introduce and experimentally validate a new macro-level model of the CPU temperature/power relationship within nanometer-scale application processors or system-onchips. By adopting a holistic view, this model is able to take into account many of the physical effects that occur within such systems. Together with two algorithms described in the paper, our results can be used, for instance by engineers designing power or thermal management units, to cancel the temperature-induced bias on power measurements. This will help them gather temperature-neutral power data while running multiple instance of their benchmarks. Also power requirements and system failure rates can be decreased by controlling the CPU's thermal behavior. Even though it is usually assumed that the temperature/power relationship is exponentially related, there is however a lack of publicly available physical temperature/power measurements to back up this assumption, something our paper corrects. Via measurements on two pertinent platforms sporting nanometer-scale application processors, we show that the power/temperature relationship is indeed very likely exponential over a 20 degrees C to 85 degrees C temperature range. Our data suggest that, for application processors operating between 20 degrees C and 50 degrees C, a quadratic model is still accurate and a linear approximation is acceptable.

关键词： central processing units PROCESSOR Power consumption Power measurement Linear approximation Bias Bias Bias Statistical Biases bias(electronics)

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High level quantitative hardware prediction modeling using statistical methods

High level quantitative hardware prediction modeling using s...

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2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Meeuws, Roel Galuzzi, Carlo Bertels, Koen Computer Engineering Lab Delft University of Technology Netherlands

ISBN: (纸本)9781457708008

With the increasing proliferation of heterogeneous and reconfigurable computing, it has become essential to have efficient prediction models to drive early HW-SW partitioning and co-design. In this paper, we present a high level quantitative prediction modeling approach that accurately models the relation between hardware and software metrics, based on several statistical techniques. The proposed approach generates models that predict hardware performance indicators for reconfigurable components, such as the number of slices, the number of flip-flops, and the number of wires. It utilizes automatic model selection, artificial neural networks, (logistic) regression, and data transformations. These models take a high-level language description as input, enabling hardware prediction in the early design stages. We calibrate the models for two sets of tools targeting Xilinx and Altera FPGAs, where we report, for example, and error of 14% for the number of multipliers in case of Xilinx and an error of only 18% for the number of wires in case of Altera. To provide a realistic evaluation, we validate the approach using 181 kernels, contrary to the majority of the existing techniques, which use libraries of tens of kernels at most. © 2011 IEEE.

关键词： Forecasting

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Hybrid functional and instruction level power modeling for embedded processors

Hybrid functional and instruction level power modeling for e...

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6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Blume, Holger Becker, Daniel Botteck, Martin Brakensiek, Joerg Noll, Tobias G. Univ Aachen Rhein Westfal TH Aachen Chair Elect Engn & Comp Syst D-52062 Aachen Germany Nokia Res Ctr D-44807 Bochum Germany

ISBN: (纸本)3540364102

In this contribution the concept of Functional-Level Power Analysis (FLPA) for power estimation of programmable processors is extended in order to model even embedded general purpose processors. The basic FLPA approach is based on the separation of the processor architecture into functional blocks like e.g. processing unit, clock network, internal memory etc. The power consumption of these blocks is described by parameterized arithmetic models. By application of a parser based automated analysis of assembler codes the input parameters of the arithmetic functions like e.g. the achieved degree of parallelism or the kind and number of memory accesses can be computed. For modeling an embedded general purpose processor (here, an ARM940T) the basic FLPA modeling concept had to be extended to a so-called hybrid functional level and instruction level model in order to achieve a good modeling accuracy. The approach is exemplarily demonstrated and evaluated applying a variety of basic digital signal processing tasks ranging from basic filters to complete audio decoders. Estimated power figures for the inspected tasks are compared to physically measured values. A resulting maximum estimation error of less than 8 % is achieved.

关键词： Program processors

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High-Level Synthesis of Digital Circuits from Template Haskell and SDF-AP 22nd

High-Level Synthesis of Digital Circuits from Template Haske...

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22nd international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Folmer, H. H. de Groote, R. Bekooij, M. J. G. Univ Twente CAES Comp Architectures Embedded Syst Enschede Netherlands Sax Hogesch Enschede Netherlands

ISBN: (纸本)9783031150746;9783031150739

Functional languages as input specifications for HLS-tools allow to specify data dependencies but do not contain a notion of time nor execution order. In this paper, we propose a method to add this notion to the functional description using the dataflow model SDF-AP. SDF-AP consists of patterns that express consumption and production that we can use to enforce resource usage. We created an HLS-tool that can synthesize parallel hardware, both data and control path, based on the repetition, expressed in Higher-Order Functions, combined with specified SDF-AP patterns. Our HLS-tool, based on Template Haskell, generates an Abstract Syntax Tree based on the given patterns and the functional description uses the Clash-compiler to generate VHDL/Verilog. Case studies show consistent resource consumption and temporal behavior for our HLS-tool. A comparison with a commercially available HLS-tool shows that our tool outperforms in terms of latency and sometimes in resource consumption. The method and tool presented in this paper offer more transparency to the developer and allow to specify more accurately the synthesized hardware compared to what is possible with pragmas of the Vitis HLS-tool.

关键词： High level synthesis

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Software-oriented system-level simulation for design space exploration of reconfigurable architectures

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10th Asia-Pacific conference on Advances in computer systems Architecture

作者： Tham, KS Maskell, DL Nanyang Technol Univ Ctr High Performance Embedded Syst Singapore Singapore

ISBN: (纸本)3540296433

To efficiently utilize the functionality of dynamic reconfigurable computing systems, it is imperative that a software-oriented approach for modeling complex hardware/software systems be adopted. To achieve this, we need to enhance the simulation environment to understand these dynamic reconfiguration requirements during system-level modeling. We present a flexible simulation model which is able to produce multiple views/contexts for a given problem. We use this model to examine each view for the mapping space, bandwidth, reconfiguration requirements, and configuration patterns of each computational problem.

关键词： computer architecture

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Rapid implementation and optimisation of DSP systems on FPGA-centric heterogeneous platforms

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JOURNAL OF systems ARCHITECTURE 2007年第8期53卷 511-523页

作者： McAllister, J. Woods, R. Fischaber, S. Malins, E. Queens Univ Belfast ECIT Belfast BT3 9DT Antrim North Ireland

The emergence of programmable logic devices as single-chip heterogeneous processing platforms for digital signal processing applications poses challenges concerning rapid implementation and high level optimisation of algorithms on these platforms. This paper describes Abhainn, a rapid implementation methodology and toolsuite for translating an algorithmic expression of the system to a working solution on FPGA-centric embedded platforms. Two particular focuses for Abhainn are the automated but configurable reallisation of inter-processor communication fabrics, and the establishment of novel dedicated hardware component design methodologies allowing algorithm level transformation for system optimisation. This paper outlines the approaches employed in these areas and demonstrates their effectiveness on high end signal processing beamforming applications. (c) 2007 Elsevier B.V. All rights reserved.

关键词： FPGA DSP electronic system level design heterogeneous platform embedded computing

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