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international conference on embedded computer systems

作者： Falcao, Gabriel Sousa, Leonel Silva, Vitor Department of Electrical and Computer Engineering Instituto de Telecomunicações/FCTUC Universidade de Coimbra - Pólo II 3030-290 Coimbra Portugal Department of Electrical and Computer Engineering IST/INESC-ID/TU Lisbon R. Alves Redol n.9 1000-029 Lisboa Portugal

ISBN: (纸本)9781424479382

Recently, the development of Low-Density Parity-Check (LDPC) decoding solutions has been proposed for a vast set of architectures, ranging from dedicated hardware to fully programmable ones (e.g. Cell/B.E. and graphics processing units). In this paper we propose efficient embedded programmable multicore architectures for achieving real-time LDPC decoding. The proposed multicore architectures allow to exploit data parallelism by decoding in parallel multiple codewords on the provided cores, with enough local memory capacity to store all data corresponding to the Tanner graph. Therefore, with this distributed memory and local computing approach, only a single shared bus is required to communicate the codewords. The proposed class of architectures can be prototyped on field programmable gate arrays or implemented on application specific integrated circuits, and it is validated by using the popular Cell processor, which relates very closely with the one here proposed. Finally, we discuss the related art of dedicated and programmable LDPC decoders, and discuss the advantages and disadvantages regarding the proposed solution. ©2010 IEEE.

关键词： Decoding

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Transparent sampling

Transparent sampling

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2010 10th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2010

作者： Khan, Taj Muhammad Pérez, Daniel Gracia Temam, Olivier INRIA Saclay France CEA LIST Software Safety Laboratory 91191 Gif-sur-Yvette Cedex France

ISBN: (纸本)9781424479382

Low simulation speeds have a critical impact on the design process by limiting the number of design options which can be explored. Sampling is a popular fast simulation technique because it can achieve high simulation speed and high accuracy. However state-of-the-art sampling techniques either consider warm-up as an orthogonal issue and leave the choice of a warm-up technique to the end user, or require cumbersome simulator modifications from the end user. Since the most user-friendly and efficient warm-up techniques are not easily compatible with the most efficient sampling techniques, the end user is left with a difficult choice, or runs the risk of misusing sampling techniques with poor warm-up. Transparent Sampling reconciles sampling and warm-up techniques by delivering state-of-the-art accuracy and simulation time, while remaining easily accessible to end users not proficient in, or not willing to delve into, fast simulation issues. ©2010 IEEE.

关键词： cumbersome simulator modification fast simulation technique high simulation speed low simulation speeds orthogonal issue sampling methods simulation state-of- the-art sampling techniques transparent sampling user friendly technique warm up technique

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Performance and power analysis of parallelized implementations on an MPCore multiprocessor platform

Performance and power analysis of parallelized implementatio...

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2007 international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2007

作者： Blume, H. Livonius, J.V. Rotenberg, L. Noll, T.G. Bothe, H. Brakensiek, J. Department of Electrical Engineering and Computer Systems RWTH Aachen University Schinkelstraße 2 52062 Aachen Germany Nokia Research Center Meesmannstr. 103 44807 Bochum Germany

ISBN: (纸本)1424410584

In this contribution, the potential of parallelized software that implements algorithms of digital signal processing on a multicore processor platform is analyzed. For this purpose various digital signal processing tasks have been implemented on a prototyping platform i.e. an ARM MPCore featuring four ARM11 processor cores. In order to analyze the effect of parallelization on the resulting performance-power ratio, influencing parameters like e.g. the number of issued program threads have been studied. For parallelization issues the OpenMP programming model has been used which can be efficiently applied on C-level. In order to elaborate power efficient code also a functional and instruction level power model of the MPCore has been derived which features a high estimation accuracy. Using this power model and exploiting the capabilities of OpenMP a variety of exemplary tasks could be efficiently parallelized. The general efficiency potential of parallelization for multiprocessor architectures can be assembled. ©2007 IEEE.

关键词： Digital signal processing

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Efficient system design using the Statistical Analysis of Architectural Bottlenecks methodology

Efficient system design using the Statistical Analysis of Ar...

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2012 international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2012

作者： Arora, Manish Wang, Feng Rychlik, Bob Tullsen, M. Department of Computer Science and Engineering University of California San Diego San Diego CA United States Qualcomm Incorporated 5775 Morehouse Drive San Diego CA United States

ISBN: (纸本)9781467322973

CPU processor design involves a large set of increasingly complex design decisions Doing full, accurate simulation of all possible designs is typically not feasible. Prior techniques for sensitivity analysis seek to identify the most critical design parameters, but also struggle to handle the increasing design space well. They can be overly sensitive to the starting fixed point of the design, can still require a large number of simulations, and do not necessarily account for the cost of each design parameter. The Statistical Analysis of Architectural Bottlenecks (SAAB) methodology simultaneously analyzes multiple parameters and requires a small number of experiments. SAAB leverages the Plackett and Burman analysis method, but builds upon the technique in two specific ways. It allows a parameter to take multiple values and replaces the unit-less impact factor with a cost-proportional impact value. This paper applies the SAAB methodology to the design of a mobile processor sub-system. It considers area and power cost models for the design. © 2012 IEEE.

关键词： Statistical methods

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Reliability Optimization Under Severe Uncertainty for NoC Based architectures Using an Info-Gap Decision Approach 63

Reliability Optimization Under Severe Uncertainty for NoC Ba...

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63rd IEEE international Midwest Symposium on Circuits and systems (MWSCAS)

作者： Guan, Wenkai Zhang, Jinhua Ababei, Cristinel Marquette Univ Dept Elect & Comp Engn Milwaukee WI 53233 USA

ISBN: (纸本)9781728180588

Increased uncertainties in design parameters undermine the accuracy of the mapping of embedded applications to Network-on-Chip (NoC) based manycore architectures. In this paper, we attempt for the first time to apply the info-gap theory to uncertainty modeling in the context of embedded systems design. We first propose a novel info-gap based uncertainty-aware reliability model for NoC based manycore platforms. We then develop an uncertainty-aware solution to the problem of mapping in embedded systems. The solution is implemented as a computer program that can generate robust Pareto frontiers. simulation results indicate that the proposed info-gap based uncertainty-aware mapping generates Pareto frontiers that have significant differences from the ones obtained with a traditional deterministic approach. Identifying and quantifying these differences is an important first step towards the development of better mapping optimization processes in order to arrive to optimal rather than suboptimal solutions.

关键词： Network-on-chip

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Fine-Grained Power modeling of Multicore Processors Using FFNNs 1

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20th international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Sagi, Mark Doan, Nguyen Anh Vu Fasfous, Nael Wild, Thomas Herkersdorf, Andreas Tech Univ Munich Munich Germany

ISBN: (数字)9783030609399

ISBN: (纸本)9783030609399;9783030609382

To minimize power consumption while maximizing performance, today's multicore processors rely on fine-grained run-time dynamic power information - both in the time domain, e.g. mu s to ms, and space domain, e.g. core-level. The state-of-the-art for deriving such power information is mainly based on predetermined power models which use linear modeling techniques to determine the core-performance/corepower relationship. However, with multicore processors becoming ever more complex, linear modeling techniques cannot capture all possible core-performance related power states anymore. Although, artificial neural networks (ANN) have been proposed for coarse-grained power modeling of servers with time resolutions in the range of seconds, no work has yet investigated fine-grained ANN-based power modeling. In this paper, we explore feed-forward neural networks (FFNNs) for core-level power modeling with estimation rates in the range of 10 kHz. To achieve a high estimation accuracy, we determine optimized neural network architectures and train FFNNs on performance counter and power data from a complex-out-of-order processor architecture. We show that, relative power estimation error decreases on average by 7.5% compared to a state-of-the-art linear power modeling approach and decreases by 5.5% compared to a multivariate polynomial regression model. Furthermore, we propose an implementation for run-time inference of the power modeling FFNN and show that the area overhead is negligible.

关键词： Processor Multicore Power modeling Estimation Core-level Artificial neural network ANN FFNN Accuracy Error Overhead

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Tuning a protocol processor architecture towards DSP operations

Tuning a protocol processor architecture towards DSP operati...

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5th international Workshop on embedded computer systems - architectures, modeling,, and simulation

作者： Paakkulainen, J Virtanen, S Isoaho, J Univ Turku Dept Informat Technol FIN-20520 Turku Finland Turku Ctr Comp Sci Embedded Syst Lab FIN-20520 Turku Finland

ISBN: (纸本)354026969X

In this paper we present an experiment in enhancing our transport triggered protocol processor hardware platform to support DSP applications. Our focus is on integrating support for both application domains into a single processor without loss of performance in either domain. Such a processor could be taken advantage of. in applications like Voice-over-IP communication using hand-held devices, where functionality is needed from both domains. As our first step in bridging the gap between the protocol processing and DSP domains we implement support for FIR filtering. We analyze four different architectural instances for implementing FIR filters according to their performance and bus utilisation. We were able to determine that protocol processing and DSP operations can be executed in parallel very efficiently. The implementations were verified with VHDL simulations and synthesis using 0.18 mu m CMOS technology.

关键词： Program processors

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Efficient design space exploration for application specific systems-on-a-chip

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JOURNAL OF systems ARCHITECTURE 2007年第10期53卷 733-750页

作者： Ascia, Giuseppe Catania, Vincenzo Di Nuovo, Alessandro G. Palesi, Maurizio Patti, Davide Univ Catania Dipartimento Ingn Informat & Telecomunicaz I-95125 Catania Italy

A reduction in the time-to-market has led to widespread use of pre-designed parametric architectural solutions known as system-on-a-chip (SoC) platforms. A system designer has to configure the platform in such a way as to optimize it for the execution of a specific application. Very frequently, however, the space of possible configurations that can be mapped onto a SoC platform is huge and the computational effort needed to evaluate a single system configuration can be very costly. In this paper we propose an approach which tackles the problem of design space exploration (DSE) in both of the fronts of the reduction of the number of system configurations to be simulated and the reduction of the time required to evaluate (i.e., simulate) a system configuration. More precisely, we propose the use of Multi-objective Evolutionary Algorithms as optimization technique and Fuzzy systems for the estimation of the performance indexes to be optimized. The proposed approach is applied on a highly parameterized SoC platform based on a parameterized VLIW processor and a parameterized memory hierarchy for the optimization of performance and power dissipation. The approach is evaluated in terms of both accuracy and efficiency and compared with several established DSE approaches. The results obtained for a set of multimedia applications show an improvement in both accuracy and exploration time. (C) 2007 Elsevier B.V. All rights reserved.

关键词： design space exploration multi-objective optimization embedded system design very long instruction word processor fuzzy estimation evolutionary computation

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Fast and cycle-accurate simulation of multi-threaded applications on SMP architectures using hybrid prototyping 16

Fast and cycle-accurate simulation of multi-threaded applica...

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international conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)

作者： Saboori, Ehsan Abdi, Samar Concordia Univ Montreal PQ Canada

ISBN: (纸本)9781450344838

This paper presents a fast and cycle accurate simulation environment for early power-performance analysis of multi-threaded applications targeted to symmetric multiprocessing embedded architectures. Our simulation environment leverages the hybrid prototyping technique, where a lightweight emulation kernel performs logical simulation of multiple identical cores on top of a single physical instance of a core. The technique does not require a detailed timing model of the core hardware because the application threads execute directly on the target core. Previous work on hybrid prototyping supported modeling of only statically scheduled threads, thereby severely limiting its modeling capabilities. In this work, we describe the modeling of dynamic RTOS scheduler as well as hardware interrupts on top of the emulation kernel, in order to support the simulation of unmodified multi-threaded applications. Our experimental results demonstrate the high accuracy, simulation speed and scalability of our hybrid prototyping-based simulation models.

关键词： Hybrid prototyping embedded systems Multicore design Rapid prototyping Symmetrical Multi Processor Virtual prototyping FPGA prototyping

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An embedded Hardware-Efficient Architecture for Real-Time Cascade Support Vector Machine Classification

An Embedded Hardware-Efficient Architecture for Real-Time Ca...

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13th international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Kyrkou, Christos Theocharides, Theocharis Bouganis, Christos-Savvas Univ Cyprus KIOS Res Ctr Dept Elect & Comp Engn Nicosia Cyprus Univ London Imperial Coll Sci Technol & Med Dept Elect & Elect Engn London SW7 2AZ England

ISBN: (纸本)9781479901036

Support Vector Machines (SVMs) are considered as a state-of-the-art classification algorithm yielding high accuracy rates. However, SVMs often require processing a large number of support vectors, making the classification process computationally demanding, especially when considering embedded applications. Cascade SVMs have been proposed in an attempt to speed-up classification times, but improved performance comes at a cost of additional hardware resources. Consequently, in this paper we propose an optimized architecture for cascaded SVM processing, along with a hardware reduction method in order to reduce the overheads from the implementation of additional stages in the cascade, leading to significant resource and power savings for embedded applications. The architecture was implemented on a Virtex 5 FPGA platform and evaluated using face detection as the target application on 640x480 resolution images. Additionally, it was compared against implementations of the same cascade processing architecture but without using the reduction method, and a single parallel SVM classifier. The proposed architecture achieves an average performance of 70 frames-per-second, demonstrating a speed-up of 5x over the single parallel SVM classifier. Furthermore, the hardware reduction method results in the utilization of 43% less hardware resources and a 20% reduction in power, with only 0.7% reduction in classification accuracy.

关键词： Field Programmable Gate Arrays Support Vector Machines Cascade Classifier Real-time and embedded systems Parallel Architecture

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