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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

共 2831 条记录，以下是381-390 订阅

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Towards scalable I/O on a many-core architecture

Towards scalable I/O on a many-core architecture

引用

2010 10th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2010

作者： Hicks, Michael A. Van Tol, Michiel W. Jesshope, Chris R. Informatics Institute University of Amsterdam Netherlands

ISBN: (纸本)9781424479382

The limitations of conventional processor performance scaling mean that general purpose many-core processors are increasingly becoming a reality. Conventional hardware device input/output (I/O), interrupt handling and operating system stacks scale poorly and are inefficient when compared with the parallelism that these architectures provide. Many-core I/O requires a decentralised approach where not every core is directly connected to the I/O infrastructure. As such, this paper discusses a software and hardware model designed to take full advantage of I/O parallelism in the Self-adaptive Virtual Processor (SVP) concurrency model and the Microgrid many-core architecture. The generic software I/O stack presented describes a high-level method by which clients and I/O resources can communicate and synchronise in a parallel and decentralised environment. The associated hardware implementation provides a facility to the higher-level interface through the introduction of specialised I/O Cores which enable direct high-speed communication between external devices and the bespoke on-chip Cache-Only Memory Architecture (COMA). ©2010 IEEE.

关键词： Parallel architectures

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Reducing execution unit leakage power in embedded processors

Reducing execution unit leakage power in embedded processors

引用

6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Homayoun, Houman Baniasadi, Amirali Univ Victoria Dept Elect & Comp Engn Victoria BC Canada

ISBN: (纸本)3540364102

We introduce low-overhead power optimization techniques to reduce leakage power in embedded processors. Our techniques improve previous work by a) taking into account idle time distribution for different execution units, and b) using instruction decode and control dependencies to wakeup the gated (but needed) units as soon as possible. We take into account idle time distribution per execution unit to detect an idle time period as soon as possible. This in turn results in increasing our leakage power savings. In addition, we use information already available in the processor to predict when a gated execution unit will be needed again. This results in early and less costly reactivation of gated execution units. We evaluate our techniques for a representative subset of MiBench benchmarks and for a processor using a configuration similar to Intels Xscale processor. We show that our techniques reduce leakage power considerably while maintaining performance.

关键词： Program processors

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Reconfigurable multiple operation array

Reconfigurable multiple operation array

引用

5th international Workshop on embedded computer systems - architectures, modeling, and simulation

作者： Calderon, H Vassiliadis, S Delft Univ Technol EEMCS Comp Engn Lab Dept Elect Engn Delft Netherlands

ISBN: (纸本)354026969X

In this paper, we investigate the collapsing of eight multi-operand addition related operations into a single and common (3:2) counter array. We consider for this unit multiplication in integer and fractional representations, the Sum of Absolute Differences (SAD) in unsigned, signed magnitude and two's complement notation. Furthermore, the unit also incorporates a Multiply-Accumulation unit, (MAC) for two's complement notation. The proposed multiple operation unit was constructed around 10 element arrays that can be reduced using well known counter techniques, which are feed with the necessary data to perform the proposed eight operations: It is estimated that 6/8 of the basic (3:2) counter array is shared by the operations. The obtained results of the presented unit indicates that is capable of processing a 4x4 SAD macro-block in 36.35 ns and takes 30.43 ns to process the rest of the operations using a VIRTEX 11 PRO xc2vp100-7ff1696 FPGA device.

关键词： embedded systems

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Efficient static buffering to guarantee throughput-optimal FPGA implementation of synchronous dataflow graphs

Efficient static buffering to guarantee throughput-optimal F...

引用

2010 10th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2010

作者： Kee, Hojin Bhattacharyya, Shuvra S. Kornerup, Jacob Department of Electrical and Computer Engineering University of Maryland College Park MD 20742 United States National Instruments Corp. Austin TX 78759 United States

ISBN: (纸本)9781424479382

When designing DSP applications for implementation on field programmable gate arrays (FPGAs), it is often important to minimize consumption of limited FPGA resources while satisfying real-time performance constraints. In this paper, we develop efficient techniques to determine dataflow graph buffer sizes that guarantee throughput-optimal execution when mapping synchronous dataflow (SDF) representations of DSP applications onto FPGAs. Our techniques are based on a novel two-actor SDF graph Model (TASM), which efficiently captures the behavior and costs associated with SDF graph edges (flowgraph connections). With our proposed techniques, designers can automatically generate upper bounds on SDF graph buffer distributions that realize maximum achievable throughput performance for the corresponding applications. Furthermore, our proposed techinque is characterized by low polynomial time complexity, which is useful for rapid prototyping in DSP system design. ©2010 IEEE.

关键词： Throughput

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Software/network Co-simulation of heterogeneous industrial networks architectures

Software/network Co-simulation of heterogeneous industrial n...

引用

Proceedings - IEEE international conference on computer Design: VLSI in computers and Processors, ICCD 2004

作者： Fummi, F. Martini, S. Monguzzi, M. Perbellini, G. Poncino, M. Universitá di Verona Verona Italy Sitek S.p.A S.G. Lupatoto Italy Embedded Systems Design Center Verona Italy

ISBN: (纸本)0769522319

The work presents a modeling and analysis framework for heterogeneous industrial networks architectures which is based on a tight integration of a network simulator with embedded software, middleware and a real-time operating system. This framework is suitable for modeling and simulating the behavior of typical components involved in factory automation applications (e.g., PLCs, remote controllers, operational screens, etc.) when they are connected through heterogeneous industrial networks. Experiments show that the framework allows to take early architectural decisions by evaluating the expected system performance based on the available models. © 2004 IEEE.

关键词： computer architecture

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Energy-aware design space exploration of registerfile for extensible processors

Energy-aware design space exploration of registerfile for ex...

引用

2010 10th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2010

作者： Yazdanbakhsh, Amir Kamal, Mehdi Salehi, Mostafa E. Noori, Hamid Fakhraie, Sied Mehdi Silicone Intelligence and VLSI Systems Laboratory School of Electrical and Computer Engineering University of Tehran Tehran 14395-515 Iran Low-Power High-Performance Nanosystems Laboratory School of Electrical and Computer Engineering University of Tehran Tehran 14395-515 Iran

ISBN: (纸本)9781424479382

This paper describes an energy-aware methodology that identifies custom instructions for critical code segments, given the available data bandwidth constraint between custom logic and a base processor. Our approach enables designers to optionally constrain the number of input and output operands for custom instructions to reach the acceptable performance considering the energy dissipation of the registerfile. We describe a design flow to identify promising area, performance, and power tradeoffs. We study the effect of custom instruction I/O constraints and registerfile input/output (I/O) ports on overall performance and energy usage of the registerfile. Our experiments show that, in most cases, the solutions with the highest performance are not identified with relaxed I/O constraints. Results for packet-processing benchmarks covering cryptography and lookup applications are shown, with speed-ups between 25% and 40%, and energy reduction between 20% and 30%. ©2010 IEEE.

关键词： Energy dissipation

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Pre-simulation elaboration of heterogeneous systems: The SystemC multi-disciplinary virtual prototyping approach 15

Pre-simulation elaboration of heterogeneous systems: The Sys...

引用

15th international conference on embedded computer systems: architectures, modeling and simulation, SAMOS 2015

作者： Aoun, Cédric Ben Andrade, Liliana Maehne, Torsten Pêcheux, François Louërat, Marie-Minerve Vachouxy, Alain Sorbonne Universités UPMC Univ Paris 06 CNRS UMR 7606 Paris France LSM Lausanne Switzerland

ISBN: (纸本)9781467373111

Designers of the upcoming digital-centric More-than-Moore systems are lacking a common design and simulation environment able to efficiently manage all the multi-disciplinary aspects of its components of various nature that closely interact with each other. A key to successful design and verification lies in a SystemC-based virtual prototyping environment that is able to simulate a complex heterogeneous system as a whole, for which each component is described and solved using the most appropriate Model of Computation (MoC). In this paper, we present a new generic MoC-independent elaboration scheme that aims at preparing a Virtual Prototype (VP) for simulation. It requires to check the correct composition of the system model through dimensional analysis, to explore the model structure to identify involved MoC and interfaces between MoCs, and to detect the underlying dependencies. Eventually, information extracted from the exploration allow the instantiation of MoC-specific solvers. To soundly handle the global model execution with a Discrete Event (DE) kernel as the main solver, synchronization mechanisms with master-slave semantics within the model structure are implicitly deduced. © 2015 IEEE.

关键词： Virtual prototyping

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A hardware accelerated configurable ASIP architecture for embedded real-time video-based driver assistance applications

A hardware accelerated configurable ASIP architecture for em...

引用

2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Schewior, Gregor Flatt, Holger Dolar, Carsten Banz, Christian Blume, Holger Leibniz Universität Hannover Institute of Microelectronic Systems Appelstr. 4 30167 Hannover Germany

ISBN: (纸本)9781457708008

In this paper, a flexible HW architecture for video-based driver assistance applications is presented. It comprises a customizable and extensible processor template and several task-specific HW accelerators. The proposed heterogeneous architecture allows utilization of the programmable processor core for control and low data rate tasks. For the acceleration of computationally intensive tasks of the application, special functional units and custom instructions can be added to the processor template to form an application specific instruction set processor (ASIP). Moreover, dedicated HW accelerators can be attached to the ASIP. To compare the diverse design options, a shape detection application for traffic sign detection is utilized as case study. It is shown that single tasks of a pure software implementation can be significantly accelerated by usage of special functional units by a factor of up to 35 and by usage of HW accelerators of up to 243. The proposed architecture has been mapped onto an FPGA and it could be shown that a realtime capable system can be realized. © 2011 IEEE.

关键词： Automobile drivers

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Power Models Supporting Energy-Efficient Co-Design on Ultra-Low Power embedded systems

Power Models Supporting Energy-Efficient Co-Design on Ultra-...

引用

international conference on embedded computer systems - architectures, modeling and simulation (SAMOS)

作者： Vi Ngoc-Nha Tran Barry, Brendan Phuong Hoai Ha UiT Arctic Univ Norway Dept Comp Sci Tromso Norway Movidius Ltd Dublin Ireland

ISBN: (纸本)9781509030767

The energy efficiency of computing systems can be enhanced via power models that provide insights into how the systems consume power. However, there are no application general, fine-grained and validated power models which can provide insights into how a given application running on an ultra-low power (ULP) embedded system consumes power. In this study, we devise new fine-grained power models that provide insights into how a given application consumes power on an ULP embedded system. The models support architecture application co-design by considering both platform and application properties. The models are validated with data from 35 micro-benchmarks and three application kernels, namely dense matrix multiplication, sparse matrix vector multiplication and breadth first search, on Movidius Myriad, an ultra-low power embedded system. The absolute percentage errors of the model are at most 8.5% for micro-benchmarks and 12% for application kernels. Based on the models, we propose a framework predicting when to apply race-to-halt (RTH) strategy (i.e., running an application with a maximum setting) to a given application. For the three validated application kernels, the proposed framework is able to predict when to use RTH and when not to use RTH precisely. The experimental results show that the prediction of our new RTH framework is accurate and we can save up to 61% energy for dense matrix multiplication, 59% energy for sparse matrix vector multiplication by using RTH and 5% energy for breadth first search by not using RTH.

关键词： Mathematical model Computational modeling Data transfer embedded systems Kernel Low-power electronics Data models embedded systems powered models low-power electronics data transmission data models Computational modeling Kernel Energy sources Mathematical Model Matrix multiplication Energy efficiency Seeds ULP Co-design Power (Psychology)

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A hardware/software architecture for tool path computation. An application to turning lathe machining

A hardware/software architecture for tool path computation. ...

引用

2007 international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2007

作者： Cuenca, Sergio Martínez, Antonio Jimeno, Antonio Sánchez, Jose Luis Computer Science Technology and Computation Department University of Alicante Apdo. Correos 99 03080 Alicante Spain

ISBN: (纸本)1424410584

Tool path generation is one of the most complex problems in computer Aided Manufacturing. Although some efficient strategies have been developed, most of them are only useful for standard machining. The algorithm called Virtual Digitizing avoids this problem by its own definition but its computing cost is high and makes it difficult for being integrated in standard machining in order to adopt the new ISO standard 14649. Presented in the paper there is a Virtual Digitizing hardware/software architecture that takes advantage of Field Programmable Gate Arrays (FPGAs) to improve the algorithm efficiency and to meet the actual restrictions of the traditional computer Numeric Control systems at the same time. In order to evaluate the architecture, a prototype was implemented using a commercial reconfigurable platform integrated within a CNC lathe for shoe last machining. The performance of the system for tool path generation was measured for different trajectory and surface precisions using a database of real shoe models. The experiments show a significant speedup for all the cases and maintaining the error of the results below the maximum allowed. ©2007 IEEE.

关键词： computer control systems

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