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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

共 2834 条记录，以下是31-40 订阅

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Automatic Search-Space Compression in System-Level Design Space Exploration Using Deep Generative Models 21st

Automatic Search-Space Compression in System-Level Design Sp...

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21st international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Richthammer, Valentina Glass, Michael Ulm Univ Inst Embedded Syst Real Time Syst Ulm Germany

ISBN: (纸本)9783031045806;9783031045790

Major challenges for system-level Design Space Exploration (DSE) include (a) tremendous search-space sizes for modern many-core architectures and networked systems and (b) the preponderance of infeasible solutions in the search space from which no actual implementations can be derived. Since current DSE approaches are not equipped to handle these developments, we propose the integration of deep generative models into DSE to automatically compress large-scale search spaces, thus (I) reducing problem complexity faced by the optimizer while (II) learning a model of feasible solutions to focus the optimization on. The proposed approach is seamlessly integrated into state-of-the-art DSE flows, is complementary to existing search-space pruning techniques, and its potential to improve optimization quality by up to approximate to 66% is demonstrated for a variety of DSE problems.

关键词： Design automation Deep learning Compression

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A Hybrid Performance Prediction Approach for Fully-Connected Artificial Neural Networks on Multi-core Platforms 22nd

A Hybrid Performance Prediction Approach for Fully-Connected...

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22nd international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Dariol, Quentin Le Nours, Sebastien Pillement, Sebastien Stemmer, Ralf Helms, Domenik Gruettner, Kim Nantes Univ IETR UMR CNRS 6164 Nantes France German Aerosp Ctr DLR SE Cologne Germany

ISBN: (纸本)9783031150746;9783031150739

Predicting the performance of Artificial Neural Networks (ANNs) on embedded multi-core platforms is tedious. Concurrent accesses to shared resources are hard to model due to congestion effects on the shared communication medium, which affect the performance of the application. Most approaches focus therefore on evaluation through systematic implementation and testing or through the building of analytical models, which tend to lack of accuracy when targeting a wide range of architectures of varying complexity. In this paper we present a hybrid modeling environment to enable fast yet accurate timing prediction for fully-connected ANNs deployed on multi-core platforms. The modeling flow is based on the integration of an analytical computation time model with a communication time model which are both calibrated through measurement inside a system level simulation using SystemC. The ANN is described using the Synchronous DataFlow (SDF) Model of Computation (MoC), which offers a strict separation of communications and computations and thus enables the building of separated computation and communication time models. The proposed flow enables the prediction of the end-to-end latency for different mappings of several fully-connected ANNs with an average of 99.5% accuracy between the created models and real implementation.

关键词： Performance prediction Multi-processor systems SystemC simulation models Artificial neural networks

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A Data-Driven Approach to Lightweight DVFS-Aware Counter-Based Power modeling for Heterogeneous Platforms 22nd

A Data-Driven Approach to Lightweight DVFS-Aware Counter-Bas...

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22nd international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Mazzola, Sergio Benz, Thomas Forsberg, Bjoern Benini, Luca Swiss Fed Inst Technol Integrated Syst Lab IIS Zurich Switzerland Univ Bologna DEI Bologna Italy

ISBN: (纸本)9783031150746;9783031150739

Computing systems have shifted towards highly parallel and heterogeneous architectures to tackle the challenges imposed by limited power budgets. These architectures must be supported by novel power management paradigms addressing the increasing design size, parallelism, and heterogeneity while ensuring high accuracy and low overhead. In this work, we propose a systematic, automated, and architecture-agnostic approach to accurate and lightweight DVFS-aware statistical power modeling of the CPU and GPU sub-systems of a heterogeneous platform, driven by the sub-systems' local performance monitoring counters (PMCs). Counter selection is guided by a generally applicable statistical method that identifies the minimal subsets of counters robustly correlating to power dissipation. Based on the selected counters, we train a set of lightweight, linear models characterizing each sub-system over a range of frequencies. Such models compose a lookup-table-based system-level model that efficiently captures the non-linearity of power consumption, showing desirable responsiveness and decomposability. We validate the system-level model on real hardware by measuring the total energy consumption of an NVIDIA Jetson AGX Xavier platform over a set of benchmarks. The resulting average estimation error is 1.3%, with a maximum of 3.1%. Furthermore, the model shows a maximum evaluation runtime of 500 ns, thus implying a negligible impact on system utilization and applicability to online dynamic power management (DPM).

关键词： Power modeling Energy estimation Performance counters Heterogeneous systems Linear models

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SIDAM: A Design Space Exploration Framework for Multi-sensor embedded systems Powered by Energy Harvesting 22nd

SIDAM: A Design Space Exploration Framework for Multi-sensor...

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22nd international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Sixdenier, Pierre-Louis Wildermann, Stefan Ziegler, Daniel Teich, Juergen Friedrich Alexander Univ Erlangen Nurnberg FAU Erlangen Germany

ISBN: (纸本)9783031150746;9783031150739

Multi-sensor embedded systems often consist of a central unit being responsible to manage a heterogeneous set of attached sensors. Particularly when such systems are deployed in areas without access to a static power supply, they have to be powered using energy harvesting to operate autonomously. Objectives such as availability and data loss rate depend on the set of attached sensors, the system configuration (e.g., used photovoltaic (PV) module, batteries, and data storage), as well as environmental factors such as the location of the deployed system. Moreover, also the employed energy management strategy and its parametrization severely influence the system characteristics. In fact, different strategies can lead to different tradeoffs in terms of the above objectives. In this paper we propose a design methodology to automatically explore the design space of configurations of multi-sensor embedded systems and to determine and configure the best energy management strategy for a given sensor configuration and location. Our methodology includes a real-time analysis and a simulation-based DSE to explore the design space. We investigate a case study from a biomonitoring project and demonstrate the benefits of the proposed design methodology: A system-including its configuration and energy management strategy-has to be tailored to the characteristics of the set of attached sensors and the location it operates. Else designs exhibit suboptimal characteristics when operating at sites or for sensor sets for which they were not optimized.

关键词： Design space exploration Energy harvesting Energy management embedded systems

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A Critical Assessment of DRAM-PIM architectures - Trends, Challenges and Solutions 22nd

A Critical Assessment of DRAM-PIM Architectures - Trends, Ch...

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22nd international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Sudarshan, Chirag Sadi, Mohammad Hassani Steiner, Lukas Weis, Christian Wehn, Norbert TU Kaiserslautern Microelect Syst Design Res Grp Kaiserslautern Germany

ISBN: (纸本)9783031150746;9783031150739

Recently, we are witnessing a surge in DRAM-based Processing in Memory (PIM) publications from academia and industry. The architectures and design techniques proposed in these publications vary largely, ranging from integration of computation units in the DRAM IO region (i.e., without modifying DRAM core circuits) to modifying the highly optimized DRAM sub-arrays inside the banks for computation operations. Additionally, the underlying memory type, e.g., DDR4, LPDDR4, GDDR6 and HBM2, for DRAM-PIM is also different. This paper presents the assessment of DRAM-PIM architectural design decisions adapted in all DRAM-PIM publications. Our study presents an in-depth analysis of computation unit placement location, i.e., from the chip-level down to DRAM sub-array-level, and discusses the implementation challenges for a computation unit in various regions of commodity DRAM architectures. We also elaborate on the architectural bottlenecks associated with the scalability of DRAM-PIM performance and energy gains, and present architectural approaches to address the issues. Finally, our assessment covers other important design dimensions, such as computation data formats and DRAM-PIM memory controller design.

关键词： Processing-in-Memory PIM DRAM CNN DNN

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The Dataflow Abstract Machine Simulator Framework 51

The Dataflow Abstract Machine Simulator Framework

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ACM/IEEE 51st Annual international Symposium on computer Architecture (ISCA)

作者： Zhang, Nathan Lacouture, Rubens Sohn, Gina Mure, Paul Zhang, Qizheng Kjolstad, Fredrik Olukotun, Kunle Stanford Univ Stanford CA 94305 USA MIT 77 Massachusetts Ave Cambridge MA 02139 USA

ISBN: (纸本)9798350326598;9798350326581

The growing interest in novel dataflow architectures and streaming execution paradigms has created the need for a simulator optimized for modeling dataflow systems. To fill this need, we present three new techniques that make it feasible to simulate complex systems consisting of thousands of components. First, we introduce an interface based on Communicating Sequential Processes which allows users to simultaneously describe functional and timing characteristics. Second, we introduce a scalable point-to-point synchronization scheme that avoids global synchronization. Finally, we demonstrate a technique to exploit slack in the simulated system, such as FIFOs, to increase simulation parallelism. We implement these techniques in the Dataflow Abstract Machine (DAM), a parallel simulator framework for dataflow systems. We demonstrate the benefits of using DAM by highlighting three case studies using the framework. First, we use DAM directly as an exploration tool for streaming algorithms on dataflow hardware. We simulate two different implementations of the attention algorithm used in large language models, and use DAM to show that the second implementation only requires a constant amount of local memory. Second, we re-implement a simulator for a sparse tensor algebra accelerator, resulting in 57% less code and a simulation speedup of up to four orders of magnitude. Finally, we demonstrate a general technique for time-multiplexing real hardware to simulate multiple virtual copies of the hardware using DAM.

关键词： Dataflow Accelerators modeling Parallel Discrete Event simulation

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Hard Edges: Hardware-Based Control-Flow Integrity for embedded Devices 21st

Hard Edges: Hardware-Based Control-Flow Integrity for Embedd...

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21st international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Christou, George Vasiliadis, Giorgos Athanasopoulos, Elias Ioannidis, Sotiris Fdn Res & Technol Hellas FORTH ICS Iraklion Greece Univ Cyprus Nicosia Cyprus Tech Univ Crete TUC ECE Khania Greece

ISBN: (纸本)9783031045806;9783031045790

Control-Flow Integrity (CFI) is a popular technique to defend against State-of-the-Art exploits, by ensuring that every (indirect) control-flow transfer points to a legitimate address and it is part of the Control-flow Graph (CFG) of a program. Enabling CFI in real systems is not straightforward, since in many cases the actual CFG of a program can only be approximated. Even in the case where there is perfect knowledge of the CFG, ensuring that all return instructions will return to their actual call sites, without employing a shadow stack, is questionable. In this work, we explore the implementation of a full-featured CFI-enabled Instruction Set Architecture (ISA) on actual hardware. Our new instructions provide the finest possible granularity for both intra-function and inter-function Control-Flow Integrity. We implement hardware-based CFI (HCFI) by modifying a SPARC SoC and evaluate the prototype on an FPGA board by running SPECInt benchmarks instrumented with a fine-grained CFI policy. HCFI can effectively protect applications from code-reuse attacks, while adding less than 1% average runtime and 2% power consumption overhead, making it particularly suitable for embedded systems.

关键词： System-on-chip

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RVfplib: A Fast and Compact Open-Source Floating-Point Emulation Library for Tiny RISC-V Processors 21st

RVfplib: A Fast and Compact Open-Source Floating-Point Emula...

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21st international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Perotti, Matteo Tagliavini, Giuseppe Mach, Stefan Bertaccini, Luca Benini, Luca Swiss Fed Inst Technol Gloriastr 35 CH-8092 Zurich Switzerland Univ Bologna Viale Risorgimento 2 I-40136 Bologna Italy

ISBN: (纸本)9783031045806;9783031045790

Small, low-cost IoT devices rely on floating-point (FP) software emulation on 32-bit integer cores when the cost of a full-fledged FPU is not affordable. Thus, the performance and code size of the FP emulation library are decisive for meeting energy and memory-size constraints. We propose RVfplib, the first ISA-optimized open-source library for single and double-precision IEEE 754 FP emulation on RV32IM[C] cores. RVfplib is 59% smaller and 2x faster than the GCC emulation library, on average. On benchmark programs, code size reduction is 39%, and performance boost 1.5x. RVfplib is 5.3% smaller than the leading closed-source RISC-V commercial library.

关键词： RISC-V embedded IoT Floating-point Library Size Performance

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NanoController: A Minimal and Flexible Processor Architecture for Ultra-Low-Power Always-On System State Controllers 22nd

NanoController: A Minimal and Flexible Processor Architectur...

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22nd international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Weissbrich, Moritz Paya-Vaya, Guillermo Tech Univ Carolo Wilhelmina Braunschweig Chair Chip Design Embedded Comp Muhlenpfordtstr 22-23 D-38106 Braunschweig Germany

ISBN: (纸本)9783031150746;9783031150739

Distributed nodes in IoT and wireless sensor networks, which are powered by small batteries or energy harvesting, are constrained to very limited energy budgets. By intelligent power management and power gating strategies for the main microcontroller of the system, the energy efficiency can be significantly increased. However, timer-based, periodical power-up sequences are too inflexible to implement these strategies, and the use of a programmable power management controller demands minimum area and ultra-low power consumption from this system part itself. In this paper, the NanoController processor architecture is proposed, which is intended to be used as a flexible system state controller in the always-on domain of smart devices. The NanoController features a compact ISA, minimal silicon area and power consumption, and enables the implementation of efficient power management strategies in comparison to much simpler and constrained always-on timer circuits. For a power management control application of an electronic door lock, the NanoController is compared to small state-of-the-art controller architectures and has up to 86% smaller code size and up to 92% less silicon area and power consumption for 65 nm standard cell ASIC implementations.

关键词： Instruction-set architecture Processor architecture Ultra-low-power microcontroller

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Unlocking the Potential of RISC-V Heterogeneous MPSoC: A PANACA-Based Approach to simulation and modeling 23rd

Unlocking the Potential of RISC-V Heterogeneous MPSoC: A PAN...

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23rd international conference on embedded computer systems: architectures, modeling, and simulation, SAMOS 2023

作者： Haase, Julian Ali, Muhammad Göhringer, Diana Chair of Adaptive Dynamic Systems Technische Universität Dresden Dresden Germany Technische Universität Dresden Dresden Germany

ISBN: (纸本)9783031460760

Very early in the hardware development lifecycle, highly abstract simulations are essential to evaluate the performance and functionality of complex designs before they are implemented physically. For Multi-Processor System-on-Chip (MPSoC) designs that incorporate Network-on-Chip (NoC) architectures and RISC-V processors, such simulation platforms are needed. In this work, we extend and combine the PANACA simulation platform with a RISC-V Virtual Prototype to create a highly efficient and flexible MPSoC simulation platform written in SystemC-TLM. This simulation platform is capable of running a variety of applications, e.g. machine learning application, and can even support the use of real-time operating systems such as FreeRTOS. The developed memory mapped network adapters with and without interrupt support provide a seamless interface between the RISC-V processors and the NoC and enables efficient communication between the components via a unified API. This API is written in such a way that the application that uses it can be applied to simulation and hardware without the need to change the application code. Our novel simulation platform has undergone extensively testing against diverse use cases, hardware implementation, and experimental simulations, establishing its accuracy and reliability as an invaluable tool for early-stage hardware development and research. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2023.

关键词： Network-on-chip

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