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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

共 2831 条记录，以下是411-420 订阅

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A GPU implementation for two MIMO-OFDM detectors

A GPU implementation for two MIMO-OFDM detectors

引用

2010 10th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2010

作者： Nyländen, Teemu Janhunen, Janne Silvén, Olli Juntti, Markku Computer Science and Engineering Laboratory University of Oulu Finland Centre for Wireless Communications University of Oulu Finland

ISBN: (纸本)9781424479382

Two real-valued signal models based on selective spanning with fast enumeration (SSFE) and layered orthogonal lattice detector (LORD) algorithms are implemented on a Nvidia graphics processing unit (GPU). A 2 x 2 multiple-input multiple-output (MIMO) antenna system with 16-quadrature amplitude modulation (16-QAM) is assumed. The chosen level update vector for SSFE is based on computer simulation results carried out in MATLAB environment. We implemented the algorithms with Nvidia Quadro FX 1700 GPU and achieved a throughput of 36.06 Mbps for SSFE and 16.8 Mbps for LORD. The results show that the general-purpose graphics processing unit (GPGPU) has the potential to achieve high throughput, presuming a detection algorithm that allows efficient parallel processing. The latency of the control code and partial Euclidean distance (PED) calculations are very small-scale, but the latency of memory loads and stores to the GPUs global memory are significant. We also compare results from the trellis based detector implementation for GPU, where a more powerful GPU and a different detection algorithm are used. The GPUs offer superior computing power and programmability compared to the application specific software defined radio (SDR) designs implemented so far. ©2010 IEEE.

关键词： Graphics processing unit

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Task-based parallel H.264 video encoding for explicit communication architectures

Task-based parallel H.264 video encoding for explicit commun...

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2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Alvanos, Michail Tzenakis, George Nikolopoulos, Dimitrios S. Bilas, Angelos 100 N. Plastira Av. Vassilika Vouton Heraklion GR-70013 Greece Department of Computer Science University of Crete P.O.Box 2208 Heraklion GR-71409 Greece

ISBN: (纸本)9781457708008

Future multi-core processors will necessitate exploitation of fine-grain, architecture-independent parallelism from applications to utilize many cores with relatively small local memories. We use c264, an end-to-end H.264 video encoder for the Cell processor based on x264, to show that exploiting fine-grain parallelism remains challenging and requires significant advancement in runtime support. Our implementation of c264 achieves speedup between 4.7× and 8.6× on six synergistic processing elements (SPEs), compared to the serial version running on the power processing element (PPE). We find that the programming effort associated with efficient parallelization of c264 at fine granularity is highly non-trivial. Hand optimizations may improve performance significantly but are limited eventually by the code restructuring they require. We assess the complexity of exploiting fine-grain parallelism in realistic applications, by identifying optimizations of c264 and the effort they require. © 2011 IEEE.x.

关键词： Video signal processing

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Enhancing network processor simulation speed with statistical input sampling

引用

1st international conference on High-Performance embedded architectures and Compilers

作者： Yu, J Yang, J Chen, SJ Luo, Y Bhuyan, L Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA Univ Calif Riverside Dept Stat Riverside CA 92521 USA

ISBN: (纸本)3540303170

While cycle-accurate simulation tools have been widely used in modeling high-performance processors, such an approach can be hindered by the increasing complexity of the simulation, especially in modeling chip multi-processors with multi-threading such as the network processors (NP). We have observed that for NP cycle level simulation, several days of simulation time covers only about one second of the real-world network traffic. Existing approaches to accelerating simulation are through either code analysis or execution sampling. Unfortunately, they are not applicable in speeding up NP simulations due to the small code size and the iterative nature of NP applications. We propose to sample the traffic input to the NP so that a long packet trace is represented by a much shorter one with simulation error bounded within +/- 3% and 95% confidence. Our method resulted one order of magnitude improvement in the NP simulation speed.

关键词： computer networks

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An adaptive superscalar architecture for embedded systems

An adaptive superscalar architecture for embedded systems

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Internation conference on embedded systems and Applications/international conference on VLSI

作者： Lan, M Biglari-Abhari, M Univ Auckland Dept Elect & Comp Engn Auckland 1 New Zealand

ISBN: (纸本)1932415416

This paper presents an adaptive superscalar architecture for embedded systems based on the characteristics of embedded applications. The architecture uses a hardware-software cooperation solution to achieve dynamic processor resource allocation with minimal hardware overhead while providing some flexibility to the applications and the operating systems. The programmers and compilers can optimize applications by properly reconfiguring the architecture to lower the energy usage while maintaining the required performance level. simulation results show that simple optimizations can result in a 9% improvement in energy consumption and a 7% power reduction at the cost of about 1% performance degradation.

关键词： adaptive architectures low power profile-based power management embedded system architectures energy-aware reconfiguration

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Real-time embedded system for rear-view mirror overtaking car monitoring

Real-time embedded system for rear-view mirror overtaking ca...

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6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Diaz, Javier Ros, Eduardo Mota, Sonia Agis, Rodrigo Univ Granada Dept Arquitectura & Tecnol Computadores Granada Spain Univ Cordoba Dept Informat & Anal Numer Cordoba Spain

ISBN: (纸本)3540364102

The main goal of an overtaking monitor system is the segmentation and tracking of the overtaking vehicle. This application can be addressed through an optic flow driven scheme. We can focus on the rear. mirror visual field by placing a camera on the top of it. If we drive a car, the ego-motion optic flow pattern is more or less unidirectional, i.e. all the static objects and landmarks move backwards while the overtaking cars move forward towards our vehicle. This well structured motion scenario facilitates the segmentation of regular motion patterns that correspond to the overtaking vehicle. Our approach is based on two main processing stages: first, the computation of optical flow using a novel superpipelined and fully parallelized architecture capable to extract the motion information with a frame-rate up to 148 frames per second at VGA resolution (640x480 pixels). Second, a tracking stage based on motion pattern analysis provides an estimated position of the overtaking car. We analyze the system performance, resources and show some promising results using a bank of overtaking car sequences.

关键词： embedded systems

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High throughput and scalable architecture for unified transform coding in embedded H.264/AVC video coding systems

High throughput and scalable architecture for unified transf...

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2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Dias, Tiago Lopez, Sebastian Roma, Nuno Sousa, Leonel INESC-ID Lisbon Rua Alves Redol 9 1000-029 Lisbon Portugal ISELPI Lisbon Rua Alves Redol 9 1000-029 Lisbon Portugal ISTTU Lisbon Rua Alves Redol 9 1000-029 Lisbon Portugal IUMAULPGC Rua Alves Redol9 1000-029 Lisbon Portugal

ISBN: (纸本)9781457708008

An innovative high throughput and scalable multi-transform architecture for H.264/AVC is presented in this paper. This structure can be used as a hardware accelerator in modern embedded systems to efficiently compute the 4×4 forward/inverse integer DCT, as well as the 2-D 4×4 / 2×2 Hadamard transforms. Moreover, its highly flexible design and hardware efficiency allows it to be easily scaled in terms of performance and hardware cost to meet the specific requirements of any given video coding application. Experimental results obtained using a Xilinx Virtex-4 FPGA demonstrate the superior performance and hardware efficiency levels provided by the proposed structure, which presents a throughput per unit of area at least 1.8× higher than other similar recently published designs. Furthermore, such results also showed that this architecture can compute, in realtime, all the above mentioned H.264/AVC transforms for video sequences with resolutions up to UHDV. © 2011 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Neuronal connectivity assessment for epileptic seizure prevention: Parallelizing the generalized partial directed coherence on many-core platforms 14

Neuronal connectivity assessment for epileptic seizure preve...

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14th international conference on embedded computer systems: architectures, modeling and simulation, SAMOS 2014

作者： Georgis, Georgios Reisis, Dionysios Skordilakis, Panagiotis Tsakalis, Konstantinos Shafique, Ashfaque Bin Chatzikonstantis, George Lentaris, George Electronics Lab Faculty of Physics University of Athens Greece School of Electrical Computer and Energy Engineering Arizona State University United States Microlab School of Electrical and Computer Engineering University of Athens Greece

ISBN: (纸本)9781479937707

Research on the prevention of epileptic seizures has led to approaches for future treatment techniques, which rely on the demanding computation of generalized partial directed coherence (GPDC) on electroencephalogram (EEG) data. A fast computation of such metrics is a key factor both for the off-line optimization of algorithmic parameters and for its real-time implementation. Aiming at speeding up the GPDC computations on EEG data, the current paper presents massively parallel computational strategies for implementing the GPDC on many-core architectures. We apply the proposed strategies on commercial and experimental many-core platforms and we compare the results of the computation time of a set of EEG data on the Bulldozer and Ivy Bridge x86-64 serial processors. We test the GPUs of nVidia GTX 550 Ti and GTX 670, which at the best case achieve a significant speedup of 190x and 460x respectively. Moreover, we apply the proposed parallelization strategies on the Single-Chip Cloud computer (SCC), an experimental processor created by Intel Labs. © 2014 IEEE.

关键词： Real time control

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Efficient automated clock gating using CoDeL

Efficient automated clock gating using CoDeL

引用

6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Agarwal, Nainesh Dimopoulos, Nikitas J. Univ Victoria Dept Elect & Comp Engn Victoria BC Canada

ISBN: (纸本)3540364102

We present a highly efficient automated clock gating platform for rapidly developing power efficient hardware architectures. Our language, called CoDeL, allows hardware description at the algorithm level, and thus dramatically reduces design time. We have extended CoDeL to automatically insert clock gating at the behavioral level to reduce dynamic power dissipation in the resulting architecture. This is, to our knowledge, the first hardware design environment that allows an algorithmic description of a component and yet produces a power aware design. To estimate the power savings, we have developed an estimation framework, which is shown to be consistent with the power savings obtained using statistical power analysis using Synopsys tools. To evaluate our platform we use the CoDeL implementation of a counter and various integer transforms used in the realm of DSP (Digital Signal Processing): discrete wavelet transform, discrete cosine transform and an integer transform used in the H.264 (MPEG4 Part 10) video compression standard. These designs are then clock gated using CoDeL and Synopsys. A simulation based power analysis on the designed circuits shows that CoDeL's clock gating performs better than Synopsys' automated clock gating. CoDeL reduces the power dissipation by 83% on average, while Synopsys gives 81% savings.

关键词： computer architecture

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Software pipelining support for transport triggered architecture processors

Software pipelining support for transport triggered architec...

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6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Salmela, Perttu Jaaskelainen, Pekka Jarvinen, Tuomas Takala, Jarmo Tampere Univ Technol FIN-33101 Tampere Finland Nokia Technol Platforms FIN-33721 Tampere Finland

ISBN: (纸本)3540364102

Many telecommunication applications, especially baseband processing, and digital signal processing (DSP) applications call for high-performance implementations due to the complexity of algorithms and high throughput requirements. In general, the required performance is obtained with the aid of parallel computational resources. In these application domains, software implementations are often preferred over fixed-function ASICs due to the flexibility and ease of development. Application-specific instruction-set processor (ASIP) architectures can be used to exploit efficiently the inherent parallelism of the algorithms but still maintaining the flexibility. Use of high-level languages to program processor architectures with parallel resources can lead to inefficient resource utilization and, on the other hand, parallel assembly programming is error prone and tedious. In this paper, the inherent problems of parallel programming and software pipelining are mitigated with parallel language syntax and automatic generation of software pipelined code for the iteration kernels. With the aid of the developed tool support, the underlying performance of a processor architecture with parallel resources can be exploited and full utilization of the main processing resources is obtained for pipelined loop kernels. The given examples show that efficiency can be obtained without reducing the performance.

关键词： computer software

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A system-level synthesis approach from formal application models to generic bus-based MPSoCs

A system-level synthesis approach from formal application mo...

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2010 10th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2010

作者： Gladigau, Jens Gerstlauer, Andreas Haubelt, Christian Streubühr, Martin Teich, Jürgen Department of Computer Science University of Erlangen-Nuremberg Erlangen Germany Department of Electrical and Computer Engineering University of Texas at Austin Austin TX United States

ISBN: (纸本)9781424479382

System-level synthesis is the task of automatically implementing application models as hardware/software systems. It encompasses four basic sub tasks, namely decision making and refinement for both computation and communication. In the past, several system-level synthesis approaches have been proposed. However, it was shown that each of these approaches has drawbacks in at least one of the four sub tasks. In this paper, we present our efforts towards a comprehensive system-level synthesis by combining two academic system-level solutions into a seamless approach that automatically generates pin-accurate implementation-level models starting from a formal application model and generic MPSoC architecture templates. We analyze the system-level synthesis flow and define intermediate representations in terms of transaction level models that serve as link between existing tools. Furthermore, we present the automated transformation between models for combining two design flows. We demonstrate the combined flow on an industrial-strength example and show the benefits of fully automatic exploration and synthesis for rapid and early system-level design. ©2010 IEEE.

关键词： Decision making

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