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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"
2831 条 记 录,以下是421-430 订阅
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SqueezeNext: Hardware-Aware Neural Network Design  31
SqueezeNext: Hardware-Aware Neural Network Design
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IEEE/CVF conference on computer Vision and Pattern Recognition (CVPR)
作者: Gholami, Amir Kwon, Kiseok Wu, Bichen Tai, Zizheng Yue, Xiangyu Jin, Peter Zhao, Sicheng Keutzer, Kurt Univ Calif Berkeley EECS Berkeley CA 94720 USA
One of the main barriers for deploying neural networks on embedded systems has been large memory and power consumption of existing neural networks. In this work, we introduce SqueezeNext, a new family of neural networ... 详细信息
来源: 评论
Proposal of dynamic module library for system level modeling and simulation of dynamically reconfigurable systems
Proposal of dynamic module library for system level modeling...
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20th international conference on VLSI Design held jointly with the 6th international conference on embedded systems
作者: Asano, Kenji Kitamichi, Junji Kuroda, Kenichi NEC Elect Corp Nakahara Ku 1753 Shimonumabe Kawasaki Kanagawa 2118668 Japan Univ Aizu Sch Comp Sci & Engn Aizu Wakamatsu Fukushima 9658580 Japan
In this paper, we propose a library for the system level modeling and simulation of dynamically reconfigurable architectures(DRAs). Using the proposed library, the designer can model the system specifications includin... 详细信息
来源: 评论
Experiences in Speeding Up computer Vision Applications on Mobile Computing Platforms  15
Experiences in Speeding Up Computer Vision Applications on M...
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international conference on embedded computer systems architectures modeling and simulation
作者: Backes, Luna Rico, Alejandro Franke, Bjorn Barcelona Supercomp Ctr Barcelona Spain Univ Edinburgh Edinburgh Midlothian Scotland
computer vision (CV) is widely expected to be the next big thing in mobile computing. The availability of a camera and a large number of sensors in mobile devices will enable CV applications that understand the enviro... 详细信息
来源: 评论
Scheduling Real-time HiL Co-simulation of Cyber-Physical systems on Multi-core architectures  24
Scheduling Real-time HiL Co-simulation of Cyber-Physical Sys...
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24th IEEE international conference on embedded and Real-Time Computing systems and Applications (RTCSA)
作者: Saidi, Salah Eddine Pernet, Nicolas Sorel, Yves IFP Energies Nouvelles Rueil Malmaison France INRIA Paris France
When designing complex cyber-physical systems, engineers have to integrate numerical models from different modeling environments in order to simulate the whole system and estimate its global performances. Co-simulatio... 详细信息
来源: 评论
Power models supporting energy-efficient co-design on ultra-low power embedded systems  16
Power models supporting energy-efficient co-design on ultra-...
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16th international conference on embedded computer systems: architectures, modeling and simulation, SAMOS 2016
作者: Tran, Vi Ngoc-Nha Barry, Brendan Ha, Phuong Hoai Department of Computer Science UiT the Arctic University of Norway Tromso Norway Movidius Ltd. Dublin Ireland
The energy efficiency of computing systems can be enhanced via power models that provide insights into how the systems consume power. However, there are no application-general, fine-grained and validated power models ... 详细信息
来源: 评论
Sunflower:: Full-system, embedded microarchitecture evaluation
<i>Sunflower</i>:: Full-system, embedded microarchitecture e...
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2nd international conference on High Performance embedded architectures and Compilers
作者: Stanley-Marbell, Phillip Marculescu, Diana Carnegie Mellon Univ Dept Elect & Comp Engn Pittsburgh PA 15217 USA
This paper describes Sunflower, a full-system microarchitectural evaluation environment for embedded computing systems. The environment enables detailed microarchitectural simulation of multiple instances of complete ... 详细信息
来源: 评论
LV*: A low complexity lazy versioning HTM infrastructure
LV*: A low complexity lazy versioning HTM infrastructure
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2010 10th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2010
作者: Negi, Anurag Waliullah, M.M. Stenstrom, Per Department of Computer Science and Engineering Chalmers University of Technology Gothenburg Sweden
Transactional memory (TM) promises to unlock parallelism in software in a safer and easier way than lock-based approaches but the path to deployment is unclear for several reasons. First of all, since TM has not been ... 详细信息
来源: 评论
A GPU implementation for two MIMO-OFDM detectors
A GPU implementation for two MIMO-OFDM detectors
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2010 10th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2010
作者: Nyländen, Teemu Janhunen, Janne Silvén, Olli Juntti, Markku Computer Science and Engineering Laboratory University of Oulu Finland Centre for Wireless Communications University of Oulu Finland
Two real-valued signal models based on selective spanning with fast enumeration (SSFE) and layered orthogonal lattice detector (LORD) algorithms are implemented on a Nvidia graphics processing unit (GPU). A 2 x 2 mult... 详细信息
来源: 评论
An adaptive superscalar architecture for embedded systems
An adaptive superscalar architecture for embedded systems
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Internation conference on embedded systems and Applications/international conference on VLSI
作者: Lan, M Biglari-Abhari, M Univ Auckland Dept Elect & Comp Engn Auckland 1 New Zealand
This paper presents an adaptive superscalar architecture for embedded systems based on the characteristics of embedded applications. The architecture uses a hardware-software cooperation solution to achieve dynamic pr... 详细信息
来源: 评论
Task-based parallel H.264 video encoding for explicit communication architectures
Task-based parallel H.264 video encoding for explicit commun...
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2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011
作者: Alvanos, Michail Tzenakis, George Nikolopoulos, Dimitrios S. Bilas, Angelos 100 N. Plastira Av. Vassilika Vouton Heraklion GR-70013 Greece Department of Computer Science University of Crete P.O.Box 2208 Heraklion GR-71409 Greece
Future multi-core processors will necessitate exploitation of fine-grain, architecture-independent parallelism from applications to utilize many cores with relatively small local memories. We use c264, an end-to-end H... 详细信息
来源: 评论