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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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SqueezeNext: Hardware-Aware Neural Network Design 31

SqueezeNext: Hardware-Aware Neural Network Design

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IEEE/CVF conference on computer Vision and Pattern Recognition (CVPR)

作者： Gholami, Amir Kwon, Kiseok Wu, Bichen Tai, Zizheng Yue, Xiangyu Jin, Peter Zhao, Sicheng Keutzer, Kurt Univ Calif Berkeley EECS Berkeley CA 94720 USA

ISBN: (数字)9781538661000

ISBN: (纸本)9781538661000

One of the main barriers for deploying neural networks on embedded systems has been large memory and power consumption of existing neural networks. In this work, we introduce SqueezeNext, a new family of neural network architectures whose design was guided by considering previous architectures such as SqueezeNet, as well as by simulation results on a neural network accelerator. This new network is able to match AlexNet's accuracy on the ImageNet benchmark with 112x fewer parameters, and one of its deeper variants is able to achieve VGG-19 accuracy with only 4.4 Million parameters, (31x smaller than VGG19). SqueezeNext also achieves better top-5 classification accuracy with 1.3x fewer parameters as compared to MobileNet, but avoids using depthwise-separable convolutions that are inefficient on some mobile processor platforms. This wide range of accuracy gives the user the ability to make speed-accuracy tradeoffs, depending on the available resources on the target hardware. Using hardware simulation results for power and inference speed on an embedded system has guided us to design variations of the baseline model that are 2.59x/8.26x faster and 2.25x/7.5x more energy efficient as compared to SqueezeNet/AlexNet without any accuracy degradation.

关键词： Neural networks Hardware computer architecture Semiconductor process modeling embedded systems Power demand Computational modeling

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Proposal of dynamic module library for system level modeling and simulation of dynamically reconfigurable systems

Proposal of dynamic module library for system level modeling...

引用

20th international conference on VLSI Design held jointly with the 6th international conference on embedded systems

作者： Asano, Kenji Kitamichi, Junji Kuroda, Kenichi NEC Elect Corp Nakahara Ku 1753 Shimonumabe Kawasaki Kanagawa 2118668 Japan Univ Aizu Sch Comp Sci & Engn Aizu Wakamatsu Fukushima 9658580 Japan

ISBN: (纸本)9780769527628

In this paper, we propose a library for the system level modeling and simulation of dynamically reconfigurable architectures(DRAs). Using the proposed library, the designer can model the system specifications including modules for the dynamic generation and elimination that are needed in the design of dynamically reconfigurable systems. In addition, we evaluate the proposed library by the modeling and simulation of sample circuits, such as multi-context DRA and partially DRA. Using the proposed library, we can model the system specifications as much the same amount as a detailed description, such as one using multiplexers and de-multiplexers, which is a modeling formula for describing multi-context DRA. Under some conditions, higher-speed simulation is possible using the proposed library.

关键词： Specifications

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Experiences in Speeding Up computer Vision Applications on Mobile Computing Platforms 15

Experiences in Speeding Up Computer Vision Applications on M...

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international conference on embedded computer systems architectures modeling and simulation

作者： Backes, Luna Rico, Alejandro Franke, Bjorn Barcelona Supercomp Ctr Barcelona Spain Univ Edinburgh Edinburgh Midlothian Scotland

ISBN: (纸本)9781467373111

computer vision (CV) is widely expected to be the next big thing in mobile computing. The availability of a camera and a large number of sensors in mobile devices will enable CV applications that understand the environment and enhance people's lives through augmented reality. One of the problems yet to solve is how to transfer demanding state-of-the-art CV algorithms designed to run on powerful desktop computers with several GPUs- onto energy-efficient, but slow, processors and GPUs found in mobile devices. To accommodate to the lack of performance, current CV applications for mobile devices are simpler versions of more complex algorithms, which generally run slowly and unreliably and provide a poor user experience. In this paper, we investigate ways to speed up demanding CV applications to run faster on mobile devices. We selected KinectFusion (KF) as a representative CV application. The KF application constructs a 3D model from the images captured by a Kinect. After porting it to an ARM platform, we applied several optimisation and parallelisation techniques using OpenCL to exploit all the available computing resources. We evaluated the impact on performance and power and demonstrate a 4 x speedup with just a 1.38x power increase. We also evaluated the performance portability of our optimisations by running on a different platform, and assessed similar improvements despite the different multi-core configuration and memory system. By measuring processor temperature, we found overheating to be the main limiting factor for running such high-performance codes on a mobile device not designed for full continuous utilisation.

关键词： Speeding Mobile devices images computer vision CATACLYSMIC VARIABLE STARS Mobile Computing desktop computers game player experience Platform Cache Memory System Energy efficiency three-dimensional displays KF

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Scheduling Real-time HiL Co-simulation of Cyber-Physical systems on Multi-core architectures 24

Scheduling Real-time HiL Co-simulation of Cyber-Physical Sys...

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24th IEEE international conference on embedded and Real-Time Computing systems and Applications (RTCSA)

作者： Saidi, Salah Eddine Pernet, Nicolas Sorel, Yves IFP Energies Nouvelles Rueil Malmaison France INRIA Paris France

ISBN: (纸本)9781538677599

When designing complex cyber-physical systems, engineers have to integrate numerical models from different modeling environments in order to simulate the whole system and estimate its global performances. Co-simulation refers to such joint simulation of heterogeneous models. If some parts of the system are physically available, it is possible to connect these parts to the co-simulation in a Hardware-in-the-Loop (HiL) approach. In this case, the simulation has to be performed in real-time where models execution consists in periodically reacting to the real (physically available) components and providing periodic output updates. This paper deals with the parallelization and scheduling of real-time Hardware-in-the-Loop co-simulation of numerical models on multi-core architectures. A method for defining real-time constraints that have to be met is proposed. Also, an ILP formulation as well as a heuristic are proposed to solve the problem of scheduling the co-simulation on a multi-core architecture while satisfying the previously defined real-time constraints. The proposed approach is evaluated for different sizes of co-simulations and multi-core processors.

关键词： co-simulation HiL scheduling real-time multi-core

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Power models supporting energy-efficient co-design on ultra-low power embedded systems 16

Power models supporting energy-efficient co-design on ultra-...

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16th international conference on embedded computer systems: architectures, modeling and simulation, SAMOS 2016

作者： Tran, Vi Ngoc-Nha Barry, Brendan Ha, Phuong Hoai Department of Computer Science UiT the Arctic University of Norway Tromso Norway Movidius Ltd. Dublin Ireland

ISBN: (纸本)9781509030767

The energy efficiency of computing systems can be enhanced via power models that provide insights into how the systems consume power. However, there are no application-general, fine-grained and validated power models which can provide insights into how a given application running on an ultra-low power (ULP) embedded system consumes power. In this study, we devise new fine-grained power models that provide insights into how a given application consumes power on an ULP embedded system. The models support architecture-application co-design by considering both platform and application properties. The models are validated with data from 35 micro-benchmarks and three application kernels, namely dense matrix multiplication, sparse matrix vector multiplication and breadth first search, on Movidius Myriad, an ultra-low power embedded system. The absolute percentage errors of the model are at most 8.5% for micro-benchmarks and 12% for application kernels. Based on the models, we propose a framework predicting when to apply race-to-halt (RTH) strategy (i.e., running an application with a maximum setting) to a given application. For the three validated application kernels, the proposed framework is able to predict when to use RTH and when not to use RTH precisely. The experimental results show that the prediction of our new RTH framework is accurate and we can save up to 61% energy for dense matrix multiplication, 59% energy for sparse matrix vector multiplication by using RTH and 5% energy for breadth first search by not using RTH. © 2016 IEEE.

关键词： Energy efficiency

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Sunflower:: Full-system, embedded microarchitecture evaluation

<i>Sunflower</i>:: Full-system, embedded microarchitecture e...

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2nd international conference on High Performance embedded architectures and Compilers

作者： Stanley-Marbell, Phillip Marculescu, Diana Carnegie Mellon Univ Dept Elect & Comp Engn Pittsburgh PA 15217 USA

ISBN: (纸本)9783540693376

This paper describes Sunflower, a full-system microarchitectural evaluation environment for embedded computing systems. The environment enables detailed microarchitectural simulation of multiple instances of complete embedded systems, their peripherals, and medium access control / physical layer communication between systems. The environment models the microarchitecture, computation and communication upset events under a variety of stochastic distributions, compute and communication power consumption, electrochemical battery systems, and power regulation circuitry, as well as analog signals external to the processing elements. The simulation environment provides facilities for speeding up simulation performance, which tradeoff accuracy of simulated properties for simulation speed. Through the detailed simulation of benchmarks in which the effect of simulation speedup on correctness can be accurately quantified, it is demonstrated that traditional techniques proposed for simulation speedup can introduce significant error when simulating a combination of computation and analog physical phenomena external to a processor.

关键词： Software architecture

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LV*: A low complexity lazy versioning HTM infrastructure

LV*: A low complexity lazy versioning HTM infrastructure

引用

2010 10th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2010

作者： Negi, Anurag Waliullah, M.M. Stenstrom, Per Department of Computer Science and Engineering Chalmers University of Technology Gothenburg Sweden

ISBN: (纸本)9781424479382

Transactional memory (TM) promises to unlock parallelism in software in a safer and easier way than lock-based approaches but the path to deployment is unclear for several reasons. First of all, since TM has not been deployed in any machine yet, experience of using it is limited. While software transactional memory implementations exist, they are too slow to provide useful experience. Existing hardware transactional memory implementations, on the other hand, can provide the efficiency required but they require a significant effort to integrate in cache coherence infrastructures or freeze critical policy parameters. This paper proposes the LV* (lazy versioning and eager/lazy conflict resolution) class of hardware transactional memory protocols. This class of protocols has been implemented with ease of deployment in mind. LV* can be integrated with low additional complexity in standard snoopy-cache MESI-protocols and can be accommodated in a directory-based cache coherence infrastructure. Since the optimal conflict resolution policy (lazy or eager) depends on transactional characteristics of workloads, LV* supports a set of conflict resolution policies that range from LazEr - a family of Lazy versioning Eager conflict resolution protocols - to LL-MESI which provides lazy resolution. We show that LV* can be hosted in a MESI protocol through straightforward extensions and that the flexibility in the choice of conflict resolution strategy has a significant impact on performance. ©2010 IEEE.

关键词： Parallel architectures

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A GPU implementation for two MIMO-OFDM detectors

A GPU implementation for two MIMO-OFDM detectors

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2010 10th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2010

作者： Nyländen, Teemu Janhunen, Janne Silvén, Olli Juntti, Markku Computer Science and Engineering Laboratory University of Oulu Finland Centre for Wireless Communications University of Oulu Finland

ISBN: (纸本)9781424479382

Two real-valued signal models based on selective spanning with fast enumeration (SSFE) and layered orthogonal lattice detector (LORD) algorithms are implemented on a Nvidia graphics processing unit (GPU). A 2 x 2 multiple-input multiple-output (MIMO) antenna system with 16-quadrature amplitude modulation (16-QAM) is assumed. The chosen level update vector for SSFE is based on computer simulation results carried out in MATLAB environment. We implemented the algorithms with Nvidia Quadro FX 1700 GPU and achieved a throughput of 36.06 Mbps for SSFE and 16.8 Mbps for LORD. The results show that the general-purpose graphics processing unit (GPGPU) has the potential to achieve high throughput, presuming a detection algorithm that allows efficient parallel processing. The latency of the control code and partial Euclidean distance (PED) calculations are very small-scale, but the latency of memory loads and stores to the GPUs global memory are significant. We also compare results from the trellis based detector implementation for GPU, where a more powerful GPU and a different detection algorithm are used. The GPUs offer superior computing power and programmability compared to the application specific software defined radio (SDR) designs implemented so far. ©2010 IEEE.

关键词： Graphics processing unit

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An adaptive superscalar architecture for embedded systems

An adaptive superscalar architecture for embedded systems

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Internation conference on embedded systems and Applications/international conference on VLSI

作者： Lan, M Biglari-Abhari, M Univ Auckland Dept Elect & Comp Engn Auckland 1 New Zealand

ISBN: (纸本)1932415416

This paper presents an adaptive superscalar architecture for embedded systems based on the characteristics of embedded applications. The architecture uses a hardware-software cooperation solution to achieve dynamic processor resource allocation with minimal hardware overhead while providing some flexibility to the applications and the operating systems. The programmers and compilers can optimize applications by properly reconfiguring the architecture to lower the energy usage while maintaining the required performance level. simulation results show that simple optimizations can result in a 9% improvement in energy consumption and a 7% power reduction at the cost of about 1% performance degradation.

关键词： adaptive architectures low power profile-based power management embedded system architectures energy-aware reconfiguration

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Task-based parallel H.264 video encoding for explicit communication architectures

Task-based parallel H.264 video encoding for explicit commun...

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2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Alvanos, Michail Tzenakis, George Nikolopoulos, Dimitrios S. Bilas, Angelos 100 N. Plastira Av. Vassilika Vouton Heraklion GR-70013 Greece Department of Computer Science University of Crete P.O.Box 2208 Heraklion GR-71409 Greece

ISBN: (纸本)9781457708008

Future multi-core processors will necessitate exploitation of fine-grain, architecture-independent parallelism from applications to utilize many cores with relatively small local memories. We use c264, an end-to-end H.264 video encoder for the Cell processor based on x264, to show that exploiting fine-grain parallelism remains challenging and requires significant advancement in runtime support. Our implementation of c264 achieves speedup between 4.7× and 8.6× on six synergistic processing elements (SPEs), compared to the serial version running on the power processing element (PPE). We find that the programming effort associated with efficient parallelization of c264 at fine granularity is highly non-trivial. Hand optimizations may improve performance significantly but are limited eventually by the code restructuring they require. We assess the complexity of exploiting fine-grain parallelism in realistic applications, by identifying optimizations of c264 and the effort they require. © 2011 IEEE.x.

关键词： Video signal processing

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