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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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Towards the Reproduction of Selected Dynamic Loop Scheduling Experiments Using SimGrid-SimDag 19

Towards the Reproduction of Selected Dynamic Loop Scheduling...

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19th IEEE international conference on High Performance Computing and Communications (HPCC) / 15th IEEE international conference on Smart City (SmartCity) / 3rd IEEE international conference on Data Science and systems (DSS)

作者： Mohammed, Ali Eleliemy, Ahmed Ciorba, Florina M. Univ Basel Dept Math & Comp Sci Basel Switzerland

ISBN: (纸本)9781538625880

Modern computing architectures exhibit increasing parallelism. Therefore, dynamic loop scheduling (DLS) plays an increasing role in the performance optimization of parallel applications executing on the modern computing architectures. In the previous decades, there was a large body of research concerning DLS techniques. Reproduction of the DLS experiments is significant for ensuring the trustworthiness of the DLS techniques implementation in modern scheduling tools or within new scientific applications. The results of executing the implemented DLS techniques are expected to be in agreement with the results reported in earlier work. The present work is a step towards the reproduction of the experiments that introduced the well-known DLS technique named factoring (FAC). Studying scheduling techniques via simulation is favorable compared to native execution to have control over all the factors that may affect the performance. The use of simulation in this work is essential for the reproduction of the scheduling experiments performed on computing systems that no longer exist. This work shows that the self scheduling technique with matrix multiplication kernel has a significantly poorer performance on the modern system considered in this study than on the past system.

关键词： Processor scheduling Kernel Computational modeling Task analysis Dynamic scheduling Convolution computer architecture

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DISCOVER THE EFFECTIVE STRATEGY FOR FACE RECOGNITION MODEL COMPRESSION BY IMPROVED KNOWLEDGE DISTILLATION

DISCOVER THE EFFECTIVE STRATEGY FOR FACE RECOGNITION MODEL C...

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IEEE international conference on Image Processing

作者： Mengjiao Wang Rujie Liu Narishige Abe Hidetsugu Uchida Tomoaki Matsunami Shigefumi Yamada Fujitsu R&D Center Co. LTD Beijing China Fujitsu Laboratories Ltd. Kawasaki Japan

For the sake of better accuracy, the face recognition model is becoming larger and larger, which makes them difficult to be deployed on embedded systems. This work proposes an effective model compression method using knowledge distillation, where a fast student model is trained under the guidance of a complex teacher model. Firstly, different loss combinations and network architectures are analyzed through comprehensive experiments to find the most effective approach. To augment the performance, the feature layer is further normalized to make the optimization objective consistent with cosine similarity metric. Moreover, a teacher weighting strategy is proposed to address the issue when teacher provides wrong guidance. Experimental results show that the student model built by our approach can surpass the teacher model while achieving 3× acceleration.

关键词： Face recognition Computational modeling computer architecture Optimization Degradation Training Mathematical model

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Proceedings - 2010 international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2010

Proceedings - 2010 International Conference on Embedded Comp...

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2010 10th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2010

ISBN: (纸本)9781424479382

The proceedings contain 46 papers. The topics discussed include: cycle-accurate performance modeling in an ultra-fast just-in-time dynamic binary translation instruction set simulator;a trace-based scenario database for high-level simulation of multimedia MP-SoCs;a library of dual-clock FIFOs for cost-effective and flexible MPSoCs design;transparent sampling;design of a flexible high-speed FPGA-based flow monitor for next generation networks;a fully programmable FSM-based processing engine for gigabytes/s header parsing;empirical evaluation of data transformations for network infrastructure applications;design environment for the support of configurable network interfaces in NoC-based platforms;an efficient realization of forward integer transform in H.264/AVC intra-frame encoder;SIMD performance in software based mobile video coding;and real-time stereo vision system using semi-global matching disparity estimation: architecture and FPGA-implementation.

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Implementing a space-aware stochastic simulator on low-power architectures: a systems biology case study 25

Implementing a space-aware stochastic simulator on low-power...

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25th Euromicro international conference on Parallel, Distributed and Network-Based Processing (PDP)

作者： Morganti, Lucia Corni, Elena Ferraro, Andrea Cesini, Daniele D'Agostino, Daniele Merelli, Ivan Italian Inst Nucl Phys CNAF Bologna Italy Natl Res Council Italy Inst Appl Math & Informat Technol E Magenes Genoa Italy Natl Res Council Italy Inst Biomed Technol Segrate Mi Italy

ISBN: (纸本)9781509060580

In the last decade, different computing paradigms and modelling frameworks for the description and simulation of biochemical systems based on stochastic modelling have been proposed. From a computational point of view, many simulations of the model are necessary to identify the behaviour of the system. The execution of thousands of simulations can require huge amount of time, therefore the parallelization of these algorithms is highly desirable. In particular, models that consider the size of volumes and objects involved in the reaction are very time-consuming, since many rules should be considered to take into account the position of the different molecules. In this work we present an implementation of a stochastic space-aware simulator which exploits the benefit and features of hybrid low-power computing architectures. This work shows that the simulator dynamic probabilistic approach to select possible chemical reactions can be applied and implemented in hybrid low-power low-cost architectures as well as current industry high-end servers.

关键词： Computational modeling Biological system modeling Stochastic processes computer architecture Evolution (biology) Biomembranes Power system dynamics

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Performance Evaluation of State Estimators for Airborne Target Tracking Using Multi Sensor Data Fusion

Performance Evaluation of State Estimators for Airborne Targ...

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IEEE international conference on Electro-Information Technology

作者： David S.R. Kondru Mehmet Celenk School of Electrical Engineering and Computer Science Ohio University Athens Ohio USA

The main function of range sensory systems under a given dynamic environment is to detect, discriminate and track a particular target for surveillance in case of a friendly target or an enemy target interception. The combination of two or more sensors will provide better position estimate than a single sensor. In this paper, the advantages of the multi sensor data fusion is presented and compared over conventional single sensor tracking. The state estimation techniques are utilized to enhance position accuracy in a single and multi-sensor environment. The performance of each state estimator is evaluated by considering different target motions along with their nonlinear characteristics. The state estimators presented here varies from simple linear filters such as fixed gain and Kalman filters to complex nonlinear filters such as Particle filter. Two widely used Extended Kalman filter based fusion architectures such as measurement fusion and state vector fusion are explored. The data is simulated from two ground based sensors RADAR and FLIR (forward looking infra red) to examine the fusion process. The RMS error is computed in range, azimuth, and elevation angles. A complete mathematical modeling and simulation is implemented in MATLAB. It is found that fusion architectures have demonstrated better performance in tracking accuracy.

关键词： Radar tracking Target tracking Kalman filters Mathematical model Atmospheric measurements Azimuth

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Special session on architectures and design tools for secure embedded systems

Special session on architectures and design tools for secure...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Francesco Regazzoni ALaRI - USI Lugano Switzerland

ISBN: (纸本)9781538634387;9781538634370

Summary form only given, as follows. The complete presentation was not made available for publication as part of the conference proceedings. The pervasive diffusion of embedded and cyberphysical systems connected to form the internet of things brings new security challenges. These devices are usually deployed in a hostile environment, where an attacker could easily have physical access, and their life span can be pretty long, thus posing the problem of long term security. Yet, security functionalities should fit the tight area and energy budget available in these devices. To address these challenges, researchers are investigating several research directions, including novel constructions withstanding future attacks carried out by quantum computational power, novel and more powerful physical attacks and new approaches to defeat them. It is thus of crucial importance that designers of embedded systems are aware of the most important security challenges which need to be addressed during design and that they have the proper basic blocks and tools to solve them in a correct and effective way. This special session covers challenges and opportunities related with design and deployment of secure embedded systems in several platforms. Talks in the session will present more targeted side channel attacks, more efficient architectures for implementing elliptic curve cryptography (ECC) and number theoretic transform (NTT), a crucial block for implementing quantum resistant algorithms, and will summarize current research effort in secure processors design and in the use of reconfigurable architectures for secure applications.

关键词： computer architecture embedded systems Elliptic curve cryptography Design tools Cyber-physical systems Internet of Things

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Performance comparison of position based routing protocols for VANETs

Performance comparison of position based routing protocols f...

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2017 international conference on Internet of Things, embedded systems and Communications, IINTEC 2017

作者： Ashtaiwi, Abduladhim Saoud, Abdusadik Department of Computer Engineering American University of the Middle East Kuwait Department of Electrical and Computer Engineering Libyan Academy Libya

ISBN: (纸本)9781538621134

Many safety and infotainment applications of Vehicular Ad hoc Networks (VANETs) depend on the robustness and reliability of the routing protocols. There are many routing protocols proposed for VANETs in the literature, only position based routing protocols are proven to be more suitable for VANETs. Some work in the literature evaluated the performance of position based routing protocols using different models, approaches and simulation tools. In order to get valuable results that reflect as close as possible the real implementations, detailed models that consider all aspects of real implementation must be considered. In this work we evaluate the routing performance of two position based routing protocols, namely, Greedy Perimeter Stateless Routing (GPSR) and Greedy Perimeter Coordinator Routing (GPCR). To cover most of the details of VANETs mobility and road infrastructures, we use two simulation tools: VanetMobiSim and NS-2. VanetMobiSim models the macro and micro aspects of vehicular networks and road infrastructures. In macro level modeling, VanetMobiSim considers all the road infrastructure details and in micro level modeling, VanetMobiSim considers all mobility aspects of vehicular networks. NS-2 simulation tool is used to model all the communication related aspects that included in network, MAC, and physical layers. The obtained results showed that GPCR perform better than GPSR under different combination of vehicular speeds, vehicular densities, and transmission ranges. Both protocols suffer performance degradation under high vehicular speeds, however, under the same circumstances, GPCR is still performing better than GPSR. © 2017 IEEE.

关键词： Vehicular ad hoc networks

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Memristor-CMOS Analog Co-Processor for Acceleration of High Performance Computing Applications

Memristor-CMOS Analog Co-Processor for Acceleration of High ...

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international conference on Current Trends towards Converging Technologies (ICCTCT)

作者： Nihar Athreyas Qiangfei Xia Dev Gupta Wenhao Song Abbie Mathew J. Joshua Yang Blair Perot Jai Gupta University of Massachusetts Amherst MA U.S.A Spero Devices MA U.S.A Spero Devices Acton MA U.S.A

Vector matrix multiplication computation underlies major applications in machine vision, deep learning and scientific simulation. These applications require high computational speed and are run on platforms that are size, weight and power constrained. With the transistor scaling coming to an end, existing digital hardware architectures will not be able to meet this increasing demand. Analog computation with its rich set of primitives and inherent parallel architecture can be faster, more efficient and compact for some of these applications. One such primitive is a memristor-CMOS crossbar array based vector matrix multiplication. In this paper, we develop a memristor-CMOS analog co-processor architecture that can handle floating point computation. The crossbar array is based on a TaOx memristor device. To demonstrate the working of the analog co-processor at a system level, we use a new tool developed by Cadence and Mathworks called PSpice systems Option which performs integrated co-simulation of MATLAB/Simulink and PSpice. It is shown that the analog co-processor has a superior performance when compared to other processors. Using the new PSpice systems Option tool, various application simulations for image processing and solution to partial differential equations are performed on the analog coprocessor model.

关键词： Memristors computer architecture Virtual machine monitors Microprocessors Engines Computational modeling Mathematical model

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Quantum Accelerators for High-Performance Computing systems

Quantum Accelerators for High-Performance Computing Systems

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IEEE international conference on Rebooting Computing (ICRC)

作者： Britt, Keith A. Mohiyaddin, Fahd A. Humble, Travis S. Oak Ridge Natl Lab Quantum Comp Inst Oak Ridge TN USA

ISBN: (纸本)9781538615539

We define some of the programming and system-level challenges facing the application of quantum processing to high-performance computing. Alongside barriers to physical integration, prominent differences in the execution of quantum and conventional programs challenges the intersection of these computational models. Following a brief overview of the state of the art, we discuss recent advances in programming and execution models for hybrid quantum-classical computing. We discuss a novel quantum-accelerator framework that uses specialized kernels to offload select workloads while integrating with existing computing infrastructure. We elaborate on the role of the host operating system to manage these unique accelerator resources, the prospects for deploying quantum modules, and the requirements placed on the language hierarchy connecting these different system components. We draw on recent advances in the modeling and simulation of quantum computing systems with the development of architectures for hybrid high-performance computing systems and the realization of software stacks for controlling quantum devices. Finally, we present simulation results that describe the expected system-level behavior of high-performance computing systems composed from compute nodes with quantum processing units. We describe performance for these hybrid systems in terms of time-to-solution, accuracy, and energy consumption, and we use simple application examples to estimate the performance advantage of quantum acceleration.

关键词： Quantum computing Registers Programming Computational modeling computer architecture Software Acceleration

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Application of Quantum Cellular Automata in Image Steganography with an Improved Fault Tolerant Majority Voter

Application of Quantum Cellular Automata in Image Steganogra...

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IEEE international conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)

作者： H P Bhavana Adiga R. Jayagowri VLSI Design and Embedded System B M S College of Engineering Bengaluru India

ISBN: (数字)9781538624401

ISBN: (纸本)9781538624418

Quantum Cellular Automata (QCA) is one of the powerful alternative to CMOS technology because of its low power and high speed. Because of the nano structure, Quantum dot cells are prone to get displaced or omitted during fabrication. Thus, it is very important to have the architecture of QCA gates to be resistant to such fabrication errors. Though many architectures have already been proposed for providing fault tolerance, percentage of fault tolerance provided by them is less than the architecture that we are proposing in this paper. In this paper we are proposing a new architecture to Majority Voter(MV) so as to make it fault tolerant to fabrication errors. We have also compared the proposed architecture to the existing ones for the cell misplacement effects namely single cell omission, extra cell deposition. Also, kink energy associated with the proposed architecture is calculated and is proved that the proposed architecture dissipates less power. Fault tolerant encoder and decoder are designed and simulated using the proposed fault tolerant MV. These encoders and decoders find application in Image Steganography.

关键词： Fault tolerance Fault tolerant systems computer architecture Decoding Fabrication Logic gates simulation

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