检索结果-内蒙古大学图书馆

Enhancing network processor simulation speed with statistical input sampling

1st international conference on High-Performance embedded architectures and Compilers

作者： Yu, J Yang, J Chen, SJ Luo, Y Bhuyan, L Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA Univ Calif Riverside Dept Stat Riverside CA 92521 USA

ISBN: (纸本)3540303170

While cycle-accurate simulation tools have been widely used in modeling high-performance processors, such an approach can be hindered by the increasing complexity of the simulation, especially in modeling chip multi-processors with multi-threading such as the network processors (NP). We have observed that for NP cycle level simulation, several days of simulation time covers only about one second of the real-world network traffic. Existing approaches to accelerating simulation are through either code analysis or execution sampling. Unfortunately, they are not applicable in speeding up NP simulations due to the small code size and the iterative nature of NP applications. We propose to sample the traffic input to the NP so that a long packet trace is represented by a much shorter one with simulation error bounded within +/- 3% and 95% confidence. Our method resulted one order of magnitude improvement in the NP simulation speed.

关键词： computer networks

来源：评论

学校读者我要写书评

暂无评论

A simulation-based methodology for evaluating the DPA-resistance of cryptographic functional units with application to CMOS and MCML technologies

A simulation-based methodology for evaluating the DPA-resist...

引用

2007 international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2007

作者： Regazzoni, Francesco Badel, Stéphane Eisenbarth, Thomas Großschädl, Johann Poschmann, Axel Toprak, Zeynep Macchetti, Marco Pozzi, Laura Paar, Christof Leblebici, Yusuf Ienne, Paolo ALaRI University of Lugano Lugano Switzerland School of Engineering EPFL Lausanne Switzerland Horst Görtz Institute for IT Security Ruhr University Bochum Germany Department of Computer Science University of Bristol United Kingdom Milan Italy Faculty of Informatics University of Lugano Lugano Switzerland School of Computer and Communication Sciences EPFL Lausanne Switzerland

ISBN: (纸本)1424410584

This paper explores the resistance of MOS Current Mode Logic (MCML) against Differential Power Analysis (DPA) attacks. Circuits implemented in MCML, in fact, have unique characteristics both in terms of power consumption and the dependency of the power profile from the input signal pattern. Therefore, MCML is suitable to protect cryptographic hardware from DPA and similar side-channel attacks. In order to demonstrate the effectiveness of different logic styles against power analysis attacks, the non-linear bijective function of the Kasumi algorithm (known as substitution box S7) was implemented with CMOS and MCML technology, and a set of attacks was performed using power traces derived from SPICE-level simulations. Although all keys were discovered for CMOS, only very few attacks to MCML were successful. ©2007 IEEE.

关键词： Side channel attack

来源：评论

学校读者我要写书评

暂无评论

A Model-Based Concept for RTOS Portability 15

A Model-Based Concept for RTOS Portability

引用

15th IEEE/ACS international conference on computer systems and Applications (AICCSA)

作者： Gomes, Renata Martins Baunach, Marcel Graz Univ Technol Graz Austria

ISBN: (纸本)9781538691205

The amount and diversity of connected computing platforms in the Internet of Things (IoT) is expected to increase exponentially throughout the next years, together with their dependability requirements. This imposes many challenges to software and hardware developers and calls for safe and secure real-time operating systems (RTOSs) that are portable to different or changing hardware. Middleware ports, including RTOS ports, must keep functional and non-functional behavior constant towards the application. Current middleware portability approaches for embedded systems, however, are arduous and error prone. We present a novel approach towards portability of embedded RTOSs based on the formal, hardware-independent and detailed specification of RTOS kernels. With additional models of relevant MCU properties and instruction set architectures (ISA), we are able to generate low level RTOS code for different target architectures. This paper focuses on the hardware-independent model of the context switch within a multi-tasking RTOS. With the general approach, we expect to (1) reduce the effort for maintaining and porting RTOS code, as well as the (2) likeliness for errors, (3) make it easier to test new kernel concepts during OS development, (4) improve security by modeling different levels of access permissions for memory or peripherals depending on the execution mode, and (5) improve safety by formally proving the correctness and consistency of the models.

关键词： RTOS portability code generation formal modeling Event-B IoT

来源：评论

学校读者我要写书评

暂无评论

modeling reflex-healing autonomy for large-scale embedded systems

引用

IEEE TRANSACTIONS ON systems MAN AND CYBERNETICS PART C-APPLICATIONS AND REVIEWS 2006年第3期36卷 292-303页

作者： Nordstrom, Steven G. Shetty, Shweta S. Neema, Sandeep K. Bapty, Theodore A. Vanderbilt Univ Inst Software Integrated Syst Nashville TN 37235 USA

High-energy physics experiments require an extraordinary amount of real-time computation, and the computers implementing the online data processing must be very reliable because of the large cost associated with operating the facilities and the potential for loss of irreplaceable data. Conventional redundancy-based fault tolerance and adaptive approaches are not appropriate because of the tremendous system cost (fault tolerance is limited to a maximum of 10% overhead). In this work, we developed a framework for building robust embedded systems, which utilizes an autonomic reflex-healing approach to achieve fault tolerance. Components of the framework implement user-defined failure adaptation strategies within the context of a large-scale embedded environment. The tools embrace a model-based approach combining design specification and code-generation for both simulation and system implementation. In this paper we present the concepts and entities of the reflex and healing framework.

关键词： autonomic computing behavioral modeling embedded large scale

来源：评论

学校读者我要写书评

暂无评论

Design of infrared power meter reading system based on embedded linux operation system

Design of infrared power meter reading system based on embed...

引用

2010 international conference on computer modeling and simulation, ICCMS 2010

作者： Zhang, Yuhua Zhang, Yifei Henan University of Urban Construction China

ISBN: (纸本)9780769539416

Along with the close combination of computer technology and industry application, general computer is no longer the leading role of information industry and embedded computer system is becoming a promising young star of computer age gradually. Aimed at the application of embedded system in electric energy meter reading, this paper finishes reading and saving data from an infrared electric energy meter and realizes infrared meter-reading function by writing driver and application of relevant hardware part. © 2010 IEEE.

关键词： computer operating systems

来源：评论

学校读者我要写书评

暂无评论

Benchmarking mesh and hierarchical bus networks in system-on-chip context

引用

JOURNAL OF systems ARCHITECTURE 2007年第8期53卷 477-488页

作者： Salminen, Erno Kangas, Tero Lahtinen, Vesa Riihimaki, Jouni Kuusilinna, Kimmo Hamalainen, Timo D. Nokia Technol Platforms Tampere Finland Nokia Res Ctr Tampere Finland

The performance and area of a System-on-Chip depend on the utilized communication method. This paper presents simulation-based comparison of generic, synthesizable single bus, hierarchical bus, and 2-dimensional mesh on-chip networks. Performance of the network depends heavily on the application and therefore six test cases with multiple parameter values are used. Furthermore, two versions of each network topology are compared. The results show that hierarchical bus scales well to large number of agents and offers a good performance and area trade-off although it has smaller aggregate bandwidth and area than mesh. Hierarchical HIBI bus achieves runtimes comparable to 2-dimensional cut-through mesh with about 50% smaller network logic. However, depending on the test case, the runtime can be reduced by 20-50% when wider bus links are utilized. (c) 2006 Published by Elsevier B.V.

关键词： on-chip network simulation benchmark hierarchical bus mesh

来源：评论

学校读者我要写书评

暂无评论

Design and Implementation of a simulation Framework for the ARM embedded System

Design and Implementation of a Simulation Framework for the ...

引用

UKSim 10th international conference on computer Modelling and simulation (EUROSIM/UKSim)

作者： Wan Han Gao Xiaopeng Deng Libo Yu Ting Beijing Univ Aeronaut & Astronaut Dept Comp Sci Beijing Peoples R China

ISBN: (纸本)9780769531144

This paper proposes a basic ARM full system simulation framework, a novel approach to understanding the behavior of modern embedded systems. Our simulation framework implements the kernel architecture of the ARM ISA, on which one can run and debug system or user-level programs. It has flexible software architecture, and good encapsulation of the communication between virtual peripherals and host peripherals. On the other hand, we implement a remote debugging system based on our simulation kernel, which extends remote serial protocol (RSP) of GDB and using Eclipse as the front-UI to build a platform-independent system. Since the simulation kernel has the full control of the target programs, the debugging system provides a flexible mechanism to collect the simulation information. These allowed people use or extend it to build a new ARM development environment, in order to study the embedded systems or help investigating the embedded operating system and low-level software.

关键词： embedded system Kernel Debugging computer architecture Instruction sets Software architecture Encapsulation Protocols Communication system control Operating systems

来源：评论

学校读者我要写书评

暂无评论

High throughput and scalable architecture for unified transform coding in embedded H.264/AVC video coding systems

High throughput and scalable architecture for unified transf...

引用

2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Dias, Tiago Lopez, Sebastian Roma, Nuno Sousa, Leonel INESC-ID Lisbon Rua Alves Redol 9 1000-029 Lisbon Portugal ISELPI Lisbon Rua Alves Redol 9 1000-029 Lisbon Portugal ISTTU Lisbon Rua Alves Redol 9 1000-029 Lisbon Portugal IUMAULPGC Rua Alves Redol9 1000-029 Lisbon Portugal

ISBN: (纸本)9781457708008

An innovative high throughput and scalable multi-transform architecture for H.264/AVC is presented in this paper. This structure can be used as a hardware accelerator in modern embedded systems to efficiently compute the 4×4 forward/inverse integer DCT, as well as the 2-D 4×4 / 2×2 Hadamard transforms. Moreover, its highly flexible design and hardware efficiency allows it to be easily scaled in terms of performance and hardware cost to meet the specific requirements of any given video coding application. Experimental results obtained using a Xilinx Virtex-4 FPGA demonstrate the superior performance and hardware efficiency levels provided by the proposed structure, which presents a throughput per unit of area at least 1.8× higher than other similar recently published designs. Furthermore, such results also showed that this architecture can compute, in realtime, all the above mentioned H.264/AVC transforms for video sequences with resolutions up to UHDV. © 2011 IEEE.

关键词： Field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Efficient automated clock gating using CoDeL

Efficient automated clock gating using CoDeL

引用

6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Agarwal, Nainesh Dimopoulos, Nikitas J. Univ Victoria Dept Elect & Comp Engn Victoria BC Canada

ISBN: (纸本)3540364102

We present a highly efficient automated clock gating platform for rapidly developing power efficient hardware architectures. Our language, called CoDeL, allows hardware description at the algorithm level, and thus dramatically reduces design time. We have extended CoDeL to automatically insert clock gating at the behavioral level to reduce dynamic power dissipation in the resulting architecture. This is, to our knowledge, the first hardware design environment that allows an algorithmic description of a component and yet produces a power aware design. To estimate the power savings, we have developed an estimation framework, which is shown to be consistent with the power savings obtained using statistical power analysis using Synopsys tools. To evaluate our platform we use the CoDeL implementation of a counter and various integer transforms used in the realm of DSP (Digital Signal Processing): discrete wavelet transform, discrete cosine transform and an integer transform used in the H.264 (MPEG4 Part 10) video compression standard. These designs are then clock gated using CoDeL and Synopsys. A simulation based power analysis on the designed circuits shows that CoDeL's clock gating performs better than Synopsys' automated clock gating. CoDeL reduces the power dissipation by 83% on average, while Synopsys gives 81% savings.

关键词： computer architecture

来源：评论

学校读者我要写书评

暂无评论

architectures for distributed information systems supporting environmental simulation 20

Architectures for distributed information systems supporting...

引用

XXth international conference of the Chilean-computer-Science-Society (SCCC 2000)

作者： Unger, S Asselmeyer, T GMD FIRST D-12489 Berlin Germany

ISBN: (纸本)0769508103

Different distributed environmental simulation systems are presented They take advantage of the possibilities of modern network technologies to gather input data, perform simulation and spread the simulation results. The term 'distributed' applies in this context both to the simulation, this is a parallel (distributed) simulation on computer networks, and to the fact, that all components (pre- and postprocessing and the simulation models) may reside in different locations and will be accessed via the Web. The systems described use this architecture to a different extent. Based on this it is shown, that it should be possible to build a system which links various data sources, simulation models, visualization and information tools, all of them running possibly remotely on the corresponding hardware. Such a system would form a distributed virtual laboratory.

关键词： Air pollution Atmospheric measurements Computational modeling computer simulation Context modeling Data visualization Distributed information systems Modems Pollution measurement Soil

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：