While cycle-accurate simulation tools have been widely used in modeling high-performance processors, such an approach can be hindered by the increasing complexity of the simulation, especially in modeling chip multi-p...
详细信息
ISBN:
(纸本)3540303170
While cycle-accurate simulation tools have been widely used in modeling high-performance processors, such an approach can be hindered by the increasing complexity of the simulation, especially in modeling chip multi-processors with multi-threading such as the network processors (NP). We have observed that for NP cycle level simulation, several days of simulation time covers only about one second of the real-world network traffic. Existing approaches to accelerating simulation are through either code analysis or execution sampling. Unfortunately, they are not applicable in speeding up NP simulations due to the small code size and the iterative nature of NP applications. We propose to sample the traffic input to the NP so that a long packet trace is represented by a much shorter one with simulation error bounded within +/- 3% and 95% confidence. Our method resulted one order of magnitude improvement in the NP simulation speed.
This paper explores the resistance of MOS Current Mode Logic (MCML) against Differential Power Analysis (DPA) attacks. Circuits implemented in MCML, in fact, have unique characteristics both in terms of power consumpt...
详细信息
The amount and diversity of connected computing platforms in the Internet of Things (IoT) is expected to increase exponentially throughout the next years, together with their dependability requirements. This imposes m...
详细信息
ISBN:
(纸本)9781538691205
The amount and diversity of connected computing platforms in the Internet of Things (IoT) is expected to increase exponentially throughout the next years, together with their dependability requirements. This imposes many challenges to software and hardware developers and calls for safe and secure real-time operating systems (RTOSs) that are portable to different or changing hardware. Middleware ports, including RTOS ports, must keep functional and non-functional behavior constant towards the application. Current middleware portability approaches for embeddedsystems, however, are arduous and error prone. We present a novel approach towards portability of embedded RTOSs based on the formal, hardware-independent and detailed specification of RTOS kernels. With additional models of relevant MCU properties and instruction set architectures (ISA), we are able to generate low level RTOS code for different target architectures. This paper focuses on the hardware-independent model of the context switch within a multi-tasking RTOS. With the general approach, we expect to (1) reduce the effort for maintaining and porting RTOS code, as well as the (2) likeliness for errors, (3) make it easier to test new kernel concepts during OS development, (4) improve security by modeling different levels of access permissions for memory or peripherals depending on the execution mode, and (5) improve safety by formally proving the correctness and consistency of the models.
High-energy physics experiments require an extraordinary amount of real-time computation, and the computers implementing the online data processing must be very reliable because of the large cost associated with opera...
详细信息
High-energy physics experiments require an extraordinary amount of real-time computation, and the computers implementing the online data processing must be very reliable because of the large cost associated with operating the facilities and the potential for loss of irreplaceable data. Conventional redundancy-based fault tolerance and adaptive approaches are not appropriate because of the tremendous system cost (fault tolerance is limited to a maximum of 10% overhead). In this work, we developed a framework for building robust embeddedsystems, which utilizes an autonomic reflex-healing approach to achieve fault tolerance. Components of the framework implement user-defined failure adaptation strategies within the context of a large-scale embedded environment. The tools embrace a model-based approach combining design specification and code-generation for both simulation and system implementation. In this paper we present the concepts and entities of the reflex and healing framework.
Along with the close combination of computer technology and industry application, general computer is no longer the leading role of information industry and embeddedcomputer system is becoming a promising young star ...
详细信息
The performance and area of a System-on-Chip depend on the utilized communication method. This paper presents simulation-based comparison of generic, synthesizable single bus, hierarchical bus, and 2-dimensional mesh ...
详细信息
The performance and area of a System-on-Chip depend on the utilized communication method. This paper presents simulation-based comparison of generic, synthesizable single bus, hierarchical bus, and 2-dimensional mesh on-chip networks. Performance of the network depends heavily on the application and therefore six test cases with multiple parameter values are used. Furthermore, two versions of each network topology are compared. The results show that hierarchical bus scales well to large number of agents and offers a good performance and area trade-off although it has smaller aggregate bandwidth and area than mesh. Hierarchical HIBI bus achieves runtimes comparable to 2-dimensional cut-through mesh with about 50% smaller network logic. However, depending on the test case, the runtime can be reduced by 20-50% when wider bus links are utilized. (c) 2006 Published by Elsevier B.V.
This paper proposes a basic ARM full system simulation framework, a novel approach to understanding the behavior of modern embeddedsystems. Our simulation framework implements the kernel architecture of the ARM ISA, ...
详细信息
ISBN:
(纸本)9780769531144
This paper proposes a basic ARM full system simulation framework, a novel approach to understanding the behavior of modern embeddedsystems. Our simulation framework implements the kernel architecture of the ARM ISA, on which one can run and debug system or user-level programs. It has flexible software architecture, and good encapsulation of the communication between virtual peripherals and host peripherals. On the other hand, we implement a remote debugging system based on our simulation kernel, which extends remote serial protocol (RSP) of GDB and using Eclipse as the front-UI to build a platform-independent system. Since the simulation kernel has the full control of the target programs, the debugging system provides a flexible mechanism to collect the simulation information. These allowed people use or extend it to build a new ARM development environment, in order to study the embeddedsystems or help investigating the embedded operating system and low-level software.
An innovative high throughput and scalable multi-transform architecture for H.264/AVC is presented in this paper. This structure can be used as a hardware accelerator in modern embeddedsystems to efficiently compute ...
详细信息
We present a highly efficient automated clock gating platform for rapidly developing power efficient hardware architectures. Our language, called CoDeL, allows hardware description at the algorithm level, and thus dra...
详细信息
ISBN:
(纸本)3540364102
We present a highly efficient automated clock gating platform for rapidly developing power efficient hardware architectures. Our language, called CoDeL, allows hardware description at the algorithm level, and thus dramatically reduces design time. We have extended CoDeL to automatically insert clock gating at the behavioral level to reduce dynamic power dissipation in the resulting architecture. This is, to our knowledge, the first hardware design environment that allows an algorithmic description of a component and yet produces a power aware design. To estimate the power savings, we have developed an estimation framework, which is shown to be consistent with the power savings obtained using statistical power analysis using Synopsys tools. To evaluate our platform we use the CoDeL implementation of a counter and various integer transforms used in the realm of DSP (Digital Signal Processing): discrete wavelet transform, discrete cosine transform and an integer transform used in the H.264 (MPEG4 Part 10) video compression standard. These designs are then clock gated using CoDeL and Synopsys. A simulation based power analysis on the designed circuits shows that CoDeL's clock gating performs better than Synopsys' automated clock gating. CoDeL reduces the power dissipation by 83% on average, while Synopsys gives 81% savings.
Different distributed environmental simulationsystems are presented They take advantage of the possibilities of modern network technologies to gather input data, perform simulation and spread the simulation results. ...
详细信息
ISBN:
(纸本)0769508103
Different distributed environmental simulationsystems are presented They take advantage of the possibilities of modern network technologies to gather input data, perform simulation and spread the simulation results. The term 'distributed' applies in this context both to the simulation, this is a parallel (distributed) simulation on computer networks, and to the fact, that all components (pre- and postprocessing and the simulation models) may reside in different locations and will be accessed via the Web. The systems described use this architecture to a different extent. Based on this it is shown, that it should be possible to build a system which links various data sources, simulation models, visualization and information tools, all of them running possibly remotely on the corresponding hardware. Such a system would form a distributed virtual laboratory.
暂无评论