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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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The Development of Multi-axis embedded CNC System Based on Dual-core Chip

The Development of Multi-axis Embedded CNC System Based on D...

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2018 international conference on computer modeling, simulation and Algorithm（CMSA2018）

作者： Xu Liu Haixin Zou Xiangfa Kong Jun Lu Shenzhen youqi lighting co.LTD. Shenzhen Institute of Information Technology Engineering Training Center School of Mechanical and Automotive Engineering South China University of Technology Guangzhou Institutes of Biomedicine and Health GIBH Chinese Academy of Sciences

At present, from the selection of the chip to the molding of the product, the embedded CNC system will encounter various problems, such as insufficient performance of the processor, hidden dangers of the physical communication scheme between the chips, insufficient reconfigurability of the platform, and transmission rate limitation and so on. This makes the development cycle of the embedded numerical control system very long. This paper combines the rapid development and mature multi-core technology of electronic products, and develops an open multi-core embedded CNC system platform based on highperformance TMS320 DM8148. The overall structure of the platform is based on a multi-core CNC system, including hardware platform construction and circuit design, dual-core and inter-core communication, and dual-core and FPGA high-speed bus communication. The reconfigurability developed by FPGA is used to develop each module in the CNC system and achieve many Axis servo driver control, and finally gives the system startup and control process, the firmware program is written to the dual-core CNC system for actual processing experiments. From the results of the performance test of the CNC system, the indicators could meet or exceed the performance requirements of the existing highperformance CNC systems, and also have open, modular and network control functions. The system platform has been successfully applied Five-axis linkage CNC machine tools, CNC milling machine, CNC engraving machine, all-electric servo CNC bending machine, spring machine and other types of CNC machine tools, reducing the design difficulty, greatly reducing the development cycle, allowing users to focus on solving specific applications Problems, and it thus quickly promote the development of the national economy and the overall level of industrial manufacturing, and has produced a very good economic and social benefits.

关键词： embedded dual-core communication multi-axis linkage FPGA interpolation CNC system

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Work-in-progress: REDEFINE – a case for WCET-friendly hardware accelerators for real time applications

Work-in-progress: REDEFINE – a case for WCET-friendly hardw...

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Proceedings of the international conference on Compilers, architectures and Synthesis for embedded systems (CASES)

作者： Kavitha Madhu Tarun Singla S K Nandy Ranjani Narayan Francois Neumann Philippe Baufreton Indian Institute of Science Morphing Machines Pvt Ltd SAFRAN Electronics & Defense

ISBN: (纸本)9781509065400

REDEFINE is a distributed dynamic datafow architecture, designed for exploiting parallelism at various granularities as an embedded system-on-chip (SoC). This paper dwells on the flexibility of REDEFINE architecture and its execution model in accelerating real-time applications coupled with a WCET analyzer that computes execution time bounds of real time applications.

关键词： Real-time systems Kernel Hardware computer architecture Parallel processing Computational modeling Analytical models

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14th international conference on Parallel Computing Technologies, PaCT 2017

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14th international conference on Parallel Computing Technologies, PaCT 2017

ISBN: (纸本)9783319629315

The proceedings contain 48 papers. The special focus in this conference is on Parallel Computing Technologies. The topics include: Experimenting with a context-aware language;generating maximal domino patterns by cellular automata agents;automated parallelization of a simulation method of elastic wave propagation in media with complex 3D geometry surface on high-performance heterogeneous clusters;parallel algorithm with modulus structure for simulation of seismic wave propagation in 3D multiscale multiphysics media;performance evaluation of two load balancing algorithms on a hybrid parallel architecture;accelerated analysis of biological parameters space using GPUs;fragmentation of IADE method using LuNA system;performance aspects of collocated and staggered grids for particle-in-cell plasma simulation;technological aspects of the hybrid parallelization with openMP and MPI;application of graph models to the parallel algorithms design for the motion simulation of tethered satellite systems;the diamondtetris algorithm for maximum performance vectorized stencil computation;a parallel locally-adaptive 3D model on cartesian nested-type grids;auto-vectorization of loops on intel 64 and intel xeon phi: analysis and evaluation;parallel algorithms for an implicit CFD solver on tree-based grids;software implementation of mathematical model of thermodynamic processes in a steam turbine on high-performance system;predictive modeling of suffocation in shallow waters on a multiprocessor computer system;finite and infinite computations and a classification of two-dimensional cellular automata using infinite computations and multiple-precision residue-based arithmetic library for parallel CPU-GPU architectures: data types and features.

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Implementation of Dead Reckoning Solution on Zynq Target 18

Implementation of Dead Reckoning Solution on Zynq Target

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18th international Carpathian Control conference (ICCC)

作者： Bouzid, Ahmed Vasarhelyi, Jozsef Univ Miskolc Dept Automat & Infocommun Miskolc Hungary

ISBN: (纸本)9781509048625

In the framework of designing a system for the estimation of the position of moving objects, this work treats the case of Dead Reckoning solution. The algorithm uses exteroceptive data coming from two degree of freedom Microelectro mechanical system (MEMS) accelerometer to plot the trajectory of a mass point in a two-dimensional map. The mathematical model of the Dead Reckoning algorithm is based on some parameters that define the behavior of the moving object (which is assumed to be a point mass). modeling and simulation has been done using MATLAB/SIMULINK environment in order to validate the algorithm of the solution. For the purpose of drawing the two-dimensional map describing the trajectory of the moving object, the positions are iteratively calculated using the previous calculated positions and velocities. The solution is implemented to get real time positions with a refresh rate of 10 Hz. It is also about implementing a Dead Reckoning algorithm on the FPGA part of a Zynq target (ZedBoard) and a personal computer to compare results obtained during hardware cosimulation process using System Generator tool from Xilinx.

关键词： Dead Reckoning Position estimation embedded systems Inertial Navigation Xilinx System Generator Zynq

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32nd international conference on High Performance Computing, ISC High Performance 2017

32nd International Conference on High Performance Computing,...

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32nd international conference on High Performance Computing, ISC High Performance 2017

ISBN: (纸本)9783319676296

The proceedings contain 53 papers. The special focus in this conference is on High Performance Computing. The topics include: simulation of hierarchical storage systems for TCO and QoS;gPU erasure coding for campaign storage;pIOM-PX: A framework for modeling the I/O behavior of parallel scientific applications;real-time I/O-monitoring of hpc applications with SIOX, elasticsearch, grafana and FUSE;output performance study on a production petascale filesystem;gPU-accelerated particle-in-cell code on minsky;pushing big data into accelerators: Can the JVM saturate our hardware?;the technological roadmap of parallware and its alignment with the OpenPOWER ecosystem;on the scalability of data reduction techniques in current and upcoming HPC systems from an application perspective;experiences evaluating functionality and performance of IBM POWER8+ systems;power/performance controlling techniques in OpenPOWER;performance evaluation of container-based high performance computing ecosystem using OpenPOWER;pre-exascale architectures: OpenPOWER performance and usability assessment for french scientific community;iXPUG: Experiences on intel knights landing at the one year mark;analyzing performance of selected NESAP applications on the cori HPC system;on the mitigation of cache hostile memory access patterns on many-core CPU architectures;from knights corner to landing: A case study based on a hodgkin-huxley neuron simulator;porting tissue-scale cardiac simulations to the knights landing platform;kART – A runtime compilation library for improving HPC application performance;toward a multi-method approach: Lossy data compression for climate simulation data;performance evaluation of nwchem ab-initio molecular dynamics (AIMD) simulations on the intel® xeon phi™ processor;performance variability on xeon phi;scaling the EOS namespace.

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Proceedings - 2010 international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2010: Preface

Proceedings - 2010 International Conference on Embedded Comp...

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Proceedings - 2010 international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2010 2010年

作者： Kurdahi, Fadi J. Takala, Jarmo

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13th international Symposium on Applied Reconfigurable Computing, ARC 2017

13th International Symposium on Applied Reconfigurable Compu...

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13th international Symposium on Applied Reconfigurable Computing, ARC 2017

ISBN: (纸本)9783319562575

The proceedings contain 28 papers. The special focus in this conference is on Applied Reconfigurable Computing. The topics include: Improving the performance of adaptive cache in reconfigurable VLIW processor;VLIW-based FPGA computation fabric with streaming memory hierarchy for medical imaging applications;an FPGA-based implementation of a pipelined FFT processor for high-speed signal processing applications;soft timing closure for soft programmable logic cores: the ARGen approach;FPGA debugging with MATLAB using a rule-based inference system;hardness analysis and instrumentation of verilog gate level code for FPGA-based designs;a framework for high level simulation and optimization of coarse-grained reconfigurable architectures;parameter sensitivity in virtual FPGA architectures;custom framework for run-time trading strategies;exploring HLS optimizations for efficient stereo matching hardware implementation;architecture reconfiguration as a mechanism for sustainable performance of embedded systems in case of variations in available power;applying TMR in hardware accelerators generated by high-level synthesis design flow for mitigating multiple bit upsets in SRAM-based FPGAs;genomic data clustering on FPGAs for compression;optimizing CNN-based object detection algorithms on embedded FPGA platforms;an FPGA realization of a deep convolutional neural network using a threshold neuron pruning;accuracy evaluation of long short term memory network based language model with fixed-point arithmetic;FPGA implementation of a short read mapping accelerator and a machine learning methodology for cache recommendation.

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Quadratic programming implementations of model predictive control on arduino for BLDC speed control 7

Quadratic programming implementations of model predictive co...

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7th IEEE international conference on System Engineering and Technology, ICSET 2017

作者： Rohman, Arief Syaichu Prasetyo, Hanif Fauzan Laboratory for Control and Computer Systems School of Electrical Engineering and Informatics Institut Teknologi Bandung Bandung West Java40132 Indonesia

ISBN: (纸本)9781538603833

Many physical process systems have performance limitation regardless the input. This limitation usually occurs in the form of input saturation of actuator as the constraint of the system. To overcome this problem, Model Predictive Control (MPC) may be used due to its capability to compute optimal control signal in the presence of input saturation. The optimal control signal is obtained by solving a quadratic programming (QP) problem with variables' constraints at each time instants. QP problem with lower and upper constraint is known to be equivalent to an algebraic loop involving diagonal upper and lower saturation. Hence, QP can be iteratively computed until its solution converges. A slow computation of QP, however, limits its applications for fast systems with simple digital processor. Therefore, in order to be able to be implemented in real-time embedded applications, a fast algorithm of QP solver is in need. In this paper, a comparison study of two QP implementation, i.e. Projected Gauss Seidel (PGS) and so called Algorithm-2, using Arduino Mega 2560 is presented. In this case, MPC with QP solver using both algorithms is implemented to control the speed of lightly loaded BLDC motor. Before implementation, system modeling, controller designing, and simulation are undertaken. The performance of both iterative algorithms are then compared in terms of average computation time in the simulation and implementation. It can be observed from the results that Algorithm-2 gives a bit faster computation than PGS under same conditions. © 2017 IEEE.

关键词： Model predictive control

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An OpenCL-based Framework for Rapid Virtual Prototyping of Heterogeneous architectures 16

An OpenCL-based Framework for Rapid Virtual Prototyping of H...

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international conference on embedded computer systems - architectures, modeling and simulation (SAMOS)

作者： Sotiriou-Xanthopoulos, Efstathios Masing, Leonard Siozios, Kostas Economakos, George Soudris, Dimitrios Becker, Juergen Natl Tech Univ Athens Sch Elect & Comp Engn Athens Greece Karlsruhe Inst Technol Inst Informat Proc Karlsruhe Germany

ISBN: (纸本)9781509030767

The increasing performance and power requirements in embedded systems has lead to a variety of heterogeneous hardware architectures, featuring many different types of processing elements. This heterogeneity however induces extra effort on system development and programming. To address this heterogeneity, OpenCL provides a portable programming model which enables the use of one source code in various architectures featuring different types of processors. Also, such systems impose higher design complexity due to the existence of an increased number of hardware components. Virtual Prototyping aims to alleviate this issue by enabling the hardware modeling in higher abstraction levels. This paper combines the benefits of OpenCL with Virtual Prototyping, by proposing an OpenCL-based framework for rapid prototyping, which (a) automatically derives a virtual prototype from an OpenCL code;(b) executes the OpenCL application by running the host program along with the hardware simulation;and (c) proposes a design flow for faster system evaluation, as compared to state-of-the-art FPGA-based flow. Using a set of OpenCL benchmarks, it is shown that the proposed framework enables faster prototyping by up to 18x, as compared to state-of-the-art flow.

关键词： embedded systems

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Coarse Grained Reconfigurable architectures in the Past 25 Years: Overview and Classification 16

Coarse Grained Reconfigurable Architectures in the Past 25 Y...

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international conference on embedded computer systems - architectures, modeling and simulation (SAMOS)

作者： Wijtvliet, Mark Waeijen, Luc Corporaal, Henk Eindhoven Univ Technol Dept Elect Engn NL-5612 AZ Eindhoven Netherlands

ISBN: (纸本)9781509030767

Reconfigurable architectures become more popular now general purpose compute performance does not increase as rapidly as before. Field programmable gate arrays are slowly moving into the direction of Coarse Grain Reconfigurable architectures (CGRA) by adding DSP and other coarse grained IP blocks, general purpose processors become more heterogeneous and include sub-word parallelism and even some reconfigurable logic. In the past 25 years, several CGRAs have been published. In this paper an overview and classification of these architectures is presented. This work also provides a clear definition of CGRAs and identifies topics for future research which are key to unlock the full potential of CGRAs.

关键词： Coarse Grain Reconfigurable Architecture CGRA Classification

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