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10th international Workshop on Software and Compilers for embedded systems, SCOPES 2007

作者： Kupriyanov, Alexey Kissler, Dmitrij Hannig, Frank Teich, Jürgen Department of Computer Science 12 Hardware-Software-Co-Design University of Erlangen Nuremberg Germany

ISBN: (纸本)9781450378345

In this paper we present a new approach for generating high-speed optimized event-driven instruction set level simulators for adaptive massively parallel processor architectures. The simulator generator is part of a methodology for the systematic mapping, evaluation, and exploration of massively parallel processor architectures that are designed for special purpose applications in the world of embedded computers. The generation of high-speed cycle-accurate simulators is of utmost importance here, because they are directly used both for parallel processor architecture debugging and evaluation purposes, as well as during time-consuming architecture/compiler co-exploration. We developed a modeling environment which automatically generates a C++ simulation model either from a graphical input or directly from an XML-based architecture description. Here, we focus on the underlying event-driven simulation model and present our modeling environment, in particular the features of the graphical parallel processor architecture editor and the automatic instruction set level simulator generator. Finally, in a case-study, we demonstrate the pertinence of our approach by simulating different processor arrays. The superior performance of the generated simulators compared to existing simulators and simulator generation approaches is shown.

关键词： Parallel processing systems

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Accurate and scalable simulation of network of heterogeneous sensor devices

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JOURNAL OF SIGNAL PROCESSING systems FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2008年第2期50卷 115-136页

作者： Wen, Ye Gurun, Selim Chohan, Navraj Wolski, Rich Krintz, Chandra Univ Calif Santa Barbara Santa Barbara CA 93106 USA

simulation is an important tool to study and analyze sensor networks. Prior work in sensor network simulation focuses on homogeneous devices. In this paper, we present a system that performs scalable and accurate simulation of a network of heterogeneous sensor devices, including both Stargate intermediate level devices and mote devices. We study accuracy, performance, and scalability of our system. The results show that we can achieve accurate functional behavior for both standalone Stargate simulation and ensemble simulation of a Stargate and motes. For motes, we have less than 4.06% cycle count error for all benchmarks and for Stargate, we have less than 10% error for most benchmarks, and less than 12.5% error for all benchmarks. We also achieve less than 3.6% error for all benchmarks when simulating an ensemble of Stargate and motes. Our system is also more scalable than prior work. We can simulate 160 sensor nodes in real time speed and 2,048 sensor nodes with ten times slowdown on a 16-node cluster.

关键词： simulation sensor network intermediate sensor node scalability

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Hardware/software specialization through aspects: The LARA approach

Hardware/software specialization through aspects: The LARA a...

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2012 international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2012

作者： Cardoso, João M. P. Carvalho, Tiago Teixeira, João Diniz, Pedro C. Goncalves, Fernando Petrov, Zlatko Departamento de Engenharia Informática R. Roberto Frias s/n 4200-465 Porto Portugal INESC-ID Lisboa Portugal CoreWorks S.A. Lisboa Portugal Honeywell International S.r.o. Czech Republic

ISBN: (纸本)9781467322973

LARA is a programming language being developed to complement application code in a host programming language with instrumentation code, for monitoring, logging, and debugging, user's knowledge about specific characteristics of the application, non-functional requirements, and compiler, mapping and synthesis strategies to guide/control design-flows, especially the ones used to map computations to FPGA-based systems. This paper shows how the aspect-oriented approach provided by LARA allows developers to specify complementary program information that can be used by LARA aware design-flows to promote customized FPGA-based software/hardware implementations. Program and compiler/mapping specialization take advantage of specific properties of applications to optimize and customize specific application modules and software/hardware implementations, e.g., according to usage contexts. We illustrate the concept using a hotspot function from a real-life, industrial, application. The results show the importance of program specialization in deriving hardware/software implementations with higher-performance. © 2012 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Portable Cost modeling for Auto-Vectorizers 27

Portable Cost Modeling for Auto-Vectorizers

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IEEE 27th international Symposium on modeling, Analysis, and simulation of computer and Telecommunication systems (MASCOTS)

作者： Pohl, Angela Cosenza, Biagio Juurlink, Ben Tech Univ Berlin Embedded Syst Architecture Berlin Germany

ISBN: (纸本)9781728149516;9781728149509

Compiler optimization passes employ cost models to determine if a code transformation will yield performance improvements. When this assessment is inaccurate, compilers apply transformations that are not beneficial, or refrain from applying ones that would have improved the code. We analyze the accuracy of the cost models used in LLVM's and GCC's vectorization passes for two different instruction set architectures. In general, speedup is over-estimated, resulting in mispredictions and a weak to medium correlation between predicted and actual performance gain. We therefore propose a novel cost model that is based on a code's intermediate representation with refined memory access pattern features. Using linear regression techniques, this platform independent model is fitted to an AVX2 and a NEON hardware. Results show that the fitted model significantly improves the correlation between predicted and measured speedup (AVX2: +52% for training data, +13% for validation data), as well as the number of mispredictions (NEON: -15 for training data, -12 for validation data) for more than 80 code patterns.

关键词： Optimization Analytical models Predictive models Hardware Benchmark testing Correlation Neon

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Work-in-Progress: Multiple Alignment of Packet Sequences for Efficient Communication in a Many-Core Neuromorphic System

Work-in-Progress: Multiple Alignment of Packet Sequences for...

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international conference on Compilers, architectures and Synthesis for embedded systems (CASES)

作者： Urgese, Gianvito Peres, Luca Barchi, Francesco Macii, Enrico Acquaviva, Andrea Politecn Torino Dept Control & Comp Engn I-10129 Turin Italy

ISBN: (纸本)9781538655641

In this era, the requirement of high-performance computing at low power cost can be met by the parallel execution of an application on a large number of programmable cores. Emerging many-core architectures provide dense interconnection fabrics leading to new communication requirements. In particular, the effective exploitation of synchronous and asynchronous channels for fast communication from/to internal cores and external devices is a key issue for these architectures. In this paper, we propose a methodology for clustering sequential commands used for configuring the parallel execution of tasks on a globally asynchronous locally synchronous multi-chip many-core neuromorphic platform. With the purpose of reducing communication costs and maximise the exploitation of the available communication bandwidth, we adapted the Multiple Sequence Alignment (MSA) algorithm for clustering the unicast streams of packets used for the configuration of each core so as to generate a coherent multicast stream that configures all cores at once. In preliminary experiments, we demonstrate how the proposed method can lead up to a 97% reduction in packet transmission thus positively affecting the overall communication cost.

关键词： Unicast computer architecture Neuromorphics Clustering algorithms Task analysis Routing Computational modeling

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RTOS-Aware modeling of embedded Hardware/Software systems

RTOS-Aware Modeling of Embedded Hardware/Software Systems

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IEEE international conference on computer Design

作者： Mueller, Matthias Gerlach, Joachim Rosenstiel, Wolfgang Univ Tubingen Wilhelm Schickard Inst Comp Sci Dept Comp Engn D-72074 Tubingen Germany

ISBN: (纸本)9781424489350

Modern embedded systems such as mobile phones or electronic control units from the automotive domain include a bulk of highly complex and highly interacting functions. Due to several reasons-flexibility and cost effectiveness may be the most important ones-a large and permanently growing part of these functions is implemented in software. This comes along with the demand for more and more processing power, paving the way for multi-core architectures, and widespread use of real-time operating systems. Application software implementation and operating system configuration strongly influence the overall system behavior. Design methodologies for such complex systems, consisting of hardware, software and real-time operating systems, must provide an early, model-based view on the overall system. The approach described in this paper enables automatic generation of system-level models of complex systems from abstract application specifications. Additionally, a compiler-based technique allows automatic calculation of precise software runtime information and annotation of the generated model. The resulting system-level model facilitates early exploration of systems on high level of abstraction, taking into account functional and temporal characteristics of hardware, software and real-time operating system. A key feature of the approach is its high accuracy, which is shown by applying it to an industrial application from the automotive domain.

关键词： RTOS-aware modeling compiler-based technique embedded hardware-software system embedded systems hardware-software codesign operating systems (computers) program compilers system-level model

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embedded computer systems: architectures, modeling, and simulation 1

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丛书名： Lecture Notes in computer Science

1000年

ISBN: (数字)9783540705505

ISBN: (纸本)9783540705499

This book constitutes the refereed proceedings of the 8th international Workshop on systems, architectures, modeling, and simulation, SAMOS 2008, held in Samos, Greece, in July 2008. The 24 revised full papers presented together with a contamplative keynote and additional papers of two special workshop sessions were carefully reviewed and selected from 62 submissions. The papers are organized in topical sections on architecture, new frontiers, SoC, application specific contributions, system level design for heterogeneous systems, programming multicores, sensors and sensor networks; and systems modeling and design.

关键词： computer System Implementation computer Communication Networks Theory of Computation computer Hardware Processor architectures System Performance and Evaluation

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Design-Space Reduction for Architectural Optimization of Automotive embedded systems 17

Design-Space Reduction for Architectural Optimization of Aut...

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2015 IEEE 17th international conference on High Performance Computing and Communications (HPCC)

作者： Zhang, Xinhai Feng, Lei Chen, De-Jiu Torngren, Martin KTH Royal Inst Technol Dept Machine Design Stockholm Sweden

ISBN: (纸本)9781479989379

A key decision for the synthesis of automotive embedded systems is the allocation of application software components to ECUs. Design Space Exploration (DSE) supports the decision by automatically characterizing and evaluating a large number of possible design alternatives, and thereby suggesting the optimal ones. A primary challenge for applying DSE methods to support this decision is to reduce the computation time of the DSE process while maintaining the generality and optimality. This paper exploits legacy system architectures and the AUTOSAR standard to preemptively reduce the design space, because both artifacts limit the flexibility of certain design variables. A new DES formulation incorporating the constraints of the legacy system architectures and the AUTOSAR standard is proposed in this paper. Computation result shows a large reduction of the computation time comparing to traditional modeling and formulations. The scalability of our method is also analyzed by testing it on a set of random problem instances.

关键词： Aging Automotive engineering computer architecture embedded systems Resource management Standards systems architecture

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Automated Design Flow for Coarse-Grained Reconfigurable Platforms: an RVC-CAL Multi-Standard Decoder Use-Case 14

Automated Design Flow for Coarse-Grained Reconfigurable Plat...

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international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Sau, C. Raffo, L. Palumbo, F. Bezati, E. Casale-Brunet, S. Mattavelli, M. Univ Cagliari Dipartimento Ingn Elettr & Elettron I-09124 Cagliari Italy Univ Sassari Dipartimento Sci Polit & Comunicaz & Ingn Informa I-07100 Sassari Italy Ecole Polytech Fed Lausanne EPFL SCI STI MM CH-1015 Lausanne Switzerland

ISBN: (纸本)9781479937707

Specialized hardware infrastructures for efficient multi-application runtime reconfigurable platforms require to address several issues. The higher is the system complexity, the more error prone and time consuming is the entire design flow. Moreover, system configuration along with resource management and mapping are challenging, especially when runtime adaptivity is required. In order to address these issues, the Reconfigurable Video Coding Group within the MPEG group has developed the MPEG RMC standards ISO/IEC 23001-4 and 23002-4, based on the dataflow Model of Computation. In this paper, we propose an integrated design flow, leveraging on Xronos, TURNUS, and the Multi-Dataflow Composer tool, capable of automatic synthesis and mapping of reconfigurable systems. In particular, an RVC MPEG-4 SP decoder and the RVC Intra MPEG-4 SP decoder have been implemented on the same coarse-grained reconfigurable platform, targeting a Xilinx Virtex 5 330 FPGA board. Results confirmed the potentiality of the approach, capable of completely preserving the single decoders functionality and of providing, in addition, considerable power/area benefits with respect to the parallel implementation of the considered decoders on the same platform.

关键词： Design flow decoders configurability Platform MAPPING(MATHEMATICAL) Regional vital capacity REACTOR VOLUME CONTROL computer-Aided Design Moving Pictures Experts Group MPEG 4 Standard management of resources

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High level modeling and validation methodologies for embedded systems: Bridging the productivity gap 16

High level modeling and validation methodologies for embedde...

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16th international conference on VLSI Design/2nd international conference on embedded systems Design

作者： Shukla, SK Edwards, SA Talpin, JP Gupta, RK Virginia Tech Blacksburg VA 24061 USA

ISBN: (纸本)0769518680

In this tutorial, we cover the most recent developments in system level design languages and models of computation which influence the choices of modeling paradigms and languages, interoperability of design components created with different modeling styles and languages, synchronous vs. asynchronous system design, and corresponding methodologies based on de-synchronization which leads to new embedded hardware/software co-design methods, formal validation of system level design of embedded hardware/software systems, and component composition frameworks that allows reuse of intellectual properties, and provides efficient simulation and validation environments. © 2003 IEEE.

关键词： Computational modeling computer networks Design engineering embedded computing embedded system Handheld computers Hardware design languages Pervasive computing Productivity System-level design

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